CN104465803A - Back emitter heterojunction solar cell and manufacturing method thereof - Google Patents
Back emitter heterojunction solar cell and manufacturing method thereof Download PDFInfo
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- CN104465803A CN104465803A CN201410677687.2A CN201410677687A CN104465803A CN 104465803 A CN104465803 A CN 104465803A CN 201410677687 A CN201410677687 A CN 201410677687A CN 104465803 A CN104465803 A CN 104465803A
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- 238000004519 manufacturing process Methods 0.000 title abstract 2
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 26
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 12
- 229910052709 silver Inorganic materials 0.000 claims abstract description 11
- 239000004332 silver Substances 0.000 claims abstract description 11
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052751 metal Inorganic materials 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 8
- 239000012528 membrane Substances 0.000 claims description 36
- 239000010408 film Substances 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 12
- 238000002360 preparation method Methods 0.000 claims description 10
- 239000002002 slurry Substances 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 7
- 238000002161 passivation Methods 0.000 claims description 7
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 7
- 238000007650 screen-printing Methods 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 5
- 239000013081 microcrystal Substances 0.000 claims description 5
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 3
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 3
- 238000005240 physical vapour deposition Methods 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 230000008595 infiltration Effects 0.000 claims description 2
- 238000001764 infiltration Methods 0.000 claims description 2
- 239000010409 thin film Substances 0.000 claims description 2
- 238000005286 illumination Methods 0.000 abstract description 3
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 238000010521 absorption reaction Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 230000031700 light absorption Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
- H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
- H01L31/202—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic System
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention discloses a back emitter heterojunction solar cell. The back emitter heterojunction solar cell comprises a substrate layer with a monocrystalline silicon wafer with the thickness ranging from 180 microns to 220 microns serving as the substrate. An amorphous silicon film intrinsic layer with the thickness ranging from 3 nm to 8 nm, a conducting medium layer with the thickness ranging from100 nm to 140 nm and a silver paste layer are sequentially arranged on the back side of the substrate layer from inside to outside. An amorphous silicon film intrinsic layer with the thickness ranging from 3 nm to 8 nm, a heavily-doped layer with the thickness ranging from 5 nm to 15 nm, a conducting film layer with the thickness ranging from 80 nm to 120 nm and a metal electrode are sequentially arranged on the front side of the substrate layer from inside to outside. Correspondingly, the invention further discloses a manufacturing method of the back emitter heterojunction solar cell. Because an emitter is manufactured on the back side of the solar cell, the front side of the solar cell receives illumination through the heavily-doped layer structure, and therefore the emitter is prevented from absorbing sunlight directly; the thickness of the emitter can be properly increased, which is beneficial for increasing the built-in potential of the cell, increasing the open-circuit voltage of the cell and effectively improving the overall performance of the cell.
Description
Technical field
The present invention relates to technical field of solar cells, especially a kind of emitters on back side heterojunction solar cell and preparation method.
Background technology
Silicon heterojunction solar battery is that deposition of amorphous silicon films is as emitter in crystalline silicon substrate, and the thickness of emitter directly determines the quality of battery performance, increases emitter thickness and contributes to increasing battery built, improve charge carrier transport efficiency.One of key factor that but light regime is also solar cell to be considered, the absorption of thicker emitter to incident light is more, make to enter the light that battery effectively absorbs less, be unfavorable for the lifting of battery efficiency, therefore, between emitter thickness and Built-in potential and optical efficiency utilize, be necessary not only increasing battery internal electric field, but also avoiding emitter to reach balance in the too much absorption of light, thus effectively improve the overall performance of solar cell.
Summary of the invention
The technical problem to be solved in the present invention is: overcome the deficiency in prior art, a kind of emitters on back side heterojunction solar cell and preparation method are provided, when emitter is thicker, both battery Built-in potential had been increased, avoid again emitter to the too much absorption of light, improve the open circuit voltage of battery, effectively improve cell integrated performance.
The technical solution adopted for the present invention to solve the technical problems is: a kind of emitters on back side heterojunction solar cell, comprise and select thickness to be that the monocrystalline silicon piece of 180 ~ 220 μm is as the substrate layer of substrate, the described base layer back side has the amorphous silicon membrane intrinsic layer that thickness is 3 ~ 8nm from inside to outside successively, thickness is the emitter layer of 15 ~ 25nm, thickness is conducting medium layer and the silver slurry layer of 100 ~ 140nm, the front of substrate layer has the amorphous silicon membrane intrinsic layer that thickness is 3 ~ 8nm from inside to outside successively, thickness is 5 ~ 15nm heavily doped layer, thickness is conductive membrane layer and the metal electrode of 80 ~ 120nm, there is a passivation layer and a tunnel contact layer between conducting medium layer and silver slurry layer, described tunnel contact layer is made up of microcrystal silicon.
Described substrate layer material is n type single crystal silicon sheet or p type single crystal silicon sheet.
Correspondingly, described emitter layer material therefor is the silica-base film contrary with substrate layer doping type; Described heavily doped layer material therefor is the silica-base film identical with substrate layer conduction type.
Described conducting medium layer material is the non-infiltration type film that TCO thin film or conductivity are superior.
Preferably, the thickness of described substrate layer is 200 μm, and the thickness of amorphous silicon membrane intrinsic layer is 5nm, and the thickness of emitter layer is 20nm, and the thickness of conducting medium layer is 120nm, and the thickness of heavily doped layer is 10nm, and the thickness of conductive membrane layer is 100nm.
The preparation method of above-mentioned emitters on back side heterojunction solar cell, has following steps:
1) select thickness to be the substrate layers of 180 ~ 220 μm of monocrystalline silicon pieces as substrate, and standard RCA clean is carried out to substrate layer surface, and adopt HF process one minute;
2) substrate layer front after treatment adopts PECVD deposit thickness to be the amorphous silicon membrane intrinsic layer of 3 ~ 8nm, is that 5 ~ 15nm heavily doped layer is as front-surface field in surface deposition a layer thickness of amorphous silicon membrane intrinsic layer;
3) magnetron sputtering mode deposit thickness is adopted to be the conductive membrane layer of 80 ~ 120nm on heavily doped layer surface;
4) adopt PECVD deposit thickness to be the amorphous silicon membrane intrinsic layer of 3 ~ 8nm at the substrate layer back side, on amorphous silicon membrane intrinsic layer, deposit thickness is the emitter layer of 15 ~ 25nm, deposit thickness is the passivation layer of 15 ~ 35nm and thickness is the tunnel contact layer of 10 ~ 30nm, and described tunnel contact layer is made up of microcrystal silicon;
5) adopt PVD or CVD method to prepare again conducting medium layer that thickness is 100 ~ 140nm;
6) on conductive membrane layer, adopt screen printing technique to prepare metal electrode, on conducting medium layer, silver slurry layer is prepared in low temperature silk screen printing;
7) finally in N2 atmosphere, above-mentioned solar cell is dried, complete the preparation of emitters on back side heterojunction solar cell.
The invention has the beneficial effects as follows: the present invention adopts and prepares emitter at back of solar cell, front accepts illumination by heavily doped layer structure, thus avoid the direct absorption of emitter to light, suitably can increase the thickness of emitter, contribute to increasing battery built-in potential, improve the open circuit voltage of battery, effectively improve the overall performance of battery.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the structural representation of emitters on back side heterojunction solar cell of the present invention.
Fig. 2 is the preparation flow figure of emitters on back side heterojunction solar cell of the present invention.
1-substrate layer in figure, 2-amorphous silicon membrane intrinsic layer, 3-emitter layer, 4-conducting medium layer, 5-silver slurry layer, 6-heavily doped layer, 7-conductive membrane layer, 8-metal electrode.
Embodiment
The present invention is further illustrated with preferred embodiment by reference to the accompanying drawings now.These accompanying drawings are the schematic diagram of simplification, only basic structure of the present invention are described in a schematic way, and therefore it only shows the formation relevant with the present invention.
A kind of emitters on back side heterojunction solar cell as shown in Figure 1, comprise the substrate layer 1 selecting N-shaped monocrystalline silicon piece to make, the thickness of substrate layer 1 is 200 μm, resistivity is 5 Ω, the back side of described substrate layer 1 has the amorphous silicon membrane intrinsic layer as buffering passivation layer from inside to outside successively, material is the emitter layer of the doped silicon based film of p-type, material is the conducting medium layer of ZnO film and the silver slurry layer of employing low temperature silk screen printing, there is a passivation layer and a tunnel contact layer be made up of microcrystal silicon between conducting medium layer and silver slurry layer, wherein, the thickness of amorphous silicon membrane intrinsic layer is 5nm, the thickness of emitter layer is 20nm, the thickness of conducting medium layer is 120nm, the thickness of passivation layer is 15nm, the thickness of tunnel contact layer is 10nm.
The front of substrate layer has amorphous silicon membrane intrinsic layer, heavily doped layer, conductive membrane layer and metal electrode as front-surface field from inside to outside successively, wherein, amorphous silicon membrane intrinsic layer be located at the identical of substrate layer 1 back side, thickness is similarly 5nm, heavily doped layer material is n+ type heavy doping film, thickness is 10nm, and conductive membrane layer material selection ITO type film, thickness is 100nm.
The preparation method of above-mentioned emitters on back side heterojunction solar cell, see accompanying drawing 2, has following steps:
1) select thickness be the N-shaped monocrystalline silicon piece of 200 μm as the substrate layer 1 of substrate, standard RCA clean is carried out to substrate layer 1 surface, and adopts HF to process one minute to substrate layer 1;
2) substrate layer 1 front after treatment, adopts PECVD deposit thickness to be the amorphous silicon membrane intrinsic layer 2 of 5nm, is then that the n+ type heavily doped layer 6 of 10nm is as front-surface field in surface deposition a layer thickness of amorphous silicon membrane intrinsic layer 2;
3) adopt magnetron sputtering mode deposit thickness to be the transparent ITO conductive membrane layer 7 of 100nm on heavily doped layer 6 surface;
4) adopt PECVD deposit thickness to be the amorphous silicon membrane intrinsic layer 2 of 5nm at substrate layer 1 back side, on amorphous silicon membrane intrinsic layer 2, deposit thickness is that the doped silicon based film of p-type of 20nm is as emitter layer 3, deposit thickness is the passivation layer of 15 ~ 35nm and thickness is the tunnel contact layer of 10 ~ 30nm, and described tunnel contact layer is made up of microcrystal silicon;
5) adopting PVD method to prepare thickness is again that the ZnO film of 120nm is as conducting medium layer 4;
6) on conductive membrane layer 7, adopt screen printing technique to prepare metal electrode 8, on conducting medium layer 4, silver slurry layer 5 is prepared in low temperature silk screen printing;
7) finally in N2 atmosphere, above-mentioned solar cell is dried, complete the preparation of emitters on back side heterojunction solar cell.
The thickness of traditional emitter layer 3, is generally less than 10nm, and being unfavorable for increases battery built-in potential, improves the open circuit voltage of battery.In the present invention, emitter layer 3 preferably ideal thickness is 20nm, emitter layer 3 is arranged on the back side of monocrystalline silicon piece, therefore when increasing the thickness of emitter layer 3, both can ensure sufficient built-in potential and pull transporting of efficient carrier, can avoid again the absorption loss water that emitter layer thicker in traditional structure 3 pairs of incident lights cause, this feature significantly improves the efficiency to light regime in high-efficiency battery; Simultaneously, increase emitter layer 3 thickness, because adopt PECVD technology or other gas phase deposition technologies to prepare emitter layer 3, its doping efficiency is always lower, increase emitter layer 3 thickness becomes a difficult problem more thorny in hetero-junction solar cell, so can ensure the impact do not caused when dopant ratio is lower Voc;
The present invention adopts and prepares emitter layer 3 at back of solar cell, front accepts illumination by heavily doped layer 6 structure, thus avoid the direct absorption of emitter layer 3 to light, therefore the thickness of emitter layer 3 can suitably be increased, contribute to increasing battery built-in potential, improve the open circuit voltage of battery, effectively improve the overall performance of battery.
Above-described embodiment is only for illustrating technical conceive of the present invention and feature; its object is to person skilled in the art can be understood content of the present invention and be implemented; can not limit the scope of the invention with this; all equivalences done according to Spirit Essence of the present invention change or modify, and all should be encompassed in protection scope of the present invention.
Claims (7)
1. an emitters on back side heterojunction solar cell, comprise and select thickness to be that the monocrystalline silicon piece of 180 ~ 220 μm is as the substrate layer (1) of substrate, it is characterized in that: described base layer (1) back side has the amorphous silicon membrane intrinsic layer (2) that thickness is 3 ~ 8nm from inside to outside successively, thickness is the emitter layer (3) of 15 ~ 25nm, thickness is conducting medium layer (4) and the silver slurry layer (5) of 100 ~ 140nm, the front of substrate layer (1) has the amorphous silicon membrane intrinsic layer (2) that thickness is 3 ~ 8nm from inside to outside successively, thickness is 5 ~ 15nm heavily doped layer (6), thickness is conductive membrane layer (7) and the metal electrode (8) of 80 ~ 120nm, there is a passivation layer and a tunnel contact layer between conducting medium layer (4) and silver slurry layer (5), described tunnel contact layer is made up of microcrystal silicon.
2. emitters on back side heterojunction solar cell according to claim 1, is characterized in that: described substrate layer (1) material is n type single crystal silicon sheet or p type single crystal silicon sheet.
3. emitters on back side heterojunction solar cell according to claim 2, is characterized in that: described emitter layer (3) material therefor is the silica-base film contrary with substrate layer (1) doping type.
4. emitters on back side heterojunction solar cell according to claim 2, is characterized in that: described heavily doped layer (6) material therefor is the silica-base film identical with substrate layer (1) conduction type.
5. emitters on back side heterojunction solar cell according to claim 1, is characterized in that: described conducting medium layer (4) material is the non-infiltration type film that TCO thin film or conductivity are superior.
6. emitters on back side heterojunction solar cell according to claim 1, it is characterized in that: the thickness of described substrate layer (1) is 200 μm, the thickness of amorphous silicon membrane intrinsic layer (2) is 5nm, the thickness of emitter layer (3) is 20nm, the thickness of conducting medium layer (4) is 120nm, the thickness of heavily doped layer (6) is 10nm, and the thickness of conductive membrane layer (7) is 100nm.
7. a preparation method for emitters on back side heterojunction solar cell described in claim 1, is characterized in that: have following steps:
1) select thickness to be the substrate layers (1) of 180 ~ 220 μm of monocrystalline silicon pieces as substrate, and standard RCA clean is carried out to substrate layer (1) surface, and adopt HF process one minute;
2) substrate layer (1) front after treatment adopts PECVD deposit thickness to be the amorphous silicon membrane intrinsic layer (2) of 3 ~ 8nm, is that 5 ~ 15nm heavily doped layer (6) is as front-surface field in surface deposition a layer thickness of amorphous silicon membrane intrinsic layer (2);
3) adopt magnetron sputtering mode deposit thickness to be the conductive membrane layer (7) of 80 ~ 120nm on heavily doped layer (6) surface;
4) adopting PECVD deposit thickness to be the amorphous silicon membrane intrinsic layer (2) of 3 ~ 8nm at substrate layer (1) back side, is the emitter layer (3) of 15 ~ 25nm at the upper deposit thickness of amorphous silicon membrane intrinsic layer (2);
5) prepare in upper PVD or the CVD method of adopting of emitter layer (3) the conducting medium layer (4) that thickness is 100 ~ 140nm;
6) prepare metal electrode (8) at the upper screen printing technique that adopts of conductive membrane layer (7), prepare silver slurry layer (5) in the upper low temperature silk screen printing of conducting medium layer (4);
7) finally in N2 atmosphere, above-mentioned solar cell is dried, complete the preparation of emitters on back side heterojunction solar cell.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410677687.2A CN104465803A (en) | 2014-11-21 | 2014-11-21 | Back emitter heterojunction solar cell and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410677687.2A CN104465803A (en) | 2014-11-21 | 2014-11-21 | Back emitter heterojunction solar cell and manufacturing method thereof |
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| CN104465803A true CN104465803A (en) | 2015-03-25 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105870215A (en) * | 2016-04-28 | 2016-08-17 | 乐叶光伏科技有限公司 | Rear surface passivation contact battery electrode structure and preparation method thereof |
| CN115000243A (en) * | 2022-05-27 | 2022-09-02 | 中国科学院电工研究所 | Preparation method of crystalline silicon heterojunction solar cell |
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|---|---|---|---|---|
| CN101142689A (en) * | 2005-03-14 | 2008-03-12 | Q-电池股份公司 | Solar cell |
| CN102842634A (en) * | 2012-08-16 | 2012-12-26 | 常州天合光能有限公司 | Back emitting electrode heterojunction solar cell and preparation method |
| EP2669952A1 (en) * | 2012-06-01 | 2013-12-04 | Roth & Rau AG | Photovoltaic device and method of manufacturing same |
-
2014
- 2014-11-21 CN CN201410677687.2A patent/CN104465803A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101142689A (en) * | 2005-03-14 | 2008-03-12 | Q-电池股份公司 | Solar cell |
| EP2669952A1 (en) * | 2012-06-01 | 2013-12-04 | Roth & Rau AG | Photovoltaic device and method of manufacturing same |
| CN102842634A (en) * | 2012-08-16 | 2012-12-26 | 常州天合光能有限公司 | Back emitting electrode heterojunction solar cell and preparation method |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105870215A (en) * | 2016-04-28 | 2016-08-17 | 乐叶光伏科技有限公司 | Rear surface passivation contact battery electrode structure and preparation method thereof |
| CN115000243A (en) * | 2022-05-27 | 2022-09-02 | 中国科学院电工研究所 | Preparation method of crystalline silicon heterojunction solar cell |
| CN115000243B (en) * | 2022-05-27 | 2023-11-21 | 中国科学院电工研究所 | Preparation method of crystalline silicon heterojunction solar cell |
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