CN104465315A - Chip separation method for 3D stacked chip encapsulator - Google Patents

Chip separation method for 3D stacked chip encapsulator Download PDF

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Publication number
CN104465315A
CN104465315A CN201310439837.1A CN201310439837A CN104465315A CN 104465315 A CN104465315 A CN 104465315A CN 201310439837 A CN201310439837 A CN 201310439837A CN 104465315 A CN104465315 A CN 104465315A
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chip
grinding
separation method
stacked die
die packaging
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CN104465315B (en
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林晓玲
章晓文
陆裕东
苏菊花
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Fifth Electronics Research Institute of Ministry of Industry and Information Technology
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Fifth Electronics Research Institute of Ministry of Industry and Information Technology
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/26—Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement

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  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Sampling And Sample Adjustment (AREA)

Abstract

The invention discloses a chip separation method for a 3D stacked chip encapsulator. The method comprises the steps that acoustic scanning micro-detection is conducted on the internal structure of a 3D stacked chip encapsulated ULSI sample to determine a region to be ground and the area of the region to be ground; the 3D stacked chip encapsulated ULSI sample is fixed to a grinding table through hot molten wax; grinding is conducted, wherein a grinding drill bit, the grinding intensity and the grinding direction are selected according to the area of the ground region, an encapsulating material and chips are removed, and the region is ground to a protective layer covering the surface of a target chip; a chemical etching method is adopted to remove the protective layer. According to the chip separation method, grinding is used as a main mode, and chemical etching is used as an auxiliary mode; a specific local region is removed through grinding, and the internal structure of the lower chips and bonding wires of the lower chips are not damaged; the protective layer covering the surface of the target chip or chip binder is removed through the chemical etching method, and then the target chip is exposed; the internal structure of the obtained target chip and the bonding wire on the target chip are complete and not damaged, and therefore subsequent electrical logging analysis is facilitated.

Description

The chip separation method of 3D Stacked Die Packaging device
Technical field
The present invention relates to chip separation method, particularly relate to a kind of chip separation method of 3D Stacked Die Packaging device.
Background technology
3D Stacked Die Packaging technology adopts solid space to realize multichip interconnection, under the prerequisite not changing package body sizes, in same packaging body, utilizes the mode such as wire bonding or through-silicon-via TSV interconnection to stack two or more chip in vertical direction.3D Stacked Die Packaging very lagre scale integrated circuit (VLSIC) (ULSI), while raising circuit performance, significantly reduces the power consumption of circuit, becomes the new lover of high performance device.
At present, for brand-new 3D ULSI product, sometimes by destructive physical analysis, check its internal structure, this needs the multilayer chiop of 3D ULSI inside successively to expose, and interior visual inspection is carried out to the internal structure of each layer, to verify whether its internal material, design and structure meet applicable design document and require or other regulation requirement.
And to using and occurring the 3D ULSI that lost efficacy, need first to utilize defect location technological orientation to defect at which layer chip concrete, then this layer of chip is come out carry out physical analysis, morphology observation analysis and failure mechanism confirmation are carried out to rejected region.When defect is on top layer chip, one chip can be utilized to encapsulate the separation method of ULSI, namely realize removing to the corrosiveness of plastic encapsulant by corrosive liquids such as traditional chemical corrosion method nitric acid, or by mechanical Kaifeng method file or small milling machine, pottery or metallic packaging cover plate are levered up and remove.These two kinds of sample treatments can realize the removal of the multiple encapsulating materials such as Plastic Package, ceramic packaging, packed by metal casing; But 3D Stacked Die Packaging ULSI contains two or more chip, when defect is on non-top layer chip, except the encapsulating material getting rid of ULSI, also need other chip on objective chip to remove to expose objective chip and to analyze; In addition, 3D Stacked Die Packaging ULSI, except encapsulating material, also has other chip and chip chamber binding agent.And, after the non-top layer chip of 3D ULSI comes out, may need to carry out defect location again.The existing Detection Techniques for chip-scale defect, as mechanical probes, light launch microtechnic, infrared thermal imagery method, liquid crystal Method, electron beam tester etc., all need to add that certain voltage bias is to reappear failure phenomenon to device, this just requires that the electrical property of device is good.Therefore, when the exposure of non-top layer chip is carried out to the 3D Stacked Die Packaging ULSI lost efficacy, must ensure while removal encapsulating material, upper strata chip etc., guarantee that the electrical property of objective chip layer is good, bonding welding pad, bonding wire etc. namely on the internal structure of objective chip layer, chip all must be intact not impaired.
Because chip material is silicon (Si), cannot remove with chemical corrosion method, even soak with hydrofluoric acid (HF), can not by its erosion removal.And mechanical Kaifeng method is mainly used for the Kaifeng of ceramic cover plate encapsulation or metal-back packaging, by grinding or prize the method combined, package casing material is removed, expose encapsulation inner chamber, but the method cannot to encapsulation cavity in chip carry out Local treatment and reserved lead can't harm.
Therefore, traditional chemical corrosion or mechanical Kaifeng method cannot meet the demand that the non-top layer chip makes physical of 3D Stacked Die Packaging ULSI is analyzed.How to be removed by the chip on objective chip, be the thorny problem run in 3D Stacked Die Packaging ULSI failure analysis/physical analysis process.
Summary of the invention
Based on this, the object of this invention is to provide a kind of chip separation method of 3D Stacked Die Packaging device.
The concrete technical scheme solved the problems of the technologies described above is as follows:
A chip separation method for 3D Stacked Die Packaging device, comprises the steps:
(1) abrasive areas and area thereof is determined
The internal structure of acoustic scan micro-detection 3D Stacked Die Packaging ULSI sample, as the chip number of plies, the chip area size of device inside, and determines abrasive areas and area thereof;
(2) fixing
With hot melt wax, 3D Stacked Die Packaging ULSI sample is fixed on grinding table;
(3) grind
According to step (1) determined abrasive areas and area thereof, select abrasive drill, grinding dynamics, the degree of depth and speed, remove encapsulating material and the chip of abrasive areas, be ground to the protective layer of objective chip surface coverage; In described grinding: if milling area is 3-6mm, abrasive drill is 1mm, if milling area is 7-15mm, abrasive drill is 3mm, if milling area is for being greater than 15mm, abrasive drill is 5mm;
(4) chemical corrosion
Adopt chemical corrosion method, the protective layer described in removal step (3).
Wherein in some embodiments, step (3)
Wherein in some embodiments, described in be ground to stepping grinding, namely stepping applies grinding dynamics, and for same material, time initial, dynamics is comparatively large, example: the 1/4-1/2 once grinding total grinding thickness, and along with the carrying out of grinding, dynamics reduces gradually.Grinding dynamics refers to and arranges the thickness of grinding downwards by dialing knob and apply corresponding power; Grinding dynamics determines the thickness that each grinding is removed.
Wherein in some embodiments, to be the described grinding direction of step (3) be the grinding dynamics described in step (3): XY direction or X-direction or Y-direction.
Wherein in some embodiments, also calibration is comprised: described calibration is the thickness by measuring abrasive areas difference on the surface in fixing described in step (2) and the grinding described in step (3), regulate the height of grinding table, to adjust the evenness of abradant surface simultaneously.
Wherein in some embodiments, described chemical corrosion method is: adopt concentrated sulfuric acid corrosion.
Wherein in some embodiments, also comprise monitoring: the progress utilizing metallomicroscope monitoring step (3) described grinding and step (4) described chemical corrosion.
The chip separation method tool of a kind of 3D Stacked Die Packaging device of the present invention has the following advantages and beneficial effect:
(1) in chip separation method of the present invention, based on grinding technique, chemical corrosion method is auxiliary; Region sample preparation grinding technique is mainly utilized to realize the grinding of micron-sized region, encapsulation inside cavity can be deep into, grinding de-layer is carried out for specific localized areas (as only to the upper area of chip area size), at removal certain layer of chip and encapsulating material, do not damage lower layer chip internal structure and bonding wire thereof simultaneously; Wherein, in described grinding: if milling area is 3-6mm, abrasive drill is 1mm, if milling area is 7-15mm, abrasive drill is 3mm, if milling area is for being greater than 15mm, abrasive drill is 5mm; Be aided with protective layer that objective chip covers by chemical corrosion method on the surface again or chip attach agent is removed, make that objective chip surface is clear comes out; The objective chip come out, the bonding wires on internal structure and chip etc. are complete not impaired, and namely electrical property is good, facilitates the follow-up electrical logging analyze to this layer of chip;
(2), in chip separation method of the present invention, adopt the method for hot melt wax fixed sample to avoid when adopting clamp to fix to being forced to of causing of encapsulation inside chip and break or warpage damage, make the thickness of sample during grinding, size unfettered;
(3) in chip separation method of the present invention, adopt multiple spot thickness measure, coordinate the calibration steps of adjustment grinding table to make lapped face smooth, avoid unnecessary inclination grinding damage.
(4) in chip separation method of the present invention, also adopt the color change of each material of metallography microscope sem observation in process of lapping to realize Real-Time Monitoring grinding progress, adjust grinding dynamics accordingly, not only break away from the dependence to sample size, also guarantee that the size of abrasive areas, the degree of depth are controlled further, avoid overmastication or grinding deficiency;
(5) chip separation method of the present invention achieves the successively exposure of 3D Stacked Die Packaging device inside multilayer chiop, solve the non-top layer chip makes physical of 3D Stacked Die Packaging device and analyze difficult problem, the failure analysis of the ineffective part of some 3D Stacked Die Packaging also can be made to be completed smoothly, determine its final failure cause and mechanism, prevent repeating of inefficacy, significant to the reliability improving device.
Accompanying drawing explanation
Fig. 1 is the techniqueflow chart of the memory chips separation method described in embodiment 1;
Fig. 2 is the internal structure schematic diagram of the memory described in embodiment 1; Wherein, 1 is ground floor chip, and 2 is second layer chip;
The local pattern metallomicroscope figure that Fig. 3 is second layer chip in the memory described in embodiment 1;
Fig. 4 is second layer chip local pattern in the memory described in embodiment 1 and lead-in wire pattern metallomicroscope figure.
Embodiment
Below with reference to specific embodiment, the present invention will be further described.
Wherein, the micro-detection of acoustic scan described in following embodiment refers to ultrasonic scanning microscope, is called for short C-SAM;
ALLIED company of the U.S. of described hot melt wax manufacturer.
Embodiment 1
The present embodiment is to include the memory of NAND Flash+Mobile SDRAM two chips (layers of chips adopts cross type refracting films), second layer chip is obtained by being separated, its separation method, comprises the steps (techniqueflow chart is see Fig. 1):
(1) abrasive areas and area thereof is determined
The internal structure of the micro-detection of acoustic scan (C-SAM) memory, as shown in Figure 2, memory is the bilateral lead packages of cross type, and wherein, 1 is ground floor chip, and 2 is second layer chip; What determine abrasive areas is encapsulating material and 1 ground floor chip, and area is 8mm; Measure memory original depth simultaneously and be about 1mm, rule of thumb, the encapsulating material of the usual the superiors accounts for 1/3 of memory gross thickness, and this provides reference for grinding dynamics when grinding encapsulating material in follow-up grinding steps;
(2) fixing
The hot wax melting of memory sample is fixed on grinding table; Flowing because hot melt wax is heated, the out-of-flatness of device surface during cooling, may be caused, by measuring the thickness of abrasive areas difference chip on the surface, coordinating the height regulating grinding table, to adjust the evenness of abradant surface simultaneously.
(3) grind
According to step (1) described abrasive areas and area thereof, select abrasive drill 3mm, metallomicroscope monitoring grinding progress, adopt stepping grinding simultaneously, initial grinding dynamics is set to grinding 100 μm downwards, from grinding direction X, Y two direction grind, remove the upper strata chip of encapsulating material and second layer chip, be ground to the protective layer that second layer chip surface covers, when namely can be observed this layer of chip internal structure through this protective layer transparent material, stop grinding; In process of lapping, according to memory inside material color, the pattern change of metallomicroscope monitoring, observe the process of grinding, and adjust grinding dynamics, for same material, grinding dynamics reduces gradually.Not polished plastic packaging material is black, and the plastic packaging material color be polished is in light grey, and pattern is careful.Silicon chip, before not being polished, is the mirror-like of light.After polished, color is in light grey, and the pattern formed after grinding can be significantly coarse.When upper strata silicon chip be ground to very thin one deck time, the internal structure of lower layer chip can be seen through this thin layer.Continue grinding, the protective layer (being generally polyimides) on second layer chip can be seen, in orange-yellow transparence, through this protective layer, clearerly can see the internal structure of lower layer chip.
(4) chemical corrosion
The protective layer (being generally polyimides) adopting the second layer chip surface described in concentrated sulfuric acid removal step (3) to cover, can expose the second layer chip surface of complete display.By the careful detection means of metallomicroscope, observe the bonding wire on the internal structure of second layer chip, chip, result is see Fig. 3 and Fig. 4, and wherein, Fig. 3 is the local shape appearance figure of second layer chip, and Fig. 4 is second layer chip local pattern and lead-in wire shape appearance figure.
From Fig. 3 and Fig. 4: adopt separation method of the present invention, to be separated the bonding wire of the objective chip obtained complete not impaired, and the internal structure of lower layer chip and bonding wire complete not impaired.
If when objective chip is third layer, the chip such as the 4th layer of other 3D Stacked Die Packaging devices, then repeat above-mentioned grinding and steps of chemical attack to remove the chip of more lower.
The above embodiment only have expressed several execution mode of the present invention, and it describes comparatively concrete and detailed, but therefore can not be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection range of patent of the present invention should be as the criterion with claims.

Claims (6)

1. a chip separation method for 3D Stacked Die Packaging device, is characterized in that, comprises the steps:
(1) abrasive areas and area thereof is determined
The internal structure of acoustic scan micro-detection 3D Stacked Die Packaging ULSI sample, determines abrasive areas and area thereof;
(2) fixing
With hot melt wax, 3D Stacked Die Packaging ULSI sample is fixed on grinding table;
(3) grind
According to step (1) determined abrasive areas and area thereof, select abrasive drill, grinding dynamics and grinding direction, remove encapsulating material and the chip of abrasive areas, be ground to the protective layer of objective chip surface coverage; In described grinding: if milling area is 3-6mm, abrasive drill is 1mm, if milling area is 7-15mm, abrasive drill is 3mm, if milling area is for being greater than 15mm, abrasive drill is 5mm;
(4) chemical corrosion
Adopt chemical corrosion method, the protective layer described in removal step (3).
2. the chip separation method of 3D Stacked Die Packaging device according to claim 1, is characterized in that, is ground to stepping grinding described in step (3).
3. the chip separation method of 3D Stacked Die Packaging device according to claim 1, is characterized in that, the described grinding direction of step (3) is: XY direction or X-direction or Y-direction.
4. the chip separation method of 3D Stacked Die Packaging device according to claim 1, is characterized in that, step (4) described chemical corrosion method is: the concentrated sulfuric acid corrodes.
5. the chip separation method of 3D Stacked Die Packaging device according to claim 1, it is characterized in that, also calibration is comprised: described calibration is the thickness by measuring abrasive areas difference on the surface in fixing described in step (2) and the grinding described in step (3), regulate the height of grinding table, to adjust the evenness of abradant surface simultaneously.
6. the chip separation method of the 3D Stacked Die Packaging device according to any one of claim 1-5, is characterized in that, also comprise monitoring: the progress utilizing metallomicroscope monitoring step (3) described grinding and step (4) described chemical corrosion.
CN201310439837.1A 2013-09-24 2013-09-24 The chip separation method of 3D Stacked Die Packaging devices Active CN104465315B (en)

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Cited By (15)

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Publication number Priority date Publication date Assignee Title
CN105842611A (en) * 2016-03-31 2016-08-10 工业和信息化部电子第五研究所 Flip chip detection sample preparation method
CN107244648A (en) * 2017-05-08 2017-10-13 中国电子产品可靠性与环境试验研究所 The opening method of the MEMS inertia devices of chip laminate Plastic Package
CN109950156A (en) * 2017-12-20 2019-06-28 海太半导体（无锡）有限公司 Chip flip-chip unsealing method
CN110587385A (en) * 2019-09-30 2019-12-20 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） Method for thinning flip chip on circuit board, grinding drill bit and fixed base
CN111579555A (en) * 2020-04-02 2020-08-25 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） Structure detection method of SiP module
CN111710627A (en) * 2020-05-28 2020-09-25 北京芯可鉴科技有限公司 Chip packaging pretreatment method and chip analysis method
CN111883453A (en) * 2020-08-28 2020-11-03 长江存储科技有限责任公司 Wafer obtaining method and semiconductor device failure analysis method
CN112179915A (en) * 2019-07-04 2021-01-05 深圳长城开发科技股份有限公司 Layer removing method for positioning damage points in bare chip
CN113013021A (en) * 2021-03-01 2021-06-22 长江存储科技有限责任公司 Unsealing method of semiconductor packaging structure
CN113702807A (en) * 2021-08-25 2021-11-26 长鑫存储技术有限公司 Chip carrier and chip detection device
WO2022083185A1 (en) * 2020-10-23 2022-04-28 长鑫存储技术有限公司 Die taking-out method
CN114487788A (en) * 2022-04-02 2022-05-13 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） Failure positioning method of packaging device
CN114927408A (en) * 2022-05-19 2022-08-19 深圳市东方聚成科技有限公司 Nondestructive chip separation and packaging test recycling method for electronic device
CN115031855A (en) * 2022-06-13 2022-09-09 北京智创芯源科技有限公司 Manufacturing method of infrared detector and blind pixel processing method thereof
US11686765B2 (en) 2020-10-23 2023-06-27 Changxin Memory Technologies, Inc. Die extraction method

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CN105842611A (en) * 2016-03-31 2016-08-10 工业和信息化部电子第五研究所 Flip chip detection sample preparation method
CN107244648A (en) * 2017-05-08 2017-10-13 中国电子产品可靠性与环境试验研究所 The opening method of the MEMS inertia devices of chip laminate Plastic Package
CN109950156A (en) * 2017-12-20 2019-06-28 海太半导体（无锡）有限公司 Chip flip-chip unsealing method
CN112179915A (en) * 2019-07-04 2021-01-05 深圳长城开发科技股份有限公司 Layer removing method for positioning damage points in bare chip
CN110587385A (en) * 2019-09-30 2019-12-20 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） Method for thinning flip chip on circuit board, grinding drill bit and fixed base
CN111579555A (en) * 2020-04-02 2020-08-25 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） Structure detection method of SiP module
CN111710627A (en) * 2020-05-28 2020-09-25 北京芯可鉴科技有限公司 Chip packaging pretreatment method and chip analysis method
CN111710627B (en) * 2020-05-28 2024-03-01 北京芯可鉴科技有限公司 Chip packaging pretreatment method and chip analysis method
CN111883453A (en) * 2020-08-28 2020-11-03 长江存储科技有限责任公司 Wafer obtaining method and semiconductor device failure analysis method
CN111883453B (en) * 2020-08-28 2021-11-12 长江存储科技有限责任公司 Wafer obtaining method and semiconductor device failure analysis method
US11686765B2 (en) 2020-10-23 2023-06-27 Changxin Memory Technologies, Inc. Die extraction method
WO2022083185A1 (en) * 2020-10-23 2022-04-28 长鑫存储技术有限公司 Die taking-out method
CN113013021A (en) * 2021-03-01 2021-06-22 长江存储科技有限责任公司 Unsealing method of semiconductor packaging structure
CN113702807A (en) * 2021-08-25 2021-11-26 长鑫存储技术有限公司 Chip carrier and chip detection device
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