CN104425651B - The technique that a kind of low temperature prepares the heterojunction solar battery of front non-grid - Google Patents
The technique that a kind of low temperature prepares the heterojunction solar battery of front non-grid Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 68
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 55
- 239000012528 membrane Substances 0.000 claims abstract description 27
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims abstract description 24
- 239000011800 void material Substances 0.000 claims description 57
- 229910021419 crystalline silicon Inorganic materials 0.000 claims description 36
- 238000002161 passivation Methods 0.000 claims description 36
- 239000010409 thin film Substances 0.000 claims description 36
- 238000000151 deposition Methods 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 239000010408 film Substances 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 9
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 9
- 238000005240 physical vapour deposition Methods 0.000 claims description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 229910004205 SiNX Inorganic materials 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 235000008216 herbs Nutrition 0.000 claims description 4
- 210000002268 wool Anatomy 0.000 claims description 4
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 claims description 3
- 238000009713 electroplating Methods 0.000 claims description 3
- 238000003475 lamination Methods 0.000 claims description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 238000007650 screen-printing Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 8
- 238000002360 preparation method Methods 0.000 description 10
- 238000012864 cross contamination Methods 0.000 description 7
- 238000006243 chemical reaction Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
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- 230000007423 decrease Effects 0.000 description 4
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- 238000005530 etching Methods 0.000 description 4
- 230000009466 transformation Effects 0.000 description 4
- 208000035126 Facies Diseases 0.000 description 3
- 239000006117 anti-reflective coating Substances 0.000 description 3
- 239000002131 composite material Substances 0.000 description 3
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- 238000003754 machining Methods 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
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- 238000013467 fragmentation Methods 0.000 description 2
- 238000006062 fragmentation reaction Methods 0.000 description 2
- 238000005286 illumination Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000011068 loading method Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000005245 sintering Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229920000049 Carbon (fiber) Polymers 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
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- 239000010439 graphite Substances 0.000 description 1
- 229910002804 graphite Inorganic materials 0.000 description 1
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- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 1
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- -1 silicon nitrides Chemical class 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
- H01L31/202—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic Table
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
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Abstract
The invention provides the technique that a kind of low temperature prepares the heterojunction solar battery of front non-grid, by utilizing PECVD method to deposit alternatively distributed p-type and N-type amorphous silicon membrane in interdigital at a lower temperature, and by using mask plate to deposit p-type and N-type amorphous silicon membrane respectively from the combination of different shields, avoid damage introduced because of etch step in prior art, simultaneously, owing to need not clean mask plate and shield frequently, also simplify the integrating step of HIT battery and IBC battery, it is adaptable to commercial production.
Description
Technical field
The present invention relates to high performance solar batteries field, particularly relate to the technique that a kind of low temperature prepares the heterojunction solar battery of front non-grid.
Background technology
The solaode (IBC) of heterojunction solar battery (HJ) and back contacts is currently a popular two kind high-efficiency batteries, and its photoelectric transformation efficiency all can reach more than 24%, far above the conversion efficiency of current common crystal silion cell 18-19%.But for HJ battery, the grid line design on light entrance face makes the absorbing light area of battery reduce, thus reduces short circuit current, affects the transformation efficiency that solar cell is final.IBC battery substantially eliminates the shading loss of front gate line electrode present in above-mentioned HJ battery, make use of illumination more fully, improve battery efficiency, but the preparation of IBC battery in the prior art have employed the elevated temperature processes of complexity, its passivating material is made to select to receive restriction, particularly can not select the amorphous silicon material of good passivation effect, thus limit the raising of battery open circuit voltage.
The Dominant Facies of HJ battery-efficient passivation layer (amorphous silicon passivation layer) with the high incident illumination transmitance (front non-grid blocks) of IBC battery can be combined by the hetero-junctions high-efficiency battery of the most emerging front non-grid, estimate to realize the conversion efficiency higher than 26%, to be the most promising high-efficiency crystal silicon cell in future, great development potentiality.But the preparation technology of the most this high-efficiency battery is first to deposit one layer of doping type amorphous silicon membrane at substrate surface, such as p-type thin film, then utilize etching technics that this thin film is performed etching, again to etched portions deposited n-type thin film, form the alternatively distributed p-type of interdigital and N-type amorphous silicon membrane with this.This kind of technology will produce damage because of containing etch step to film surface, and complex manufacturing technology is relatively costly simultaneously, is not suitable for large-scale industrial production.
Summary of the invention
The invention provides the technique that a kind of low temperature prepares the heterojunction solar battery of front non-grid, by utilizing PECVD method to deposit alternatively distributed p-type and N-type amorphous silicon membrane in interdigital at a lower temperature, and by using mask plate to deposit p-type and N-type amorphous silicon membrane respectively from the combination of different shields, avoid damage introduced because of etch step in prior art, simultaneously, owing to need not clean mask plate and shield frequently, also simplify the integrating step of HJ battery and IBC battery, it is adaptable to commercial production.
In order to reach object above, the invention provides the technique that a kind of low temperature prepares the heterojunction solar battery of front non-grid, it is characterised in that: this technique comprises the following steps:
The first step, is carried out crystalline silicon and making herbs into wool, makes the front surface of described crystalline silicon have matte light trapping structure；
Second step, the front surface at described crystalline silicon is sequentially depositing amorphous silicon passivation layer, antireflection layer, and deposited amorphous silicon passivation layer on rear surface；
3rd step, mask plate and the first shield it is sequentially placed in the rear in the amorphous silicon passivation layer on surface, described mask plate includes overlay area, be arranged alternately in interdigital the first void region and the second void region, described first shield covers in overlay area and first void region of described mask plate, then uses the PECVD method surface deposited n-type in described second void region or P-type non-crystalline silicon thin film；
4th step, described first shield is replaced with the second shield that can hide described overlay area and the first void region, PECVD method is used to deposit the p-type contrary with amorphous silicon membrane conduction type described in the 3rd step or N-type amorphous silicon membrane on the surface of described first void region
5th step, replaces with the 3rd shield of the overlay area that can hide described mask plate by described second shield, and at described first void region and the second surface, void region depositing TCO films.
6th step, takes out described 3rd shield and mask plate, prepares metal electrode on described TCO thin film surface, forms cell piece.
Alternatively, described first void region being arranged alternately in interdigital is identical with described second void region shape.
Alternatively, described first void region that shape is identical can be rectangle, inverted trapezoidal with the cross section of the second void region or fall from power stepped.
Alternatively, described first void region being arranged alternately in interdigital and described second void region are for be alternately distributed at equal intervals.
Alternatively, the altitude range of described mask plate is 20-500 μm, and the thickness range of described amorphous silicon passivation layer is 3-12nm, and the thickness range of described p-type or N-type amorphous silicon membrane is 5-20nm, and the thickness range of described TCO thin film is 40-1000nm.
Alternatively, described crystalline silicon can be any one in n type single crystal silicon, p type single crystal silicon, N-type polycrystalline silicon, p-type polysilicon.
Alternatively, antireflective coating described in second step can be SiNx, the SiOx using PECVD with PVD method to prepare, or
SiOx/SiNx lamination, described amorphous silicon passivation layer can use PECVD method to prepare.
Alternatively, described TCO thin film can be the transparency conducting layer with ITO, ZnO:B, FTO, GZO or AZO as material using PVD, LPCVD or APCVD method to prepare.
Alternatively, the Process temperature ranges that described PECVD method relates to is 130-300 DEG C.
Alternatively, the 6th step prepares metal electrode and can use silk screen printing, PVD or electro-plating method.
Compared with prior art, the present invention has following technical effect that
The technique that disclosed low temperature prepares the heterojunction solar battery of front non-grid, IBC with HJ both high-efficiency battery Dominant Facies can be combined, and cell manufacturing process only needs to carry out under the lower temperature technique of 130-300 DEG C, without using etch step, avoid the damage and impurity introduced because of etching, decrease the damage situations of each process devices caused because temperature is too high simultaneously, the preparation difficulty of battery can be reduced, reduce cost.
In the present invention relatively low due to the technological temperature of PECVD method of preparation p-type and N-type non-crystalline silicon, therefore amorphous silicon layer can be introduced as passivation layer, silicon nitride relative to other, silicon oxide, the passivation material such as carborundum, amorphous silicon passivation layer has more preferable passivation effect, and it can more reduce the Interface composites that boundary defect causes, improve the open-circuit voltage of battery, thus preferably improve battery conversion efficiency.
During prior art prepares amorphous silicon passivation layer, P-type non-crystalline silicon thin film, N-type amorphous silicon membrane, TCO thin film, for avoiding cross-contamination, need to put in different pallets different types of amorphous silicon membrane so that silicon chip frequently shifts between pallet, easily causes the fragmentation of silicon chip.And in the present invention, it is only necessary to change shield and can solve the problem of cross-contamination, simplify production process, improve the yields of product.
In the present invention amorphous silicon passivation layer, P-type non-crystalline silicon thin film, N-type amorphous silicon membrane, TCO thin film preparation process in, owing to different film deposition processes employing special shield, and the overlay area of mask plate all carries on the back covering in each film deposition process, thus decrease cross-contamination, extend the cleaning frequency of mask plate and shield, the most also extend their service life.
Typically, in order to increase the effective area of electrode, it is desirable to the interval of P-type non-crystalline silicon thin film and N-type amorphous silicon membrane is the smaller the better, i.e. the overlay area of mask plate is the narrowest more good, but the width requirement of tens micron dimensions can bring the biggest challenge to machining, increases difficulty of processing and cost.In the alternative of the present invention, the overlay area that cross section can be used to be inverted trapezoidal or step, the bottom area that only need to reduce overlay area can realize increasing the purpose of electrode effective area, also reduce mechanical processing difficulty simultaneously.
Accompanying drawing explanation
Fig. 1 is the process chart of the heterojunction solar battery that low temperature prepares front non-grid in the present invention.
Fig. 2-Fig. 4 is corresponding to the structural representation of different phase in Fig. 1 solar cell technical process in the present invention.
Fig. 5 is the mask plate sectional view of one embodiment of the invention.
Specific embodiment
Understandable for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from, below in conjunction with the accompanying drawings the detailed description of the invention of the present invention is described in detail.
Elaborating a lot of detail in the following description so that fully understanding the present invention, but the present invention can also use other to be different from other method described here to be implemented, therefore the present invention is not limited by following public specific embodiment.
The invention provides the technique that a kind of low temperature prepares the heterojunction solar battery of front non-grid, by utilizing PECVD method to deposit alternatively distributed N-type and P-type non-crystalline silicon thin film in interdigital at a lower temperature, and by using combination deposited n-type and the P-type non-crystalline silicon thin film respectively of mask plate and different shields, avoid damage introduced because of etch step in prior art, simultaneously, owing to need not clean mask plate and shield frequently, decrease cross-contamination, also simplify the integrating step of HJ battery and IBC battery, it is adaptable to commercial production.
The invention provides the technique that a kind of low temperature prepares the heterojunction solar battery of front non-grid, this technological process comprises the following steps as shown in Figure 1:
Step S1, is carried out crystalline silicon and making herbs into wool, makes the front surface of described crystalline silicon have matte light trapping structure；
Step S2, the front surface at described crystalline silicon is sequentially depositing amorphous silicon passivation layer, antireflection layer, and deposited amorphous silicon passivation layer on rear surface；
Step S3, mask plate and the first shield it is sequentially placed in the rear in the amorphous silicon passivation layer on surface, described mask plate includes overlay area, be arranged alternately in interdigital the first void region and the second void region, described first shield covers in overlay area and first void region of described mask plate, then uses the PECVD method surface deposited n-type in described second void region or P-type non-crystalline silicon thin film；
Step S4, described first shield is replaced with the second shield that can hide described overlay area and the first void region, uses PECVD method to deposit the p-type contrary with amorphous silicon membrane conduction type described in the 3rd step or N-type amorphous silicon membrane on the surface of described first void region；
Step S5, replaces with the 3rd shield of the overlay area that can hide described mask plate by described second shield, and at described first void region and the second surface, void region depositing TCO films；
Step S6, takes out described 3rd shield and mask plate, prepares metal electrode on described TCO thin film surface, forms cell piece.
Fig. 2-Fig. 4 is corresponding to the structural representation of different phase during the processing technology of the solar cell shown in Fig. 1, is described in detail this technological process below in conjunction with Fig. 2-Fig. 4:
In step sl, crystalline silicon is carried out and making herbs into wool, the front surface making described crystalline silicon has matte light trapping structure, its described crystalline silicon can be any one in n type single crystal silicon, p type single crystal silicon, N-type polycrystalline silicon, p-type polysilicon, described matte light trapping structure can be to have the pattern such as the arc-shaped protrusions of array, pyramid projection, and it is mainly used in increasing absorptivity.Preferably, described crystalline silicon is n type single crystal silicon.
In step s 2, the front surface at described crystalline silicon is sequentially depositing amorphous silicon passivation layer 20, antireflection layer 10, and deposited amorphous silicon passivation layer 20 on rear surface, as shown in Figure 2.Described antireflective coating 10 can be to use SiNx, SiOx, or
SiOx/SiNx lamination, its frequently with preparation method can be PECVD Yu PVD method, be mainly used in increasing light and absorb, reduce sunlight in the reflection loss of battery surface.When preparing the passivation layer of solar cell, the relatively low PECVD method of temperature can be used to prepare amorphous silicon passivation layer, the thickness range of described amorphous silicon passivation layer is 3-12nm, it is relative to other traditional silicon nitrides, silicon oxide, the passivation material such as carborundum has more preferable passivation effect, it is possible to more reduce the Interface composites that boundary defect causes, improve the open-circuit voltage of battery, thus preferably improve battery conversion efficiency.
In step s3, as shown in Figure 2, mask plate 30 and the first shield 40 it is sequentially placed in the rear in the amorphous silicon passivation layer 20 on surface, the first void region 301 and the second void region 302 that described mask plate 30 includes overlay area 303, is arranged alternately in interdigital, described first shield 40 covers in overlay area 303 and first void region 301 of described mask plate, then uses the PECVD method surface deposited n-type in described second void region 302 or P-type non-crystalline silicon thin film.The shape of described described first void region 301 being arranged alternately in interdigital and described second void region 302 can be identical, and its cross sectional shape can be rectangle, inverted trapezoidal or fall from power stepped.Described first void region 301 being arranged alternately in interdigital and described second void region 302 are for be alternately distributed at equal intervals.The altitude range of described mask plate is 20-500 μm, is 5-20nm at the described surface deposited n-type of the second void region 302 or the thickness range of P-type non-crystalline silicon thin film, and the Process temperature ranges of the PECVD method that it uses is 130-300 DEG C.When crystalline silicon is n type single crystal silicon, in order to make carrier preferably to migrate, the N-type amorphous silicon membrane in the second void region 302 deposition would generally preferably prepare the higher N+ type amorphous silicon membrane of the doping content relative to substrate N.Described mask plate can be fixed on the pallet loading substrate or directly overlay on substrate, and described first shield can be fixed on the pallet loading substrate or be fixed on described mask plate.
In step s 4, as shown in Figure 3, described first shield 40 is replaced with and can hide described overlay area 303 and the second shield 50 of the second void region 302, use PECVD method to deposit the N-type contrary with amorphous silicon membrane conduction type described in step S3 or P-type non-crystalline silicon thin film on the surface of described first void region 301；Step S4 is similar with the PECVD method used in step S3, Process temperature ranges is also 130-300 DEG C, the thickness of the amorphous silicon membrane of deposition is 5-20nm, when crystalline silicon is n type single crystal silicon, if step S3 deposits N+ type amorphous silicon membrane in the second void region 302, then step S4 deposits P-type non-crystalline silicon thin film in the first void region 301;If step S3 deposits P-type non-crystalline silicon thin film in the second void region 302, then step S4 deposits N+ type amorphous silicon membrane in the first void region 301, finally make N+ type can form, with P-type non-crystalline silicon thin film, the structure that interdigital is arranged alternately.
In step s 5, as shown in Figure 4, described second shield 50 is replaced with the 3rd shield 60 of the overlay area 303 that can hide described mask plate, and at described first void region 301 and the surface depositing TCO films of the second void region 302；Described TCO thin film can be the transparency conducting layer with ITO, ZnO:B, FTO, GZO or AZO as material using PVD, LPCVD or APCVD method to prepare.Preferably, described TCO thin film is ito thin film, and its thickness range is 40-1000nm, uses PVD method to prepare.
In step s 6, take out described 3rd shield 60 and mask plate 30, and use on described TCO thin film surface silk screen printing, PVD or electro-plating method to prepare metal electrode (not shown), form cell piece.
Mask plate 30 involved in the present invention and the material requirements of first shield the 40, second shield the 50, the 3rd shield 60 can still provide for preferable machining below a size of 200 μm, and excellent flatness can be remained in that under the technological temperature of PECVD again, it is generally selected the carbon-based material that deformation is less, can preferably be any one material in carbon fiber, graphite.
The technique that disclosed low temperature prepares the heterojunction solar battery of front non-grid, IBC battery can be combined with HJ battery both high-efficiency battery Dominant Facies, and battery preparation technique only need to be carried out under the lower temperature of 130-300 DEG C, without using etch step, on the one hand the damage and impurity introduced because of etching is avoided, improve the deposition quality of thin film, another reverse side decreases the damage situations of each process devices caused because temperature is too high, such that it is able to reduce the preparation difficulty of battery, reduce cost.
In the present invention relatively low due to the technological temperature of PECVD method of preparation p-type and N-type non-crystalline silicon, therefore amorphous silicon layer can be introduced as passivation layer, silicon nitride relative to other, silicon oxide, the passivation material such as carborundum, amorphous silicon passivation layer has more preferable passivation effect, and it can more reduce the Interface composites that boundary defect causes, improve the open-circuit voltage of battery, thus preferably improve battery conversion efficiency.
During prior art prepares amorphous silicon passivation layer, P-type non-crystalline silicon thin film, N-type amorphous silicon membrane, TCO thin film, for avoiding cross-contamination, need to put in different pallets different types of amorphous silicon membrane so that silicon chip frequently shifts between pallet, easily causes the fragmentation of silicon chip.And in the present invention, it is only necessary to change shield and can solve the problem of cross-contamination, simplify production process, improve the yields of product.
In the present invention amorphous silicon passivation layer, P-type non-crystalline silicon thin film, N-type amorphous silicon membrane, TCO thin film preparation process in, owing to different film deposition processes employing special the first shield, the second shield and the 3rd shield, and the overlay area of mask plate the most all carries on the back covering in each film deposition process, therefore cell fabrication processes can reduce cross-contamination, thus extend the cleaning frequency of mask plate and shield, the most also extend their service life.
In order to increase the effective area of electrode, it is desirable to have greater area of p-type and N-type amorphous silicon membrane region, correspondingly, need the overlay area of narrower mask plate, usually require that overlay area reaches the width of 10-200 μm magnitude, but, the magnitude of tens μm brings the biggest difficulty to machining.Therefore, in the alternative of the present invention, described described first void region 301 being arranged alternately in interdigital and described second void region 302 cross sectional shape can be chosen as inverted trapezoidal, and the bottom surface area of the overlay area of the most described mask plate is amassed trapezoidal, as shown in Figure 5 less than top surface.Described first void region 301 and described second void region 302 cross sectional shape can be stepped for falling from power, described in the fall from power step number on rank can be 1-5.So, the purpose of electrode effective area can be realized increasing by reducing the bottom area of overlay area, also reduce mechanical processing difficulty simultaneously.
In the prior art making solar cell at present, separated by the nitride as antireflective coating between electrode and electric layer, therefore the electric current that electric layer produces is transferred on electrode, it is accomplished by using the method for sintering to be connected with electric layer by electrode, thus cause saturation current too high, reduce photoelectric transformation efficiency.And in the present invention owing to being transparency conducting layer between electrode and electric layer, the transmission of electric current therefore can be carried out without sintering, thus reduce saturation current, improve photoelectric transformation efficiency.
Although the present invention discloses as above with preferred embodiment; but the present invention is not limited to this, any those skilled in the art, without departing from the spirit and scope of the present invention; all can make various change and amendment, therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (10)
1. a low temperature prepares the technique of heterojunction solar battery of front non-grid, it is characterised in that: this technique bag
Include following steps:
The first step, is carried out crystalline silicon and making herbs into wool, makes the front surface of described crystalline silicon have matte and falls into light knot
Structure；
Second step, the front surface at described crystalline silicon is sequentially depositing amorphous silicon passivation layer, antireflection layer, and rear
Deposited amorphous silicon passivation layer on surface；
3rd step, is sequentially placed mask plate and the first shield in the rear in the amorphous silicon passivation layer on surface, described
Mask plate includes overlay area, be arranged alternately in interdigital the first void region and the second vacancy section
Territory, described first shield covers in overlay area and first void region of described mask plate, then uses
The PECVD method surface deposited n-type in described second void region or P-type non-crystalline silicon thin film；
4th step, replaces with described first shield and can hide described overlay area and the second of the second void region
Shield, uses PECVD method to deposit and amorphous described in the 3rd step on the surface of described first void region
P-type that silicon thin film conduction type is contrary or N-type amorphous silicon membrane；
5th step, replaces with the 3rd shield of the overlay area that can hide described mask plate by described second shield,
And at described first void region and the second surface, void region depositing TCO films；
6th step, takes out described 3rd shield and mask plate, prepares metal electrode on described TCO thin film surface,
Form cell piece.
A kind of low temperature the most as claimed in claim 1 prepares the technique of the heterojunction solar battery of front non-grid, its
It is characterised by: described first void region being arranged alternately in interdigital and described second void region shape
Shape is identical.
A kind of low temperature the most as claimed in claim 2 prepares the technique of the heterojunction solar battery of front non-grid, its
Be characterised by: the cross section of identical described first void region of shape and the second void region be rectangle,
Inverted trapezoidal or fall from power stepped.
A kind of low temperature the most as claimed in claim 1 prepares the technique of the heterojunction solar battery of front non-grid, its
It is characterised by: described first void region and described second void region that are arranged alternately in interdigital are
It is alternately distributed at equal intervals.
A kind of low temperature the most as claimed in claim 1 prepares the technique of the heterojunction solar battery of front non-grid, its
It is characterised by: the altitude range of described mask plate is 20-500 μm, the thickness of described amorphous silicon passivation layer
Scope is 3-12nm, and the thickness range of described p-type or N-type amorphous silicon membrane is 5-20nm, described TCO
The thickness range of thin film is 40-1000nm.
A kind of low temperature the most as claimed in claim 1 prepares the technique of the heterojunction solar battery of front non-grid, its
It is characterised by: described crystalline silicon is n type single crystal silicon, p type single crystal silicon, N-type polycrystalline silicon, p-type polysilicon
In any one.
A kind of low temperature the most as claimed in claim 1 prepares the technique of the heterojunction solar battery of front non-grid, its
It is characterised by: antireflection layer described in second step is SiNx, the SiOx using PECVD with PVD method to prepare,
Or SiOx/SiNx lamination, described amorphous silicon passivation layer uses PECVD method to prepare.
A kind of low temperature the most as claimed in claim 1 prepares the technique of the heterojunction solar battery of front non-grid, its
Be characterised by: described TCO thin film be use PVD, LPCVD or APCVD method prepare with ITO,
ZnO:B, FTO, GZO or AZO are the transparency conducting layer of material.
A kind of low temperature the most as claimed in claim 1 prepares the technique of the heterojunction solar battery of front non-grid, its
It is characterised by: the Process temperature ranges that described PECVD method relates to is 130-300 DEG C.
A kind of low temperature the most as claimed in claim 1 prepares the technique of the heterojunction solar battery of front non-grid,
It is characterized in that: the 6th step is prepared metal electrode and uses silk screen printing, PVD or electro-plating method.
Priority Applications (1)
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| CN108521832A (en) * | 2015-12-31 | 2018-09-11 | 中海阳能源集团股份有限公司 | A kind of back electrode heterojunction solar battery and preparation method thereof |
| CN107068798B (en) * | 2017-03-15 | 2019-05-17 | 深圳市科纳能薄膜科技有限公司 | Back contacts heterojunction solar battery and preparation method thereof |
| CN109755350A (en) * | 2019-01-14 | 2019-05-14 | 浙江晶科能源有限公司 | A kind of solar battery and preparation method thereof |
| CN110752274A (en) * | 2019-09-12 | 2020-02-04 | 常州比太科技有限公司 | Method for manufacturing HBC battery piece and battery by using shadow mask film coating |
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