CN104425446B - Electric fuse structure and its application method - Google Patents
Electric fuse structure and its application method Download PDFInfo
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- CN104425446B CN104425446B CN201310365603.7A CN201310365603A CN104425446B CN 104425446 B CN104425446 B CN 104425446B CN 201310365603 A CN201310365603 A CN 201310365603A CN 104425446 B CN104425446 B CN 104425446B
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Abstract
The present invention provides a kind of electric fuse structure and its application method.Wherein, electric fuse structure includes：Polysilicon layer below conductive layer and conductive layer；The polysilicon layer includes the first area doped with p-type ion and the second area doped with N-type ion, and the first area is disposed adjacent with second area, and the negative electrode projection of conductive layer, in the first area, anode projection is in the second area.In above-mentioned technical proposal, equivalent to one PN junction of the polysilicon layer.In use, the first area connection power cathode of the polysilicon layer, and second area connection positive source.Information write phase, the small voltage of short time can fuse conductive layer, increase resistance conductive layer；And the information after conductive layer fusing reads the breakdown reverse voltage that or so stage, 1V voltage is not up to PN junction, so as to read the stage in information, polysilicon layer keeps powerful resistance states, and then ensures the stability that information is read.
Description
Technical field
The present invention relates to semiconductor preparation field, more particularly, to a kind of electric fuse structure and its application method.
Background technology
In integrated circuit fields, electric fuse（Fuse）Refer to that resistance can significantly alter in integrated circuits（By
Low resistance state changes to high-impedance state）Or the connecting line that can be fused.
Electric fuse main application includes：（1）The defective circuit on same chip is substituted for starting redundant circuit, from
And effectively improve process rate.In this kind of purposes, the redundant circuit in electric fuse connection integrated circuit, once detection finds to integrate
Circuit has defect, just utilizes electric fuse reparation or the defective circuit of substitution；（2）For integrated circuit programmed functions.
Realize and first process metal interconnection, device array and programmed circuit (including electric fuse device) on chip during this kind of function
It is good, it is then that standard chips are fabricated to unique various chip by sequencing by the outside data input that carries out.Electric fuse is collecting
Chip research and development and cost of manufacture can be greatlyd save into circuit program function, thus are widely applied in programmable read only memory
On (Programmable Read Only Memory, PROM).In integrated circuit programmed process, melted by high voltage
Power-off fuse produces open circuit to complete the write-in of information 1, and the electric fuse not disconnected keeps connection status, as state 0.
As shown in figure 1, existing electric fuse structure forms fleet plough groove isolation structure in the semiconductor substrate（STI）100
On, electric fuse structure includes using metal（Aluminium, copper etc.）Or conductive layer 105 made of silicon.The conductive layer 105 includes anode 101
With negative electrode 103, and the electric fuse 102 for the fine strip shape being connected between anode 101 and negative electrode 103 with both.The sun
Pole 101 and the surface of negative electrode 103 have conductive plunger 104.In use, apply 3.3~5.0V high pressure to electric fuse structure, in sun
Pole 101 and negative electrode 103 are that electric fuse 102 produces heat energy, electric fuse are increased substantially to change by larger immediate current
102 resistance directly fuses electric fuse 102.Wherein, if electric fuse 102 is blown, the shape that electric fuse 102 is not blown
It is low resistance state under state, at electric fuse structure（If resistance is R）, after electric fuse 102 is blown in the state of, at electric fuse structure
For high-impedance state（If resistance is infinity）.
In order to improve the compatibility of electric fuse structure and IC manufacturing, electric fuse structure also includes being arranged at described lead
A layer thickness of the lower section of electric layer 105 isThe polysilicon layer 106 of doping above.So in actual use, often
Resistance based on the polysilicon layer 106 is not big enough, and after causing the electric fuse of conductive layer 105 to fuse, pass through polysilicon layer
Electric current causes the phenomenon that electric fuse structure anode and cathode turns on, so as to cause the resistance of electric fuse structure up to standard.
It is continuously increased especially with integrated circuit integrated level, after device size constantly reduction in integrated circuits, applies
The voltage for being added on electric fuse structure also decreases.Such as after the CD processing procedures of integrated circuit are less than 40nm, electric fuse knot is put on
The voltage of structure is typically only 1.5~2.5V, not so can damage other devices in integrated circuit.However, at lower voltages, hair
The resistance of existing polysilicon layer 106 reduces all the more, so that so that the conducting of electric fuse structure anode and cathode, several near failures of electric fuse structure.
During In-circuit programming, the resistance of electric fuse structure can not once meet to require, cause information to write and read unstable.
Therefore, after electric fuse fusing, how to ensure the resistance of electric fuse structure, prevent electric fuse structure negative and positive interpolar from leading
Logical the problem of being those skilled in the art's urgent need to resolve.
The content of the invention
The present invention solves the problems, such as to be to provide a kind of electric fuse structure and its application method, compared to existing electric fuse knot
Structure, the electric fuse structure is under less voltage, in shorter conduction time section, can also realize that electric fuse melts rapidly
It is disconnected, and ensure that the resistance of the electric fuse after fusing is sufficiently large to realize electric smelting wire cathode and be electrically isolated from the anodes.
To solve the above problems, described electric fuse structure, including：
Polysilicon layer in Semiconductor substrate；
Conductive layer on the polysilicon layer, the both ends of the conductive layer are respectively negative electrode and anode；
The polysilicon layer includes the first area doped with p-type ion and the second area doped with N-type ion, described
First area is disposed adjacent with second area, and the negative electrode projection of conductive layer, in the first area, anode projection is located at
In the second area.
Alternatively, the dopant dose of the N-type ion of the p-type ion concentration of the first area and second area be 1.0 ×
1013/cm2~1.0 × 1015/cm2。
Alternatively, the p-type ion concentration of the first area and the N-type ion concentration of second area are 1019~1021/
cm3。
Alternatively, the p-type ion is B, and the N-type ion is As or P.
Alternatively, the conductive layer also includes the interlude between negative electrode and anode, the width of the negative electrode and anode
Width of the degree more than the interlude.
Alternatively, the width of the interlude is 28~45nm, and the width of the negative electrode and anode is 0.1~0.5 μm.
Alternatively, the conductive layer is metal silicide layer.
Alternatively, the conductive layer thickness is
Alternatively, the thickness of the polysilicon layer is
Present invention also offers a kind of application method of above-mentioned electric fuse structure, including：
The first area connection power cathode of the electric fuse structure；
The second area connection positive source of the electric fuse structure；
Apply pulse voltage to the electric fuse structure, fuse the electric fuse, to write information；
Apply operating voltage to the electric fuse structure, to read write information.
Alternatively, the pulse voltage is 1.5~2.5V.
Alternatively, the time for being continuously applied the pulse voltage is less than 10 seconds.
Compared with prior art, technical scheme has advantages below：
In the polysilicon layer of electric fuse structure, the polysilicon layer includes the first area and doping doped with p-type ion
There is the second area of N-type ion, the first area is disposed adjacent with second area, and the negative electrode projection of conductive layer is positioned at described
In first area, anode projection is in the second area.In above-mentioned technical proposal, equivalent to one PN of the polysilicon layer
Knot.During follow-up use, the negative pole of power supply, second doped with N-type ion are connected doped with the first area of p-type ion
Region connects the positive pole of power supply.Therefore, in information write phase, after applying voltage to the electric fuse structure, the conductive layer
Heat is produced by electric current, EM effects occurs, causes conductive layer to exhaust rapidly and realizes fusing；And by conductive layer in polysilicon layer
Transmit under the heat effect come, acted on based on carrier intrinsic excitation, the current blocking failure of PN junction, so that it is guaranteed that information is write
Enter flow to be smoothed out；
And in the information reading stage, fused based on conductive layer, there is high resistance；And apply small voltage to electric fuse
（At most 1V）, there is breakback phenomenon insufficient for PN junction, the polysilicon layer with PN junction structure is with very high resistance（One
As in the case of, less than 10V, there is breakback phenomenon insufficient for PN junction）.So that above-mentioned electric fuse structure is protected all the time
High resistance state, it is ensured that information read stability.
Brief description of the drawings
Fig. 1 is the schematic diagram of existing electric fuse structure；
Fig. 2 a and 2b are the schematic diagrames of one embodiment of the present of invention electric fuse structure；
Fig. 3 a to Fig. 6 are the preparation process schematic diagrames of one embodiment of the present of invention electric fuse structure；
Fig. 7 is the voltage-current characteristic figure of PN junction.
Embodiment
As described in background, as the increase that integrated circuit integrates, the device size of integrated circuit also accordingly reduce,
In order to ensure the device in integrated circuit is injury-free, the operating voltage for putting on the device of integrated circuit also accordingly reduces.Such as
During In-circuit programming, the voltage for the electric fuse structure that fuses is reduced to 1.5V~2.5V by original 3.3V~5.0V.
But existing electric fuse is under above-mentioned voltage, even if after conductive layer fusing, high resistance that also can not be continual and steady
State, so as to reduce the reliability of follow-up reading.
Its reason is analyzed, can be sufficiently long to electric fuse structure application time in the integrated circuit of original larger CD processing procedures
3.3V~5.0V pulse voltage, with the electric fuse that fuses.But the diminution of the device size with integrated circuit, existing electric fuse
Structure is to exhaust conductive using electromigration (Electron Migration, abbreviation EM) effect to produce open circuit.
Electron mobility effect is shifting that is via temperature and electronic impact (Electron Wind) plus multiplying the metal ion caused by effect
It is dynamic.With continued reference to shown in Fig. 1, after enough pulse voltages are applied to electric fuse structure, conductive layer 105 is brought rapidly up（But no
The fusing point of the material of conductive layer use can be reached）, there are EM phenomenons, finally causes conductive layer to fuse in conductive layer 105.Period is conductive
High temperature caused by layer is transferred to polysilicon layer 106 so that and the Doped ions in polysilicon layer 106 are based on high temperature and EM phenomenons occur,
Another section is shifted to by one end of electric fuse structure, causes Doped ions in electric fuse 102 to exhaust, so as to improve the electricity of polysilicon layer
Resistance.
However, the thickness of polysilicon layer 106 is larger, and its electric conductivity is poor compared to conductive layer 105, so polysilicon layer
106 need the longer heat time to be properly completed EM so that in polysilicon layer 106 to complete the Doped ions in polysilicon layer 106
Doped ions " exhausting ".Reduced based on the pulse voltage numerical value applied to electric fuse structure, and the voltage value after reducing
Enough heats, which can not be produced, causes Doped ions " exhausting " in polysilicon layer 106, to improve the resistance of polycrystal layer.Thus,
Even if conductive layer fuses, polysilicon layer still keeps conducting between the negative electrode of electric fuse and anode.
In addition, the pursuit based on user for integrated circuit response speed, continues to apply pulse voltage to electric fuse structure
Time shortens again and again, thus more adds the difficulty that Doped ions in polysilicon layer 106 are properly completed EM.When polysilicon layer 106
In Doped ions can not thoroughly exhaust, the concentration gradient of a Doped ions is only formd in polysilicon layer 106, can not be made
Sufficiently large resistance is produced in polysilicon layer 106, is conducted with blocking between the anode 101 of electric fuse structure and negative electrode 103.Such as exist
In integrated circuit programmed process, after the conducting of electric fuse structure negative and positive interpolar directly reduces the write-in of integrated circuit information,
The reliability that information is read.
Therefore, the invention provides a kind of electric fuse structure and its application method.Electric fuse structure bag provided by the invention
Include the polysilicon layer below conductive layer and conductive layer.The polysilicon layer is including the first area doped with p-type ion and mixes
The miscellaneous second area for having N-type ion, the first area and second area are adjacent, and the negative electrode projection of conductive layer is positioned at described the
In one region, anode projection is in the second area.In use, the first area and second area form a PN
Knot.
Such as in integrated circuit programmed process, the first area connection power cathode of the polysilicon layer, and the secondth area
Domain connects positive source.PN junction of the polysilicon layer equivalent to an Opposite direction connection.It is short in information write phase under normal temperature
The small voltage of time can fuse conductive layer, increase resistance conductive layer；And the information after conductive layer fusing reads rank
Section, 1V or so operating voltage are not up to the breakdown reverse voltage of PN junction, and so as to read the stage in information, polysilicon layer is kept
Powerful resistance states, and then ensure the stability that information is read.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
With reference to shown in figure 2a and Fig. 2 b, wherein, Fig. 2 b be in Fig. 2 a along A-A to cross-sectional view.The present embodiment
A kind of electric fuse structure provided, including：Semiconductor substrate 100；It is stacked according to this from the bottom to top in the Semiconductor substrate 100
Insulating barrier 110, polysilicon layer and conductive layer.
The Semiconductor substrate 100 can be silicon substrate or germanium, germanium silicon, gallium arsenide substrate or silicon-on-insulator lining
Bottom, common Semiconductor substrate can be as the Semiconductor substrates in the present embodiment.
The insulating barrier is chosen as MeOx, zirconium, hafnium, aluminium, lanthanum, strontium, titanium, silicon and combinations thereof and oxide and nitride,
Or AL2O3、BST、TaO2And HfO2Etc. high-K dielectric layer, it does not limit protection scope of the present invention.
In the present embodiment, the polysilicon layer includes first area 121 and the two parts of second area 122 being disposed adjacent.
Wherein, the first area 121 is doped with p-type ion, and second area 122 is doped with N-type ion.
With reference to reference to shown in figure 3a and Fig. 3 b, wherein, Fig. 3 b be in Fig. 3 a along A-A to cross-sectional view.
The forming process of the polysilicon layer doped with ion includes：
After the insulating barrier 110 is formed in the Semiconductor substrate 100, one layer is formed above the insulating barrier 110
Polysilicon layer 120；
Afterwards, mask layer can be formed on the polysilicon layer 120（Do not shown in figure）, and patterning the mask layer
Afterwards, predetermined structure is formed as polysilicon layer described in mask etching using mask layer.
With reference to shown in figure 3a, in the present embodiment, structure and the follow-up conductive layer to be formed of the polysilicon in 120
Structure matches.The polysilicon layer 120 is along A-A to, middle tiny structure roomy in two.
Specifically, in the present embodiment, the polysilicon layer 120 include along A-A to, positioned at the end 123 and 124 at two,
And the pars intermedia 125 between end 123 and 124, the width of the end 123 and 124 are 28~45nm, pars intermedia
125 width is 0.1~0.5 μm.
In the present embodiment, the thickness of the polysilicon layer isIts formation process is chosen as CVD（Chemistry
Vapour deposition process）.
Referring next to shown in Fig. 4 a and 4b.Wherein, Fig. 4 b be in Fig. 4 a along A-A to cross-sectional view.
Along A-A directions, by one layer of photoresist layer 151 of the top of the polysilicon layer 120 covering of half.Its process includes can
One layer of photoresist layer is first covered above the polysilicon layer 120（Do not shown in figure）, removed afterwards using exposure imaging technology
Part photoresist layer, retain part photoresist layer 151 as shown in figures 4 a and 4b, its process is known to those skilled in the art
Technology, it will not be repeated here.
In the present embodiment, it is first area 121 to define the partial polysilicon layer covered by the photoresist layer 151, and naked
The partial polysilicon layer of dew is second area 122.It is mask with the photoresist layer 151, is injected into the second area 122
N-type ion, the N-type ion include As, P etc..Concrete technology may include：
After the photoresist layer 151 is formed, with 5KeV~20KeV ion implantation energy to the second area 122
Interior implantation dosage is 1.0x1013/cm2~1.0x1015/cm2The N-type ion such as As, P.
Then referring to shown in Fig. 5 a and 5b, wherein, Fig. 5 b be in Fig. 5 a along A-A to cross-sectional view.
After removing the photoresist layer 151, another layer of photoresist layer 152 of formation above the second area 122, and with
The photoresist layer 152 is mask, and the p-type ions such as B are injected into the exposed first area 121.The photoresist layer 152
Formation process it is close with the formation process of the photoresist layer 151, will not be repeated here.
Specifically, in the present embodiment, into the first area 121, the process of doped p-type ion may include：With 1KeV~
5KeV ion implantation energy implantation dosage into the first area 121 is 1.0x1013/cm2~1.0x1015/cm2The N such as B
Type ion.
After the ion injecting process of the first area 121 and second area 122 is completed, institute is activated using annealing process
State the p-type ion in first area 121, and the N-type ion in second area 122.P-type in the first area 121 from
N-type ion concentration in sub- concentration and second area 122 is 1019~1021/cm3。
After above-mentioned technique, the first area 121 and second area 122 form a PN junction.
With continued reference to shown in Fig. 2 a and 2b.Conductive layer is formed above the polysilicon layer.The conductive layer can be, such as
The metal levels such as Cu, Al or the metal silicide layer doped with metal ion.
In the present embodiment, the conductive layer is metal silicide layer.
With reference to shown in figure 6, in the present embodiment, the thickness of the conductive layer isThe conductive layer it is specific
Forming method may include：First use PVD（Physical vapour deposition (PVD)）, to the polysilicon layer on deposit the metal such as Ni, Co, Pt from
Son, form metal ion 130；Afterwards at 205 DEG C~500 DEG C, carry out annealing process so that the metal such as described Ni, Co, Pt from
Son is reacted with polysilicon layer 120, and metal silicide layer is formed on the top layer of polysilicon layer 120.
With continued reference to shown in Fig. 2 a and 2b, in the present embodiment, the structure of the conductive layer and the structure of the polysilicon layer
Match, along A-A directions, the conductive layer is roomy in two, middle tiny structure.The conductive layer wraps along its length
Include：Negative electrode 131 and anode 132 positioned at the conductive layer both ends, and the interlude between negative electrode 131 and anode 1332
133.The width of the negative electrode 131 and anode 132 is 28~45nm, and the width of interlude 133 is 0.1~0.5 μm.Wherein, institute
The negative electrode 121 for stating conductive layer is located at the top of first area 131 of the polysilicon layer, and the anode 122 of the conductive layer is located at institute
State the top of second area 132 of polysilicon layer.
During use, after voltage is applied to the anode and cathode, the conductive layer produces heat, and EM effects occur, and
Fuse the part of interlude 133 at first.
Then, multiple conductive plungers 140 are respectively formed on the negative electrode 121 and anode 122 of the conductive layer.
The formation process of the conductive plunger 140 may include：First dielectric layer is formed above the conductive layer（Do not show in figure
Show）, afterwards, in the dielectric layer, through hole is opened up with the corresponding position of the negative electrode 121 and anode 122（Do not show in figure
Show）, and the metals such as tungsten, copper, aluminium are filled into these through holes, to form the conductive plunger 140.
The invention provides a kind of application method of above-mentioned electric fuse structure, specifically include：
The negative electrode 121 of the conductive coating structure of the electric fuse structure is connected into power cathode, anode 122 is connecting power supply just
Pole.That is, the first area 131 equivalent to the polysilicon layer connects the negative pole of power supply, the second area 132 of the polysilicon layer
Connect positive source.PN junction of the polysilicon layer equivalent to an Opposite direction connection.
Apply pulse voltage to the electric fuse structure, fuse the electric fuse, to write information.Detailed process can wrap
Include：
Continue the pulse voltage to 1.5~2.5V of electric fuse structure application, be further chosen as 1.6~2.0V's
Pulse voltage.Now equivalent to information write phase.Based on the silicide layer（That is, conductive layer）Good electric conductivity, electric current
Silicide layer is run through, and produces heat；Based on the heat, there are rapidly EM effects in the silicide layer, causes silication
Nitride layer exhausts rapidly and fused.
Heat caused by silicide layer is transferred on the polysilicon layer simultaneously, the sheet based on the carrier in polysilicon layer
Excitation, the current blocking failure of PN junction are levied, thus smoothly completes information ablation process.
In the present embodiment, the time for being continuously applied the pulse voltage is less than 10 seconds, and the pulse voltage of 10 seconds is enough to cause
The metal silicide layer is fused rapidly.Above-mentioned technical proposal substantially reduces the time of information write-in.
Apply operating voltage after information write step is completed, then to the integrated circuit, carry out information reading step.This
When, the operating voltage applied to the integrated circuit is not more than 1V.With reference to reference to figure 7 and formula（1）It is shown.Wherein, formula（1）
In, Is is electric current, and C is constant, and K is Boltzmann constant, and T is temperature, and Eg is energy gap.Under normal temperature, K 8.6174x10- 5In eV/K, Eg 1.12eV, Fig. 7, V (BR) is breakdown reverse voltage, under normal temperature, V (BR) the ＞ 5V；V (TH) is work electricity
Press, under normal temperature, the V (TH) is 0.5~0.7V.
At normal temperatures, after applying operating voltage to the integrated circuit, the 1V operating voltage deficiency metal silicide
Layer and polysilicon layer are produced from thermal phenomenon, thus T（About 300K or so）It is very small, thus Is numerical value is very small.
With reference to reference to shown in figure 7, in the reverse characteristic stage of PN junction, PN junction is not up to by 1V or so operating voltage completely
Breakdown reverse voltage V (BR) numerical value.Voltage in polysilicon layer now is infinitely great, has been melted based on the metal silicide layer
It is disconnected, thus the electric fuse structure has sufficiently strong resistance, can effectively improve the reliability of information reading.
... ... formula（1）
In the present embodiment, under the conditions of above-mentioned pulse voltage, the metal silicide layer has good electric conductivity, is believing
Cease in ablation process, under 1.5~2.5V impulsive condition, metal silicide layer can be fused rapidly, so as to less than 10 second time
It is interior, it is general only to need 1~2 second, information write-in can be completed, substantially increases the speed of integrated circuit information write-in；Afterwards
In the information reading stage, the conductive layer has fused, and the PN junction structure based on the Opposite direction connection in the polysilicon layer, described
Electric fuse structure provides sufficiently large resistance, to improve the reliability of information reading.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, this is not being departed from
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (11)
1. a kind of electric fuse structure, including：
Polysilicon layer in Semiconductor substrate；
Conductive layer on the polysilicon layer, the both ends of the conductive layer are respectively negative electrode and anode；
Characterized in that, the polysilicon layer includes the first area doped with p-type ion and the secondth area doped with N-type ion
Domain, the first area are disposed adjacent with second area, and the negative electrode projection of conductive layer, in the first area, anode is thrown
Shadow is located in the second area；
The polysilicon layer is included positioned at the end at two, and the pars intermedia between two ends, the pars intermedia
Width is less than the width of the end；The first area and the second area account for the polysilicon layer Zone Full respectively
Half；The PN junction formed between the first area and the second area is located at the centre of the pars intermedia；
The thickness of the polysilicon layer is
2. electric fuse structure as claimed in claim 1, it is characterised in that the p-type ion concentration of the first area and second
The dopant dose of the N-type ion in region is 1.0 × 1013/cm2~1.0 × 1015/cm2。
3. electric fuse structure as claimed in claim 1, it is characterised in that the p-type ion concentration of the first area and second
The N-type ion concentration in region is 1019~1021/cm3。
4. electric fuse structure as claimed in claim 1, it is characterised in that the p-type ion is B, the N-type ion be As or
P。
5. electric fuse structure as claimed in claim 1, it is characterised in that the conductive layer also include positioned at negative electrode and anode it
Between interlude, the width of the negative electrode and anode is more than the width of the interlude.
6. electric fuse structure as claimed in claim 5, it is characterised in that the width of the interlude is 28~45nm, described
The width of negative electrode and anode is 0.1~0.5 μm.
7. electric fuse structure as claimed in claim 1, it is characterised in that the conductive layer is metal silicide layer.
8. electric fuse structure as claimed in claim 7, it is characterised in that the conductive layer thickness is
A kind of 9. application method of electric fuse structure as claimed in claim 1, it is characterised in that including：
The first area connection power cathode of the electric fuse structure；
The second area connection positive source of the electric fuse structure；
Apply pulse voltage to the electric fuse structure, fuse the electric fuse, to write information；
Apply operating voltage to the electric fuse structure, to read write information.
10. application method as claimed in claim 9, it is characterised in that the pulse voltage is 1.5~2.5V.
11. application method as claimed in claim 10, it is characterised in that the time for being continuously applied the pulse voltage is less than 10
Second.
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| CN109285974B (en) * | 2017-07-20 | 2021-08-03 | 宁德时代新能源科技股份有限公司 | Secondary cell top cap subassembly and secondary cell |
| CN109037190B (en) * | 2018-07-27 | 2020-07-10 | 上海华力集成电路制造有限公司 | Electric fuse structure and manufacturing method thereof |
| CN109244061A (en) * | 2018-09-03 | 2019-01-18 | 上海华虹宏力半导体制造有限公司 | Electrically programmable fuse structure and forming method thereof |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6420217B1 (en) * | 1999-08-17 | 2002-07-16 | National Semiconductor Corporation | Method of an apparatus for programming an integrated fuse element to high resistance in low voltage technology |
| US6436738B1 (en) * | 2001-08-22 | 2002-08-20 | Taiwan Semiconductor Manufacturing Company | Silicide agglomeration poly fuse device |
| TW512509B (en) * | 2000-06-16 | 2002-12-01 | Infineon Technologies Corp | Electrical fuses employing reverse biasing to enhance programming |
| US6580156B1 (en) * | 2002-04-04 | 2003-06-17 | Broadcom Corporation | Integrated fuse with regions of different doping within the fuse neck |
| US6661330B1 (en) * | 2002-07-23 | 2003-12-09 | Texas Instruments Incorporated | Electrical fuse for semiconductor integrated circuits |
| CN101312153A (en) * | 2007-05-23 | 2008-11-26 | 中芯国际集成电路制造(上海)有限公司 | Fuse-wires structure and forming method thereof |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6774457B2 (en) * | 2001-09-13 | 2004-08-10 | Texas Instruments Incorporated | Rectangular contact used as a low voltage fuse element |
| US7659168B2 (en) * | 2005-11-03 | 2010-02-09 | International Business Machines Corporation | eFuse and methods of manufacturing the same |
| TWM512509U (en) * | 2015-04-02 | 2015-11-21 | Spar Cobikes Co Ltd | Bicycle tire pressure transmission equipment |
-
2013
- 2013-08-20 CN CN201310365603.7A patent/CN104425446B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6420217B1 (en) * | 1999-08-17 | 2002-07-16 | National Semiconductor Corporation | Method of an apparatus for programming an integrated fuse element to high resistance in low voltage technology |
| TW512509B (en) * | 2000-06-16 | 2002-12-01 | Infineon Technologies Corp | Electrical fuses employing reverse biasing to enhance programming |
| US6436738B1 (en) * | 2001-08-22 | 2002-08-20 | Taiwan Semiconductor Manufacturing Company | Silicide agglomeration poly fuse device |
| US6580156B1 (en) * | 2002-04-04 | 2003-06-17 | Broadcom Corporation | Integrated fuse with regions of different doping within the fuse neck |
| US6661330B1 (en) * | 2002-07-23 | 2003-12-09 | Texas Instruments Incorporated | Electrical fuse for semiconductor integrated circuits |
| CN101312153A (en) * | 2007-05-23 | 2008-11-26 | 中芯国际集成电路制造(上海)有限公司 | Fuse-wires structure and forming method thereof |
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