CN104425446A - Fuse structure and using method thereof - Google Patents
Fuse structure and using method thereof Download PDFInfo
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- CN104425446A CN104425446A CN201310365603.7A CN201310365603A CN104425446A CN 104425446 A CN104425446 A CN 104425446A CN 201310365603 A CN201310365603 A CN 201310365603A CN 104425446 A CN104425446 A CN 104425446A
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Abstract
The invention provides a fuse structure and a using method thereof. The fuse structure comprises a conductive layer and a polysilicon layer below the conductive layer. The polysilicon layer comprises a firs region doped with P-type ions and a second region doped with N-type ions, and the first region and the second region are adjacent to each other. The projection of the cathode of the conductive layer is in the first region, and the projection of the anode is in the second region. According to the technical scheme, the polysilicon layer is equivalent to a PN junction. In use, the first region of the polysilicon layer is connected to the negative pole of a power supply, and the second region is connected to the positive pole of the power supply. In the stage of information writing, the conductive layer can be fused at low voltage in a short period of time, and the resistance of the conductive layer is increased. In the stage of information reading after the conductive layer is fused, voltage of about 1V does not reach the reverse breakdown voltage of the PN junction. Therefore, the polysilicon layer is always maintained at high resistance in the stage of information reading, and thus the stability of information reading is ensured.
Description
Technical field
The present invention relates to semiconductor preparation field, especially relate to a kind of electric fuse structure and using method thereof.
Background technology
In integrated circuit fields, electric fuse (Fuse) refers to that the connecting line significantly changing (being changed to high-impedance state by low resistance state) or can fuse can occur for resistance in integrated circuits.
Electric fuse main application comprises: (1) for starting redundant circuit to substitute defective circuit on same wafer, thus effectively improves process rate.In this kind of purposes, electric fuse connects the redundant circuit in integrated circuit, finds that integrated circuit has defect, just utilize electric fuse reparation or replace defective circuit once detect; (2) for integrated circuit programmed functions.First metal interconnection, device array and programmed circuit (comprising electric fuse device) are processed on chip when realizing this kind of function, then carry out data input and sequencing by outside and standard chips is made into unique various chip.Electric fuse can save chip research and development and cost of manufacture greatly in integrated circuit programmed functions, thus widely applies in programmable read only memory (Programmable Read Only Memory, PROM).In integrated circuit programmed process, produce by high voltage fusing electric fuse the write that open circuit completes information 1, and the electric fuse do not disconnected keeps connection status, is state 0.
As shown in Figure 1, existing electric fuse structure is formed on fleet plough groove isolation structure (STI) 100 in the semiconductor substrate, and electric fuse structure comprises the conductive layer 105 made with metal (aluminium, copper etc.) or silicon.Described conductive layer 105 comprises anode 101 and negative electrode 103, and the electric fuse 102 of the fine strip shape be connected with both between anode 101 and negative electrode 103.Described anode 101 and negative electrode 103 surface have conductive plunger 104.During use, applying the high pressure of 3.3 ~ 5.0V to electric fuse structure, at anode 101 and negative electrode 103 by larger immediate current, is that electric fuse 102 produces heat energy, to change the resistance that increases substantially electric fuse 102 or directly to be fused by electric fuse 102.Wherein, if electric fuse 102 is fused, electric fuse 102 is not by under the state that fuses, and electric fuse structure place is low resistance state (if resistance is R), and when electric fuse 102 is by under the state after fusing, electric fuse structure place is high-impedance state (if resistance is for infinitely great).
In order to improve the compatibility of electric fuse structure and IC manufacturing, electric fuse structure also comprises a layer thickness be arranged at below described conductive layer 105 and is
the polysilicon layer 106 of above doping.In right actual use procedure, resistance often based on described polysilicon layer 106 is large not, and after causing the electric fuse fusing of conductive layer 105, caused the phenomenon of electric fuse structure anode and cathode conducting by the electric current of polysilicon layer, thus cause the resistance of electric fuse structure cannot be up to standard.
Especially, along with integrated circuit integrated level constantly increases, after device size in integrated circuits constantly reduces, the voltage putting on electric fuse structure also decreases.As after the CD processing procedure of integrated circuit is less than 40nm, the voltage putting on electric fuse structure is generally only 1.5 ~ 2.5V, not so can damage other devices in integrated circuit.But, at lower voltages, find that the resistance of polysilicon layer 106 reduces all the more, so that make the conducting of electric fuse structure anode and cathode, a few near failure of electric fuse structure.As in In-circuit programming process, the resistance of electric fuse structure, once cannot meet the demands, causes information to write and reads unstable.
For this reason, after electric fuse fusing, how to ensure the resistance of electric fuse structure, stop conducting between electric fuse structure anode and cathode to be the problem that those skilled in the art need solution badly.
Summary of the invention
The problem that the present invention solves is to provide a kind of electric fuse structure and using method thereof, compared to existing electric fuse structure, even if described electric fuse structure is under less voltage, in shorter conduction time section, also can realize electric fuse quick-break, and guarantee that the resistance of the electric fuse after fusing is enough large to realize electric fuse negative electrode and anode electric isolution.
For solving the problem, described electric fuse structure, comprising:
Be positioned at the polysilicon layer in Semiconductor substrate;
Be positioned at the conductive layer on described polysilicon layer, the both ends of described conductive layer are respectively negative electrode and anode;
Described polysilicon layer comprises doped with the first area of P type ion and the second area doped with N-type ion, described first area is disposed adjacent with second area, and the projection of the negative electrode of conductive layer is positioned at described first area, anode projection is positioned at described second area.
Alternatively, the dopant dose of the P type ion concentration of described first area and the N-type ion of second area is 1.0 × 10
13/ cm
2~ 1.0 × 10
15/ cm
2.
Alternatively, the P type ion concentration of described first area and the N-type ion concentration of second area are 10
19~ 10
21/ cm
3.
Alternatively, described P type ion is B, and described N-type ion is As or P.
Alternatively, described conductive layer also comprises the interlude between negative electrode and anode, and the width of described negative electrode and anode is greater than the width of described interlude.
Alternatively, the width of described interlude is 28 ~ 45nm, and the width of described negative electrode and anode is 0.1 ~ 0.5 μm.
Alternatively, described conductive layer is metal silicide layer.
Alternatively, described conductive layer thickness is
Alternatively, the thickness of described polysilicon layer is
Present invention also offers a kind of using method of above-mentioned electric fuse structure, comprising:
The first area of described electric fuse structure connects power cathode;
The second area of described electric fuse structure connects positive source;
Apply pulse voltage to described electric fuse structure, fuse described electric fuse, with written information;
Operating voltage is applied, to read write information to described electric fuse structure.
Alternatively, described pulse voltage is 1.5 ~ 2.5V.
Alternatively, the time being continuously applied described pulse voltage is less than 10 seconds.
Compared with prior art, technical scheme of the present invention has the following advantages:
In the polysilicon layer of electric fuse structure, described polysilicon layer comprises doped with the first area of P type ion and the second area doped with N-type ion, described first area is disposed adjacent with second area, and the projection of the negative electrode of conductive layer is positioned at described first area, anode projection is positioned at described second area.In technique scheme, described polysilicon layer is equivalent to a PN junction.In follow-up use procedure, the first area doped with P type ion connects the negative pole of power supply, connects the positive pole of power supply doped with the second area of N-type ion.Therefore, in information write phase, after applying voltage to described electric fuse structure, by current generates heat, there is EM effect in described conductive layer, causes conductive layer to exhaust rapidly and realize fusing; And in polysilicon layer by conductive layer transmit the heat effect come under, based on the effect of charge carrier intrinsic excitation, the current blocking of PN junction lost efficacy, thus guaranteed that information write flow process is carried out smoothly;
And in information fetch phase, fused based on conductive layer, there is high resistance; And apply small voltage (at the most 1V) to electric fuse, be not enough to make PN junction occur breakback phenomenon, the polysilicon layer with PN junction structure has very high resistance (generally, less than 10V, being not enough to make PN junction occur breakback phenomenon).Thus make above-mentioned electric fuse structure protect high resistance state all the time, guarantee information read stability.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of existing electric fuse structure;
Fig. 2 a and 2b is the schematic diagram of one embodiment of the present of invention electric fuse structure;
Fig. 3 a to Fig. 6 is the preparation process schematic diagram of one embodiment of the present of invention electric fuse structure;
Fig. 7 is the voltage-current characteristic figure of PN junction.
Embodiment
As described in background, along with the increase that integrated circuit is integrated, the device size also corresponding reduction of integrated circuit, injury-free in order to ensure the device in integrated circuit, put on the operating voltage also corresponding reduction of the device of integrated circuit.As in In-circuit programming process, the voltage for the electric fuse structure that fuses is reduced to 1.5V ~ 2.5V by original 3.3V ~ 5.0V.
But existing electric fuse is under above-mentioned voltage, even if after conductive layer fusing, high resistance state that also cannot be continual and steady, thus the reliability reducing follow-up reading.
Analyze its reason, in the integrated circuit of original larger CD processing procedure, can to the pulse voltage of the sufficiently long 3.3V ~ 5.0V of electric fuse structure application time, with the electric fuse that fuses.But along with the reducing of device size of integrated circuit, existing electric fuse structure utilizes electromigration (Electron Migration is called for short EM) effect to exhaust conductive to produce open circuit.Electron mobility effect is the movement adding the metal ion taking advantage of effect to cause via temperature and electronic impact (Electron Wind).Continue with reference to shown in figure 1, after applying enough pulse voltages to electric fuse structure, conductive layer 105 rapid temperature increases (but can not arrive the fusing point of the material that conductive layer adopts), there is EM phenomenon in conductive layer 105, finally causes conductive layer to fuse.Period conductive layer produce high temperature be passed to polysilicon layer 106, make the Doped ions in polysilicon layer 106, based on high temperature, EM phenomenon occur, shift to another section by one end of electric fuse structure, cause Doped ions in electric fuse 102 to exhaust, thus improve the resistance of polysilicon layer.
But, polysilicon layer 106 thickness is larger, and poor compared to its conductivity of conductive layer 105, so the Doped ions that polysilicon layer 106 needs thoroughly complete in EM so that polysilicon layer 106 with the Doped ions completed in polysilicon layer 106 longer heating time " exhausts ".Reduce based on the pulse voltage numerical value that applies to electric fuse structure, and the voltage value after reducing cannot produce enough heats and causes the Doped ions in polysilicon layer 106 " to exhaust ", to improve the resistance of polycrystal layer.Thus, even if conductive layer fusing, polysilicon layer still keeps conducting between the negative electrode of electric fuse and anode.
In addition, based on the pursuit of user for integrated circuit response speed, continue to shorten again and again to the electric fuse structure applying pulse voltage time, thus more add Doped ions in polysilicon layer 106 and thoroughly complete the difficulty of EM.When the Doped ions in polysilicon layer 106 cannot thoroughly exhaust, in polysilicon layer 106, only define the concentration gradient of a Doped ions, cannot make to produce enough large resistance in polysilicon layer 106, conduct to block between the anode 101 of electric fuse structure and negative electrode 103.As in integrated circuit programmed process, after conducting between electric fuse structure anode and cathode directly reduces the write of integrated circuit information, the reliability that information reads.
For this reason, the invention provides a kind of electric fuse structure and using method thereof.Electric fuse structure provided by the invention comprises the polysilicon layer below conductive layer and conductive layer.Described polysilicon layer comprises doped with the first area of P type ion and the second area doped with N-type ion, and described first area is adjacent with second area, and the projection of the negative electrode of conductive layer is positioned at described first area, and anode projection is positioned at described second area.During use, described first area and second area form a PN junction.
As in integrated circuit programmed process, the first area of described polysilicon layer connects power cathode, and second area connects positive source.Described polysilicon layer is equivalent to the PN junction of an Opposite direction connection.Under normal temperature, in information write phase, the small voltage just fusible conductive layer of short time, increases resistance conductive layer; And the information fetch phase after described conductive layer fusing, the operating voltage of about 1V does not reach the reverse breakdown voltage of PN junction, thus at information fetch phase, polysilicon layer all keeps powerful resistance states, and then guarantees the stability that information reads.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
Shown in figure 2a and Fig. 2 b, wherein, Fig. 2 b be in Fig. 2 a along A-A to cross-sectional view.A kind of electric fuse structure that the present embodiment provides, comprising: Semiconductor substrate 100; Be stacked in insulating barrier 110, polysilicon layer and the conductive layer in described Semiconductor substrate 100 from the bottom to top according to this.
Described Semiconductor substrate 100 can be silicon substrate, and also can be germanium, germanium silicon, gallium arsenide substrate or silicon-on-insulator substrate, common Semiconductor substrate all can be used as the Semiconductor substrate in the present embodiment.
Described insulating barrier is chosen as MeOx, zirconium, hafnium, aluminium, lanthanum, strontium, titanium, silicon and combination thereof and oxide and nitride, or AL
2o
3, BST, TaO
2and HfO
2etc. high-K dielectric layer, it does not limit protection scope of the present invention.
In the present embodiment, described polysilicon layer comprises the first area 121 and second area 122 two parts that are disposed adjacent.Wherein, described first area 121 is doped with P type ion, and second area 122 is doped with N-type ion.
In conjunction with reference to shown in figure 3a and Fig. 3 b, wherein, described Fig. 3 b be in Fig. 3 a along A-A to cross-sectional view.The forming process of the described polysilicon layer doped with ion comprises:
After described Semiconductor substrate 100 forms described insulating barrier 110, above described insulating barrier 110, form one deck polysilicon layer 120;
Afterwards, mask layer (not shown) can be formed on described polysilicon layer 120, and after mask layer described in patterning, with mask layer for polysilicon layer described in mask etching forms predetermined structure.
Shown in figure 3a, in the present embodiment, described polysilicon is that the structure of 120 and the structure of the follow-up conductive layer that will be formed match.Described polysilicon layer 120 along A-A to, roomy in two, middle tiny structure.
Particularly, in the present embodiment, described polysilicon layer 120 comprise along A-A to, be positioned at the end 123 and 124 at two, and the pars intermedia 125 between end 123 and 124, the width of described end 123 and 124 is 28 ~ 45nm, and the width of pars intermedia 125 is 0.1 ~ 0.5 μm.
In the present embodiment, the thickness of described polysilicon layer is
its formation process is chosen as CVD(chemical vapour deposition technique).
Then with reference to shown in figure 4a and 4b.Wherein, described Fig. 4 b be in Fig. 4 a along A-A to cross-sectional view.
Along A-A direction, cover one deck photoresist layer 151 by above the described polysilicon layer 120 of half.Its process comprises and first can cover one deck photoresist layer (not shown) above described polysilicon layer 120, exposure imaging technology removal unit is adopted to divide photoresist layer afterwards, retain part photoresist layer 151 as shown in figures 4 a and 4b, its process knows technology for those skilled in the art, does not repeat them here.
In the present embodiment, defining the partial polysilicon layer covered by described photoresist layer 151 is first area 121, and exposed partial polysilicon layer is second area 122.With described photoresist layer 151 for mask, in described second area 122, inject N-type ion, described N-type ion comprises As, P etc.Concrete technology can comprise:
Formation described photoresist layer 151 after, with the ion implantation energy of 5KeV ~ 20KeV to implantation dosage in described second area 122 for 1.0x10
13/ cm
2~ 1.0x10
15/ cm
2as, the N-type ions such as P.
Then with reference to shown in figure 5a and 5b, wherein, described Fig. 5 b be in Fig. 5 a along A-A to cross-sectional view.
After removing described photoresist layer 151, above described second area 122, form another layer photoetching glue-line 152, and with described photoresist layer 152 for mask, in exposed described first area 121, inject the P type ions such as B.The formation process of described photoresist layer 152 is close with the formation process of described photoresist layer 151, does not repeat them here.
Particularly, in the present embodiment, in described first area 121, the process of doped p-type ion can comprise: with the ion implantation energy of 1KeV ~ 5KeV to implantation dosage in described first area 121 for 1.0x10
13/ cm
2~ 1.0x10
15/ cm
2the N-type ion such as B.
After the ion injecting process completing described first area 121 and second area 122, employing annealing process activates the P type ion in described first area 121, and the N-type ion in second area 122.P type ion concentration in described first area 121 and the N-type ion concentration in second area 122 are 10
19~ 10
21/ cm
3.
After above-mentioned technique, described first area 121 and second area 122 form a PN junction.
Continue with reference to shown in figure 2a and 2b.Conductive layer is formed above described polysilicon layer.Described conductive layer can be, as metal levels such as Cu, Al, also can be the metal silicide layer doped with metal ion.
In the present embodiment, described conductive layer is metal silicide layer.
Shown in figure 6, in the present embodiment, the thickness of described conductive layer is
the concrete formation method of described conductive layer can comprise: first adopt PVD(physical vapour deposition (PVD)), on described polysilicon layer, deposit the metal ions such as Ni, Co, Pt, form metal ion 130; Afterwards at 205 DEG C ~ 500 DEG C, carry out annealing process, the metal ions such as described Ni, Co, Pt and polysilicon layer 120 are reacted, form metal silicide layer on described polysilicon layer 120 top layer.
Continue with reference to shown in figure 2a and 2b, in the present embodiment, the structure of described conductive layer and the structure of described polysilicon layer match, and along A-A direction, described conductive layer is that two is roomy, middle tiny structure.Described conductive layer comprises along its length: the negative electrode 131 and the anode 132 that are positioned at described conductive layer two ends, and the interlude 133 between negative electrode 131 and anode 1332.The width of described negative electrode 131 and anode 132 is 28 ~ 45nm, and the width of interlude 133 is 0.1 ~ 0.5 μm.Wherein, the negative electrode 121 of described conductive layer is positioned at above the first area 131 of described polysilicon layer, and the anode 122 of described conductive layer is positioned at above the second area 132 of described polysilicon layer.
In use procedure, after applying voltage to described anode and cathode, described conductive layer produces heat, and EM effect occurs, and interlude 133 part that fuses at first.
Then, the multiple conductive plunger 140 of each formation on the negative electrode 121 and anode 122 of described conductive layer.
The formation process of described conductive plunger 140 can comprise: first above described conductive layer, form dielectric layer (not shown), afterwards, in described dielectric layer, through hole (not shown) is offered with the corresponding position of described negative electrode 121 and anode 122, and in these through holes, fill the metals such as such as tungsten, copper, aluminium, to form described conductive plunger 140.
The invention provides a kind of using method of above-mentioned electric fuse structure, comprise particularly:
The negative electrode 121 of the conductive coating structure of described electric fuse structure is connected power cathode, and anode 122 connects positive source.That is, the first area 131 being equivalent to described polysilicon layer connects the negative pole of power supply, and the second area 132 of described polysilicon layer connects positive source.Described polysilicon layer is equivalent to the PN junction of an Opposite direction connection.
Apply pulse voltage to described electric fuse structure, fuse described electric fuse, with written information.Detailed process can comprise:
Continue the pulse voltage applying 1.5 ~ 2.5V to described electric fuse structure, be chosen as the pulse voltage of 1.6 ~ 2.0V further.Now be equivalent to information write phase.Based on the conductivity that described silicide layer (that is, conductive layer) is good, electric current rapidly by silicide layer, and produces heat; Based on described heat, there is rapidly EM effect in described silicide layer, causes silicide layer exhaust rapidly and fuse.
The heat that silicide layer produces is passed on described polysilicon layer simultaneously, and based on the intrinsic excitation effect of the charge carrier in polysilicon layer, the current blocking of PN junction lost efficacy, and thus completed information ablation process smoothly.
In the present embodiment, the time being continuously applied described pulse voltage is less than 10 seconds, and the pulse voltage of 10 seconds is enough to cause described metal silicide layer by quick-break.Technique scheme substantially reduces the time of information write.
After completing information write step, then apply operating voltage to described integrated circuit, carry out information reading step.Now, the operating voltage applied to described integrated circuit is not more than 1V.In conjunction with reference to shown in figure 7 and formula (1).Wherein, in formula (1), Is is electric current, and C is constant, and K is Boltzmann constant, and T is temperature, and Eg is energy gap.Under normal temperature, K is 8.6174x10
-5eV/K, Eg are in 1.12eV, Fig. 7, and V (BR) is reverse breakdown voltage, under normal temperature, and described V (BR) > 5V; V (TH) is operating voltage, and under normal temperature, described V (TH) is 0.5 ~ 0.7V.
At normal temperatures, after applying operating voltage to described integrated circuit, the not enough described metal silicide layer of operating voltage of 1V and polysilicon layer produce from thermal phenomenon, and thus T(is approximately about 300K) very little, thus Is numerical value is very little.
In conjunction with reference to shown in figure 7, in the reverse characteristic stage of PN junction, do not reached reverse breakdown voltage V (BR) numerical value of PN junction completely by the operating voltage of about 1V.Voltage in polysilicon layer is now infinitely great, and fuse based on described metal silicide layer, thus described electric fuse structure has enough strong resistance, effectively can improve the reliability that information reads.
In the present embodiment, under above-mentioned pulse voltage condition, described metal silicide layer has good conductivity, in information ablation process, under the impulsive condition of 1.5 ~ 2.5V, metal silicide layer can by quick-break, thus less than in 10 second time, general needs 1 ~ 2 second, just can complete information write, substantially increase the speed of integrated circuit information write; In information fetch phase afterwards, described conductive layer fuses, and based on the PN junction structure of the Opposite direction connection in described polysilicon layer, described electric fuse structure provides enough large resistance, to improve the reliability that information reads.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (12)
1. an electric fuse structure, comprising:
Be positioned at the polysilicon layer in Semiconductor substrate;
Be positioned at the conductive layer on described polysilicon layer, the both ends of described conductive layer are respectively negative electrode and anode;
It is characterized in that, described polysilicon layer comprises doped with the first area of P type ion and the second area doped with N-type ion, described first area is disposed adjacent with second area, and the projection of the negative electrode of conductive layer is positioned at described first area, and anode projection is positioned at described second area.
2. electric fuse structure as claimed in claim 1, it is characterized in that, the dopant dose of the P type ion concentration of described first area and the N-type ion of second area is 1.0 × 10
13/ cm
2~ 1.0 × 10
15/ cm
2.
3. electric fuse structure as claimed in claim 1, it is characterized in that, the P type ion concentration of described first area and the N-type ion concentration of second area are 10
19~ 10
21/ cm
3.
4. electric fuse structure as claimed in claim 1, it is characterized in that, described P type ion is B, and described N-type ion is As or P.
5. electric fuse structure as claimed in claim 1, it is characterized in that, described conductive layer also comprises the interlude between negative electrode and anode, and the width of described negative electrode and anode is greater than the width of described interlude.
6. electric fuse structure as claimed in claim 5, it is characterized in that, the width of described interlude is 28 ~ 45nm, and the width of described negative electrode and anode is 0.1 ~ 0.5 μm.
7. electric fuse structure as claimed in claim 1, it is characterized in that, described conductive layer is metal silicide layer.
8. electric fuse structure as claimed in claim 7, it is characterized in that, described conductive layer thickness is
9. electric fuse structure as claimed in claim 1, it is characterized in that, the thickness of described polysilicon layer is
10. a using method for electric fuse structure as claimed in claim 1, is characterized in that, comprising:
The first area of described electric fuse structure connects power cathode;
The second area of described electric fuse structure connects positive source;
Apply pulse voltage to described electric fuse structure, fuse described electric fuse, with written information;
Operating voltage is applied, to read write information to described electric fuse structure.
11. usings method as claimed in claim 10, it is characterized in that, described pulse voltage is 1.5 ~ 2.5V.
12. usings method as claimed in claim 11, it is characterized in that, the time being continuously applied described pulse voltage is less than 10 seconds.
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| CN109244061A (en) * | 2018-09-03 | 2019-01-18 | 上海华虹宏力半导体制造有限公司 | Electrically programmable fuse structure and forming method thereof |
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