JP2008227267A - Forming method of resistance change memory, resistance change memory, and manufacturing method of resistance change memory - Google Patents

Forming method of resistance change memory, resistance change memory, and manufacturing method of resistance change memory Download PDF

Info

Publication number
JP2008227267A
JP2008227267A JP2007065139A JP2007065139A JP2008227267A JP 2008227267 A JP2008227267 A JP 2008227267A JP 2007065139 A JP2007065139 A JP 2007065139A JP 2007065139 A JP2007065139 A JP 2007065139A JP 2008227267 A JP2008227267 A JP 2008227267A
Authority
JP
Japan
Prior art keywords
resistance change
forming
change memory
voltage
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2007065139A
Other languages
Japanese (ja)
Other versions
JP5317420B2 (en
Inventor
Shinya Yagaki
真也 矢垣
Shinji Miyagaki
真治 宮垣
Masaki Aoki
正樹 青木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2007065139A priority Critical patent/JP5317420B2/en
Publication of JP2008227267A publication Critical patent/JP2008227267A/en
Application granted granted Critical
Publication of JP5317420B2 publication Critical patent/JP5317420B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a voltage necessary for forming operation, related to a forming method of a resistance change memory, a resistance change memory, and a manufacturing method of the resistance change memory. <P>SOLUTION: The forming method is conducted in such a manner that the forming operation of the resistance change memory equipped with a memory cell 1 composed of a resistance change element 2 in which a metal oxide film is interposed between conductive films and a cell selection transistor 3 is performed in a state of being heated at 80 to 200°C. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は抵抗変化メモリのフォーミング方法、抵抗変化メモリ、及び、抵抗変化メモリの製造方法に関するものであり、特に、金属酸化膜を導電層で挟み込んだ抵抗変化素子に電流パスを形成するためのフォーミング電圧を低減するための構成及びそれに伴うデバイス構成に特徴のある抵抗変化メモリのフォーミング方法、抵抗変化メモリ、及び、抵抗変化メモリの製造方法に関するものである。   The present invention relates to a resistance change memory forming method, a resistance change memory, and a resistance change memory manufacturing method, and more particularly to forming a current path in a resistance change element in which a metal oxide film is sandwiched between conductive layers. The present invention relates to a resistance change memory forming method, a resistance change memory, and a resistance change memory manufacturing method characterized by a configuration for reducing voltage and a device configuration associated therewith.

近年、不揮発性メモリとして金属酸化物薄膜の抵抗変化を用いたＲｅＲＡＭ（Ｒｅｓｉｓｔｉｖｅ Ｒａｎｄｏｍ Ａｃｃｅｓｓ Ｍｅｍｏｒｙ）が注目を集めており、その潜在能力はＭＲＡＭ（磁気抵抗効果型メモリ）を凌ぐものとして期待されている（例えば、特許文献１参照）。   In recent years, ReRAM (Resistive Random Access Memory) using a resistance change of a metal oxide thin film has attracted attention as a nonvolatile memory, and its potential is expected to surpass MRAM (magnetoresistance effect type memory). (For example, refer to Patent Document 1).

このＲｅＲＡＭの書込時間、読出時間、及び、消去時間は１０ナノ秒のオーダーであり、ＭＲＡＭと同程度であるが、ＭＲＡＭに比べて構成が簡単であり、且つ、動作原理も磁気スピンの向きを制御するＭＲＡＭに比べて簡単なため小型化が可能であるという利点がある。   The writing time, reading time, and erasing time of this ReRAM are on the order of 10 nanoseconds, which is similar to that of MRAM, but the configuration is simpler than that of MRAM, and the operating principle is the direction of magnetic spin. There is an advantage that it is possible to reduce the size because it is simpler than an MRAM that controls the above.

また、ＲｅＲＡＭは、“１”状態と“０”状態との間の抵抗変化が大きいので、多値化が可能であるという利点があるので、ここで、図６乃至図８を参照してＲｅＲＡＭを説明する。   In addition, since the ReRAM has a large resistance change between the “1” state and the “0” state, there is an advantage that multi-value can be obtained. Therefore, the ReRAM will be described with reference to FIGS. Will be explained.

図６参照
図６は、ＲｅＲＡＭの概念的要部断面図であり、ｐ型シリコン基板３１に設けたセル選択Ｔｒ３０とセル選択Ｔｒ３０のドレイン３３と多層配線構造３５を介して接続される抵抗変化素子４０からなる。 See FIG.
FIG. 6 is a conceptual cross-sectional view of the ReRAM, and includes a cell selection Tr 30 provided on the p-type silicon substrate 31, a resistance change element 40 connected to the drain 33 of the cell selection Tr 30 via a multilayer wiring structure 35. .

この場合の抵抗変化素子４０は、例えば、ＮｉＯ等の酸化膜４１の両面を下部Ｐｔ膜４２と上部Ｐｔ膜４３で挟んだサンドイッチ構造になっており、下部Ｐｔ電極４２は多層配線構造３５と接続し、一方、上部Ｐｔ電極４３はビット線３７を介して後述するコラムセレクタＴｒと接続している。
なお、ソース３４はソース電極３５を介してＧＮＤに接地される。 The resistance change element 40 in this case has a sandwich structure in which both surfaces of an oxide film 41 such as NiO are sandwiched between a lower Pt film 42 and an upper Pt film 43, and the lower Pt electrode 42 is connected to the multilayer wiring structure 35. On the other hand, the upper Pt electrode 43 is connected via a bit line 37 to a column selector Tr described later.
The source 34 is grounded to GND via the source electrode 35.

この抵抗変化素子は、成膜した状態のままの初期状態では絶縁体のような状態であり、成膜後にパルス電圧（フォーミング電圧）を印加して酸化膜４１中にｎｍオーダーの電流パス（“フィラメント”）を形成するフォーミング（Ｆｏｒｍｉｎｇ）動作が必要になる（例えば、非特許文献１参照）。   This resistance change element is in the state of an insulator in the initial state as it is formed, and a pulse voltage (forming voltage) is applied after the film formation to pass a current path (“ A forming operation for forming the filament “) is required (for example, see Non-Patent Document 1).

その後、電圧を印加することで高抵抗状態“０”と低抵抗状態“１”のデータを書き込む。
この場合、０→１の書き込みをセット（Ｓｅｔ）動作といい、１→０の書き込みをリセット（Ｒｅｓｅｔ）動作と言う。 Thereafter, the data of the high resistance state “0” and the low resistance state “1” is written by applying a voltage.
In this case, the writing of 0 → 1 is called a set operation, and the writing of 1 → 0 is called a reset operation.

図７参照
図７は、フォーミング動作、セット動作、リセット動作の説明図であり、成膜直後の状態では絶縁体のような状態であり、ここでフォーミング電圧をかけると、ある電圧で急激に抵抗が小さくなる（図７における実線の軌跡）。
この時に大きな電流が流れるので、素子が破損するのを防ぐために電流制限をかける。
なお、このフォーミング動作は大気中で室温で行っている。 See FIG.
FIG. 7 is an explanatory diagram of the forming operation, the setting operation, and the resetting operation. In the state immediately after the film formation, the state is like an insulator. When the forming voltage is applied here, the resistance rapidly decreases at a certain voltage. (The locus of the solid line in FIG. 7).
Since a large current flows at this time, a current limit is applied to prevent the element from being damaged.
This forming operation is performed at room temperature in the atmosphere.

次いで、フォーミング動作後の低抵抗状態の抵抗変化素子にパルス電圧を印加すると、ある電圧で急激に抵抗が大きくなるリセット動作となり（図７における破線の軌跡）、この状態のままであると、高抵抗状態“０”が書き込まれたことになる。   Next, when a pulse voltage is applied to the resistance change element in the low resistance state after the forming operation, the resistance suddenly increases in resistance at a certain voltage (a broken line locus in FIG. 7). The resistance state “0” is written.

次いで、リセット動作後の高抵抗状態の抵抗変化素子にパルス電圧を印加すると、ある電圧で急激に抵抗が小さくなるセット動作となり（図７における一点鎖線の軌跡）、この状態のままであると、低抵抗状態“１”が書き込まれたことになる。
この場合もフォーミング動作の時と同じように素子が破損するのを防ぐために電流制限をかける。
なお、各図においては、軌跡が重なるので矢印を有する細線により電流の変動方向を示している。 Next, when a pulse voltage is applied to the resistance change element in the high resistance state after the reset operation, the resistance suddenly decreases at a certain voltage (the locus of the alternate long and short dash line in FIG. 7). The low resistance state “1” is written.
In this case as well, a current limit is applied in order to prevent the element from being damaged as in the forming operation.
In each figure, since the loci overlap, the current fluctuation direction is indicated by a thin line having an arrow.

以降、リセット動作とセット動作の繰り返しをすることによってメモリ動作を行う。
なお、データの読み出しは、リセット動作を起こさない程度の小さな電圧を印加し、電流を測定することにより可能となる。 Thereafter, the memory operation is performed by repeating the reset operation and the set operation.
Note that data can be read by applying a small voltage that does not cause a reset operation and measuring the current.

図８参照
図８は、ＲｅＲＡＭの要部回路構成図であり、セル選択Ｔｒ３０と抵抗変化素子４０からなる各メモリセルは、各々コラムセレクタＴｒ５１に接続され、このコラムセレクタＴｒ５１は電源電圧印加用Ｔｒ５２を介して電源電圧５３に接続されている。
なお、フォーミング動作時及びセット動作時の電流制限はコラムセレクタＴｒ５１で行う。
特開２００４−２４１３９６号公報 Ｊａｐａｎｅｓｅ Ｊｏｕｒｎａｌ ｏｆ Ａｐｐｌｉｅｄ Ｐｈｙｓｉｃｓ Ｖｏｌ．４５，ｐ．９９１，２００６ See FIG.
FIG. 8 is a circuit diagram of the main part of the ReRAM. Each memory cell composed of the cell selection Tr30 and the resistance change element 40 is connected to a column selector Tr51. The column selector Tr51 is connected via a power supply voltage application Tr52. The power supply voltage 53 is connected.
Note that the current is limited during the forming operation and the setting operation by the column selector Tr51.
JP 2004-241396 A Japan Journal of Applied Physics Vol. 45, p. 991,2006

上述のフォーミング動作に必要な電圧は、酸化膜４１がＮｉＯ等の遷移金属酸化膜の場合には、３〜４Ｖとなり、セット動作に必要な電圧の１．５〜２Ｖと比較すると２倍ぐらいの大きさになるので、コラムセレクタＴｒ５１や電源電圧印加用Ｔｒ５２としては、セル選択Ｔｒ等の通常のトランジスタよりも高耐圧なトランジスタが必要になる。   When the oxide film 41 is a transition metal oxide film such as NiO, the voltage required for the above-described forming operation is 3 to 4 V, which is about twice as high as the voltage required for the set operation of 1.5 to 2 V. Therefore, as the column selector Tr51 and the power supply voltage application Tr52, a transistor having a higher breakdown voltage than that of a normal transistor such as a cell selection Tr is required.

しかし、ＲｅＲＡＭ装置中に高耐圧トランジスタを組み込むと、高耐圧トランジスタは通常のトランジスタよりも占有面積が大きいので集積度が低下するという問題がある。   However, when a high breakdown voltage transistor is incorporated in the ReRAM device, the high breakdown voltage transistor occupies a larger area than a normal transistor, and thus there is a problem that the degree of integration decreases.

また、ソース・ドレイン領域を通常のトランジスタよりも深く形成する必要があるので、通常のトランジスタとは別工程で形成する必要があり、工程数が増えることによってスループットが低下するという問題がある。   Further, since it is necessary to form the source / drain region deeper than the normal transistor, it is necessary to form the source / drain region in a separate process from the normal transistor, and there is a problem that the throughput is lowered by increasing the number of processes.

一方、コラムセレクタＴｒ５１や電源電圧印加用Ｔｒ５２を通常の耐圧のままでフォーミング動作時における素子破損を防止するためには、フォーミング動作に必要なフォーミング電圧を低下させる必要がある。   On the other hand, in order to prevent damage to the element during the forming operation while maintaining the column selector Tr51 and the power supply voltage application Tr52 at the normal breakdown voltage, it is necessary to reduce the forming voltage required for the forming operation.

したがって、本発明は、フォーミング動作に必要な電圧を低減することを目的とする。   Therefore, an object of the present invention is to reduce the voltage required for the forming operation.

図１は本発明の原理的構成図であり、ここで図１を参照して、本発明における課題を解決するための手段を説明する。
なお、図における符号６は、電源電圧である。
図１参照
上記の課題を解決するために、本発明は、金属酸化膜を導電膜で挟み込んだ抵抗変化素子２とセル選択トランジスタ３からなるメモリセル１を備えた抵抗変化メモリのフォーミング方法であって、抵抗変化メモリのフォーミング動作を８０〜２００℃に加熱した状態で行うことを特徴とする。 FIG. 1 is a block diagram showing the principle of the present invention, and means for solving the problems in the present invention will be described with reference to FIG.
In addition, the code | symbol 6 in a figure is a power supply voltage.
See FIG. 1 In order to solve the above problem, the present invention is a resistance change memory forming method including a memory cell 1 including a resistance change element 2 and a cell selection transistor 3 in which a metal oxide film is sandwiched between conductive films. Then, the forming operation of the resistance change memory is performed in a state heated to 80 to 200 ° C.

このように、８０〜２００℃に加熱した状態でフォーミング動作を行うことによって、従来、室温で行っていたフォーミング動作に必要だったフォーミング電圧を低下することができ、それによって、フォーミング過程における素子破壊発生の危険度を大幅に低減することができる。   Thus, by performing the forming operation in a state heated to 80 to 200 ° C., the forming voltage required for the forming operation that has been conventionally performed at room temperature can be reduced. The risk of occurrence can be greatly reduced.

また、フォーミング電圧の低下によって、コラムセレクタトランジスタ４や電源電圧印加用トランジスタ５を特別高耐圧にする必要がなくなる。
例えば、従来、３〜４Ｖ必要であったフォーミングで電圧を３Ｖ前後に低下することが可能になる。 In addition, it is not necessary to make the column selector transistor 4 and the power supply voltage application transistor 5 have an extra high breakdown voltage due to a decrease in the forming voltage.
For example, it is possible to reduce the voltage to around 3V by forming which conventionally required 3-4V.

この場合、フォーミング動作はウェーハ状態で行うことが望ましく、それによって、チップ毎のセッテイングが不要になり、フォーミング動作を一括して行えるのでフォーミング動作に要する時間を短縮することができる。   In this case, it is desirable that the forming operation be performed in a wafer state, so that setting for each chip becomes unnecessary, and the forming operation can be performed in a lump, so that the time required for the forming operation can be shortened.

また、本発明は、金属酸化膜を導電膜で挟み込んだ抵抗変化素子２とセル選択トランジスタ３からなるメモリセル１を備えた抵抗変化メモリであって、抵抗変化素子２に電源電圧を印加する電源電圧印加用トランジスタ５及びコラムセレクタトランジスタ４の耐圧とセル選択トランジスタ３の耐圧が同じであることを特徴とする。   The present invention also relates to a resistance change memory including a memory cell 1 including a resistance change element 2 and a cell selection transistor 3 in which a metal oxide film is sandwiched between conductive films, and a power supply for applying a power supply voltage to the resistance change element 2. The breakdown voltage of the voltage application transistor 5 and the column selector transistor 4 is the same as that of the cell selection transistor 3.

上述のように、フォーミング電圧を低下させた場合には、電源電圧印加用トランジスタ５を特別高耐圧にする必要がなくなるので、コラムセレクタトランジスタ４や電源電圧印加用トランジスタ５とセル選択トランジスタ３を同じトランジスタで構成すれば良く、それによって、別個の製造工程が不要になるとともに、占有面積を小さくすることができるので集積度が向上する。   As described above, when the forming voltage is lowered, it is not necessary to make the power supply voltage applying transistor 5 have an extra high breakdown voltage, so that the column selector transistor 4 and the power supply voltage applying transistor 5 are the same as the cell selection transistor 3. What is necessary is just to comprise with a transistor, and, thereby, a separate manufacturing process becomes unnecessary and an occupation area can be made small and an integration degree improves.

この場合の金属酸化膜としては、ＮｉＯやＴｉＯ等の遷移金属酸化膜が典型的なものであり、８０〜２００℃に加熱した状態でフォーミング動作を行うことでフォーミング電圧を３Ｖ程度に低下することが可能になる。   As the metal oxide film in this case, a transition metal oxide film such as NiO or TiO is typical, and the forming voltage is lowered to about 3 V by performing the forming operation in a state heated to 80 to 200 ° C. Is possible.

本発明により、フォーミング過程における素子破壊発生の危険度を大幅に低減することができるとともに、コラムセレクタトランジスタや電源電圧印加用トランジスタを通常のトランジスタとすることができ、高耐圧トランジスタが不要となり、高集積度で小面積のＲｅＲＡＭのが実現が可能になる。   According to the present invention, the risk of element destruction in the forming process can be greatly reduced, and the column selector transistor and the power supply voltage application transistor can be made into ordinary transistors, so that a high withstand voltage transistor is not required. It is possible to realize a ReRAM with a small degree of integration.

本発明は、ＲｅＲＡＭをウェーハ状態で、８０〜２００℃に加熱した状態、例えば、１５０℃に加熱したホットプレート上に載置した状態でフォーミング動作を行うものである。   The present invention performs the forming operation in a state where the ReRAM is heated to 80 to 200 ° C. in a wafer state, for example, placed on a hot plate heated to 150 ° C.

図２参照
図２は、フォーミング電圧の温度依存性の測定系の説明図であり、ＲｅＲＡＭを形成したウェーハ１１を温度可変プローブステーション１２上に載置して、ウェーハを所定温度に加熱した状態で、ＲｅＲＡＭに１０ｎ秒のパルス幅のパルス電圧を１パルス印加して、プローブ端子１３，１４を抵抗変化素子の電流出力端子に当接して、抵抗変化素子に流れる電流をテスタ１５で監視し、抵抗変化素子に流れる電流が急激に増加した時点、即ち、抵抗が急激に低下した時点で、金属酸化膜中に電流パスが形成されたフォーミングが完了したものと判定する。 See Figure 2
FIG. 2 is an explanatory diagram of a measurement system of the temperature dependence of the forming voltage. The wafer 11 on which the ReRAM is formed is placed on the temperature variable probe station 12, and the wafer is heated to a predetermined temperature and the ReRAM is mounted on the ReRAM. A pulse voltage having a pulse width of 10 ns is applied, the probe terminals 13 and 14 are brought into contact with the current output terminal of the resistance change element, the current flowing through the resistance change element is monitored by the tester 15, and the resistance change element is applied. When the flowing current suddenly increases, that is, when the resistance sharply decreases, it is determined that the forming in which the current path is formed in the metal oxide film is completed.

図３参照
図３は、フォーミング電圧の雰囲気温度依存性の説明図であり、バラツキはあるものの、フォーミング雰囲気温度を８０℃以上にした場合には有意にフォーミング電圧の低下が認められ、特に、２００℃の範囲までは、温度の上昇とともにフォーミング電圧が低下することが確認された。
なお、２００℃以上においても、フォーミング電圧自体はさらなる低下が予測されるが、温度を上げ過ぎると、層間絶縁膜等に悪影響を与える可能性が生じる。 See Figure 3
FIG. 3 is an explanatory diagram of the atmospheric temperature dependence of the forming voltage. Although there is variation, when the forming atmosphere temperature is 80 ° C. or higher, a significant decrease in the forming voltage is recognized, particularly in the range of 200 ° C. Until now, it has been confirmed that the forming voltage decreases as the temperature increases.
Even at 200 ° C. or higher, the forming voltage itself is expected to further decrease. However, if the temperature is raised excessively, there is a possibility that the interlayer insulating film or the like is adversely affected.

一方、温度を低下させた場合には、あまり変化が見られなかった。
なお、−５０℃近傍において、フォーミング電圧のバラツキは低下する傾向が見られたが、フォーミング電圧の平均値にはさほどの低下は見られない。 On the other hand, when the temperature was lowered, there was little change.
In addition, although the variation in forming voltage tended to decrease in the vicinity of −50 ° C., the average value of the forming voltage did not decrease so much.

このように、バラツキはあるものの、フォーミング動作を８０〜２００℃の加熱状態で行うことによって、フォーミング電圧を有意に低減することができる。
なお、フォーミング電圧のバラツキについては、ＲｅＲＡＭの製造工程が確立された暁にはバラツキは当然非常に小さくなるので、その時点で８０〜２００℃の範囲において、ウェーハ内に形成した各ＲｅＲＡＭのバラツキを予めサンプル測定して、その内の最も高いフォーミング電圧を合わせてフォーミング動作を行えば良い。 Thus, although there is variation, the forming voltage can be significantly reduced by performing the forming operation in a heating state of 80 to 200 ° C.
Regarding the variation of the forming voltage, the variation is naturally very small when the manufacturing process of ReRAM is established. Therefore, the variation of each ReRAM formed in the wafer is within the range of 80 to 200 ° C. at that time. Samples may be measured in advance, and the forming operation may be performed with the highest forming voltage among them.

ここで、図４乃至図５を参照して、本発明の実施例１のＲｅＲＡＭのフォーミング方法を説明する。
図４参照
図４は、本発明の実施例１のＲｅＲＡＭのフォーミング方法の対象となるＲｅＲＡＭの要部回路構成図であり、と抵抗変化素子２２とセル選択Ｔｒ２３からなる各メモリセル２１は、各々コラムセレクタＴｒ２４に接続され、このコラムセレクタＴｒ２４は電源電圧印加用Ｔｒ２５を介して電源電圧２６に接続されている。
この場合、セル選択Ｔｒ２３、コラムセレクタＴｒ２４、及び、電源電圧印加用Ｔｒ２５は同一工程で形成するものであり、したがって、耐圧も殆ど同じになる。 Here, the ReRAM forming method according to the first embodiment of the present invention will be described with reference to FIGS.
See Figure 4
FIG. 4 is a circuit diagram of a principal part of the ReRAM that is a target of the ReRAM forming method according to the first embodiment of the present invention, and each memory cell 21 including the resistance change element 22 and the cell selection Tr 23 includes a column selector Tr 24. The column selector Tr24 is connected to the power supply voltage 26 via the power supply voltage application Tr25.
In this case, the cell selection Tr23, the column selector Tr24, and the power supply voltage application Tr25 are formed in the same process, and therefore the breakdown voltage is almost the same.

図５参照
図５は、本発明の実施例１のＲｅＲＡＭのフォーミング方法の説明図であり、ＲｅＲＡＭを形成したウェーハ１１をホットプレート１６上に載置して、予めサンプル測定により決定したフォーミング電圧でのフォーミング動作が可能な温度、例えば、１５０℃まで加熱した状態で、例えば、３Ｖでパルス幅が１０ｎ秒のパルス電圧を１パルスだけ印加してフォーミング動作を行う。 See Figure 5
FIG. 5 is an explanatory diagram of the ReRAM forming method according to the first embodiment of the present invention. The wafer 11 on which the ReRAM is formed is placed on the hot plate 16 and the forming operation at the forming voltage determined in advance by sample measurement is performed. In a state where the temperature is heated to 150.degree. C., for example, 150.degree.

この時、プローブ端子１３，１４を抵抗変化素子の電流出力端子に当接して、抵抗変化素子に流れる電流をテスタ１５でモニターして、フォーミング動作が正常に行われているか否かを監視する。   At this time, the probe terminals 13 and 14 are brought into contact with the current output terminal of the variable resistance element, and the current flowing through the variable resistance element is monitored by the tester 15 to monitor whether or not the forming operation is normally performed.

以上、本発明の実施例を説明したが、本発明は実施例に示した構成、条件、数値に限られるものではなく、各種の変更が可能であり、例えば、上記の実施例においては、抵抗変化素子を構成する金属酸化膜としてＮｉＯを用いているが、ＮｉＯ以外の金属酸化膜に対しても同様のフォーミング動作は有効である。   Although the embodiments of the present invention have been described above, the present invention is not limited to the configurations, conditions, and numerical values shown in the embodiments, and various modifications are possible. For example, in the above embodiments, the resistance Although NiO is used as the metal oxide film constituting the change element, the same forming operation is effective for metal oxide films other than NiO.

例えば、ＮｉＯと同様に、ＴｉＯ2 、ＨｆＯ2 、或いは、ＺｒＯ2 等の二元系遷移金属酸化膜を用いても良いし、或いはＰｒ0.7 Ｃａ0.3 ＭｎＯ3 やＰｂ（Ｚｒ，Ｔｉ）Ｏ3 ／Ｚｎ0.4 Ｃｄ0.6 Ｓ等のペロブスカイト系酸化膜を用いた場合にも適用されるものである。 For example, similarly to NiO, a binary transition metal oxide film such as TiO 2 , HfO 2 , or ZrO 2 may be used, or Pr 0.7 Ca 0.3 MnO 3 or Pb (Zr, Ti) O 3 / The present invention is also applied when a perovskite oxide film such as Zn 0.4 Cd 0.6 S is used.

また、上記の実施例においては、セル選択Ｔｒ２３、コラムセレクタＴｒ２４、及び、電源電圧印加用Ｔｒ２５は同一工程で形成しているが、必ずしも、同一工程である必要はなく、また、耐圧も同じである必要はなく、例えば、従来の高耐圧のコラムセレクタＴｒ及び／又は電源電圧印加用トランジスタを備えたＲｅＲＡＭのフォーミング動作にも適用されるものである。   In the above embodiment, the cell selection Tr23, the column selector Tr24, and the power supply voltage application Tr25 are formed in the same process, but they are not necessarily in the same process, and have the same breakdown voltage. For example, the present invention can be applied to a forming operation of a ReRAM including a conventional high-voltage column selector Tr and / or a power supply voltage application transistor.

この場合、集積度の改善効果は得られないものの、フォーミング電圧を従来より低下することができるので、フォーミング動作に伴う素子破壊による不良品の発生を大幅に低減することができ、それによって、製造歩留りが向上するので、低コスト化が可能になる。   In this case, although the improvement effect of the degree of integration cannot be obtained, the forming voltage can be lowered as compared with the conventional one, so that the generation of defective products due to the element destruction accompanying the forming operation can be greatly reduced, thereby producing Since the yield is improved, the cost can be reduced.

本発明の活用例としては、不揮発性メモリが典型的なものであり、特に、微細化に適し且つ製造コストが低いためにフラッシュメモリの後継として非常に有望であるが、単体のメモリ素子に限られるものではなく、ロジックと同一チップにメモリを混載した混載メモリ等のメモリにも適用されるのでもである。   As a practical example of the present invention, a non-volatile memory is typical. Particularly, it is very promising as a successor to a flash memory because it is suitable for miniaturization and low in manufacturing cost, but it is limited to a single memory element. However, the present invention is also applicable to a memory such as an embedded memory in which the memory is embedded in the same chip as the logic.

本発明の原理的構成の説明図である。It is explanatory drawing of the fundamental structure of this invention. フォーミング電圧の温度依存性の測定系の説明図である。It is explanatory drawing of the measurement system of the temperature dependence of forming voltage. フォーミング電圧の雰囲気温度依存性の説明図である。It is explanatory drawing of the atmospheric temperature dependence of forming voltage. 本発明の実施例１のＲｅＲＡＭのフォーミング方法の対象となるＲｅＲＡＭの要部回路構成図である。FIG. 2 is a circuit diagram of a main part of the ReRAM that is a target of the ReRAM forming method according to the first embodiment of the present invention. 本発明の実施例１のＲｅＲＡＭのフォーミング方法の説明図である。It is explanatory drawing of the forming method of ReRAM of Example 1 of this invention. ＲｅＲＡＭの概念的要部断面図である。It is a conceptual principal part sectional drawing of ReRAM. フォーミング動作、セット動作、リセット動作の説明図である。It is explanatory drawing of forming operation | movement, set operation | movement, and reset operation | movement. ＲｅＲＡＭの要部回路構成図である。It is a principal circuit block diagram of ReRAM.

符号の説明Explanation of symbols

１ メモリセル
２ 抵抗変化素子
３ セル選択トランジスタ
４ コラムセレクタトランジスタ
５ 電源電圧印加用トランジスタ
６ 電源電圧
１１ ウェーハ
１２ 温度可変プローブステーション
１３，１４ プローブ端子
１５ テスタ
１６ ホットプレート
２１ メモリセル
２２ 抵抗変化素子
２３ セル選択Ｔｒ
２４ コラムセレクタＴｒ
２５ 電源電圧印加用Ｔｒ
２６ 電源電圧
３０ セル選択Ｔｒ
３１ ｐ型シリコン基板
３２ 素子分離絶縁膜
３３ ドレイン
３４ ソース
３５ 多層配線構造
３６ ソース電極
３７ ビット線
４０ 抵抗変化素子
４１ 酸化膜
４２ 下部Ｐｔ電極
４３ 上部Ｐｔ電極
５１ コラムセレクタＴｒ
５２ 電源電圧印加用Ｔｒ
５３ 電源電圧 DESCRIPTION OF SYMBOLS 1 Memory cell 2 Resistance change element 3 Cell selection transistor 4 Column selector transistor 5 Power supply voltage application transistor 6 Power supply voltage 11 Wafer 12 Temperature variable probe stations 13 and 14 Probe terminal 15 Tester 16 Hot plate 21 Memory cell 22 Resistance change element 23 Cell Selection Tr
24 Column selector Tr
25 Tr for power supply voltage application
26 Power supply voltage 30 Cell selection Tr
31 p-type silicon substrate 32 element isolation insulating film 33 drain 34 source 35 multilayer wiring structure 36 source electrode 37 bit line 40 resistance change element 41 oxide film 42 lower Pt electrode 43 upper Pt electrode 51 column selector Tr
52 Tr for power supply voltage application
53 Power supply voltage

Claims (5)

金属酸化膜を導電膜で挟み込んだ抵抗変化素子とセル選択トランジスタからなるメモリセルを備えた抵抗変化メモリのフォーミング方法であって、抵抗変化メモリのフォーミング動作を８０〜２００℃に加熱した状態で行うことを特徴とする抵抗変化メモリのフォーミング方法。 A method of forming a resistance change memory having a memory cell composed of a resistance change element and a cell selection transistor in which a metal oxide film is sandwiched between conductive films, wherein the forming operation of the resistance change memory is performed in a state heated to 80 to 200 ° C. A forming method for a resistance change memory. 上記フォーミング動作をウェーハ状態で行うことを特徴とする請求項１記載のフォーミング方法。 2. The forming method according to claim 1, wherein the forming operation is performed in a wafer state. 金属酸化膜を導電膜で挟み込んだ抵抗変化素子とセル選択トランジスタからなるメモリセルを備えた抵抗変化メモリであって、前記抵抗変化素子に電源電圧を印加する電源電圧印加トランジスタ及びコラムセレクタトランジスタの耐圧と前記セル選択トランジスタの耐圧が同じであることを特徴とする抵抗変化メモリ。 A resistance change memory comprising a resistance change element having a metal oxide film sandwiched between conductive films and a memory cell made up of a cell selection transistor, the withstand voltage of a power supply voltage application transistor and a column selector transistor for applying a power supply voltage to the resistance change element And the cell selection transistor have the same breakdown voltage. 上記金属酸化膜が、遷移金属酸化膜であることを特徴とする請求項３記載の抵抗変化メモリ。 4. The resistance change memory according to claim 3, wherein the metal oxide film is a transition metal oxide film. 金属酸化膜を導電膜で挟み込んだ抵抗変化素子を基板上に形成し、前記抵抗変化素子を８０〜２００℃に加熱した状態で、該抵抗変化素子に電圧を印加することを特徴とする抵抗変化メモリの製造方法。 A resistance change element characterized in that a resistance change element in which a metal oxide film is sandwiched between conductive films is formed on a substrate, and a voltage is applied to the resistance change element while the resistance change element is heated to 80 to 200 ° C. Memory manufacturing method.
JP2007065139A 2007-03-14 2007-03-14 Resistance change memory forming method, resistance change memory, and resistance change memory manufacturing method Expired - Fee Related JP5317420B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007065139A JP5317420B2 (en) 2007-03-14 2007-03-14 Resistance change memory forming method, resistance change memory, and resistance change memory manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007065139A JP5317420B2 (en) 2007-03-14 2007-03-14 Resistance change memory forming method, resistance change memory, and resistance change memory manufacturing method

Publications (2)

Publication Number Publication Date
JP2008227267A true JP2008227267A (en) 2008-09-25
JP5317420B2 JP5317420B2 (en) 2013-10-16

Family

ID=39845514

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007065139A Expired - Fee Related JP5317420B2 (en) 2007-03-14 2007-03-14 Resistance change memory forming method, resistance change memory, and resistance change memory manufacturing method

Country Status (1)

Country Link
JP (1) JP5317420B2 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011009344A (en) * 2009-06-24 2011-01-13 Sharp Corp Forming method of nonvolatile variable resistance element
US8410467B2 (en) 2009-08-12 2013-04-02 Kabushiki Kaisha Toshiba Nonvolatile memory device and method of manufacturing the same
US8625329B2 (en) 2010-07-28 2014-01-07 Kabushiki Kaisha Semiconductor storage device including variable resistive elements
US9558824B2 (en) 2015-03-23 2017-01-31 Renesas Electronics Corporation Semiconductor device and operating method thereof
WO2019009296A1 (en) * 2017-07-06 2019-01-10 日本電気株式会社 Switch element, switching method and semiconductor device
CN110137348A (en) * 2019-04-11 2019-08-16 上海集成电路研发中心有限公司 A kind of neural network multiplexing multivalue resistive structure and its formation

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004158143A (en) * 2002-11-07 2004-06-03 Sharp Corp Semiconductor memory device and its control method
WO2006070151A1 (en) * 2004-12-23 2006-07-06 Commissariat A L'energie Atomique Pmc memory with improved retention time and writing speed
WO2007023569A1 (en) * 2005-08-26 2007-03-01 Fujitsu Limited Nonvolatile semiconductor storage device and its write method
WO2008068807A1 (en) * 2006-11-30 2008-06-12 Renesas Technology Corp. Semiconductor device fabricating method and semiconductor device
JP2008159760A (en) * 2006-12-22 2008-07-10 Sharp Corp Variable-resistance nonvolatile memory element, creating method thereof, and nonvolatile semiconductor memory

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004158143A (en) * 2002-11-07 2004-06-03 Sharp Corp Semiconductor memory device and its control method
WO2006070151A1 (en) * 2004-12-23 2006-07-06 Commissariat A L'energie Atomique Pmc memory with improved retention time and writing speed
WO2007023569A1 (en) * 2005-08-26 2007-03-01 Fujitsu Limited Nonvolatile semiconductor storage device and its write method
WO2008068807A1 (en) * 2006-11-30 2008-06-12 Renesas Technology Corp. Semiconductor device fabricating method and semiconductor device
JP2008159760A (en) * 2006-12-22 2008-07-10 Sharp Corp Variable-resistance nonvolatile memory element, creating method thereof, and nonvolatile semiconductor memory

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011009344A (en) * 2009-06-24 2011-01-13 Sharp Corp Forming method of nonvolatile variable resistance element
US8410467B2 (en) 2009-08-12 2013-04-02 Kabushiki Kaisha Toshiba Nonvolatile memory device and method of manufacturing the same
US8625329B2 (en) 2010-07-28 2014-01-07 Kabushiki Kaisha Semiconductor storage device including variable resistive elements
US9558824B2 (en) 2015-03-23 2017-01-31 Renesas Electronics Corporation Semiconductor device and operating method thereof
WO2019009296A1 (en) * 2017-07-06 2019-01-10 日本電気株式会社 Switch element, switching method and semiconductor device
US10971547B2 (en) 2017-07-06 2021-04-06 Nanobridge Semiconductor, Inc. Switch element, switching method and semiconductor device
CN110137348A (en) * 2019-04-11 2019-08-16 上海集成电路研发中心有限公司 A kind of neural network multiplexing multivalue resistive structure and its formation
CN110137348B (en) * 2019-04-11 2023-01-31 上海集成电路研发中心有限公司 Multiplexing multivalue resistance change structure and neural network formed by same

Also Published As

Publication number Publication date
JP5317420B2 (en) 2013-10-16

Similar Documents

Publication Publication Date Title
TWI518956B (en) Resistive ram and fabrication method
US8107274B2 (en) Variable and reversible resistive element, non-volatile memory device and methods for operating and manufacturing the non-volatile memory device
Khan et al. Charge trap transistor (CTT): An embedded fully logic-compatible multiple-time programmable non-volatile memory element for high-$ k $-metal-gate CMOS technologies
JP5830655B2 (en) Method for driving nonvolatile memory element
JP5317420B2 (en) Resistance change memory forming method, resistance change memory, and resistance change memory manufacturing method
JP2015525969A (en) Integrated circuit device employing antifuse and method of making the device
CN100538889C (en) Non-volatile memory cells, memory cell matrix and memory storage
Slaughter et al. Technology for reliable spin-torque MRAM products
KR20150047562A (en) Unipolar memory devices
KR101385251B1 (en) Multi-level antifuse and method for operation the same
US8811058B2 (en) Resistance change element, method for manufacturing the same, and semiconductor memory
US10957854B2 (en) Tunable resistive element
Li et al. Evaluation of SiO/sub 2/antifuse in a 3D-OTP memory
JP2006173485A (en) Electronic device and its manufacturing method
JP4995512B2 (en) Semiconductor device
Kuo et al. Antifuse OTP cell in a cross-point array by advanced CMOS FinFET process
Chen et al. Multilevel Anti-Fuse Cells by Progressive Rupturing of the High-$\kappa $ Gate Dielectric in FinFET Technologies
CN104425446B (en) Electric fuse structure and its application method
Peng et al. High-density FinFET one-time programmable memory cell with intra-fin-cell-isolation technology
US10446564B2 (en) Non-volatile memory allowing a high integration density
Deloge et al. Application of a TDDB Model to the Optimization of the Programming Voltage and Dimensions of Antifuse Bitcells
US20070052001A1 (en) Nonvolatile semiconductor memory device and method of fabricating the same
JP5492929B2 (en) Manufacturing method of semiconductor device
JP6051574B2 (en) Nonvolatile storage device
TWI284964B (en) A non-volatile memory array

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20091208

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20110915

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20120516

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120522

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20120821

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130613

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20130709

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

LAPS Cancellation because of no payment of annual fees