TWI284964B - A non-volatile memory array - Google Patents

Abstract

A non-volatile memory array including a plurality of memory units is provided. The memory units are arranged in a row/column array. Source lines are arranged in parallel in the column direction and connect the source regions of the memory units in the one column. Bit lines are arranged in parallel in the row direction and connect the drain regions of the memory units in the one row. Word lines are arranged in parallel in the column direction and connect the select gates of the memory units in the one column. Control lines are arranged in parallel in the column direction and connect the control gates of the memory units in the one column. The control lines is divided into several groups by n (n is an integer not less than 2), and the control lines in each group are connect to each other electrically.

Description

1284^wf.doc/y IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor element, and in particular to a non-volatile memory array. [Prior Art] Among various non-volatile memory products, there are many operations that can perform data storage, reading, erasing, etc., and the stored data can not disappear after power-off. Erasing and programmable read-only (EEPRQM) has become a widely used memory component for personal computers and electronic devices. A typical electrically erasable and programmable read-only memory system uses a doped P〇lysilicon to fabricate a floating 闲 ( gate gate). Because this non-volatile memory device is difficult to integrate with the general-purpose CMOS logic process (L〇gicPr〇cess) = the double-layered gate of the 疋 double-layer, making the entire embedded non-volatile memory manufacturing cost increase Not conducive to its competitive advantage. , ° This @@本心体 is stylized (P r f1 pole Γ 分布 分布 分布 分布 分布 分布 分布 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 而 而 而 而 而 而π is the leakage current of the component, which affects the reliability of the component. The problem can be: erase the leakage current of the programmable read-only memory component t ^ «^-#t^, A##(charge trapping materiaJ) stone In the evening, G catches the neutrons. What is trapped in the material is, for example, nitride rock. Because of the characteristics of electron capture, the electrons injected into the nitride layer are concentrated only in the local area of 3 6 I284% 4wf.doc/y. Therefore, the sensitivity to the defects in the tunneling oxide layer is small, and the phenomenon of leakage current of the element is less likely to occur. Moreover, there is usually a layer of oxidized oxide on the upper and lower layers of the nitride layer, and the formation of oxidized stone/nitrite/ Oxidation oxide (oxide_nitride_oxide, ΟΝΟ) composite layer. On the other hand, in order to avoid the typical erasable and programmable read-only memory during erasing/writing, the over-erase/write phenomenon is too serious. , causing misjudgment of data. While controlling gates and floating gates One side is connected in series with a select transistor to form a two-transistor (2τ) structure. The memory is selected and read by selecting a transistor (select transist〇r). When a memory cell array of a non-volatile memory cell having two crystal structures is used, the memory cell is erroneously written or programmed due to program disturb or erase disturb under different bias voltages. The erasing situation may result in a decrease in the reliability of the memory unit. SUMMARY OF THE INVENTION The object of the present invention is to provide a non-volatile memory array that can reduce stylized interference or erase interference. Therefore, the reliability of the memory unit is improved. The present invention provides a non-volatile memory array including a plurality of memory sheets 7C, a plurality of source lines, a plurality of bit lines, a plurality of word lines, and a strip control line. A plurality of memory cells are arranged in a row/column array, and each of the memory cells includes a first conductive type well region, a second conductive germanium source region, a first V-electric doped region, and a first Conductive type bungee region, select gate, control 5 7 1284撇; wf.doc/y interpole, charge storage structure. Control gate and select gate are formed by the same interlayer material. Charge storage structure, at least the towel Including a charge storage layer. The first conductive type well region is disposed in the substrate, and the second conductive type source region, the second conductive type doped region and the second conductive type drain region are disposed in the first. The control gate is disposed on the substrate between the second conductive type source region and the second conductive type interface region, and the control gate is disposed on the substrate of the second conductive type doping region and the second conductive type drain region. The charge storage structure is disposed between the control idler and the substrate. In the memory unit of the same row, the adjacent two memory modules are arranged in a mirror-symmetrical manner. The plurality of source lines are connected in parallel in the column direction to the second conductivity type source lines of the memory cells in the same column, and are connected in parallel in the row direction, and are connected to each other in the same row. Most of the word line lines are in the column direction. Two = 'The selection gates of the memory cells connected to the same column. The plurality of strips - 4 are arranged in parallel in the column direction, and the control lines connecting the same column are each set to be larger than each other in n_; integers are grouped and electrically connected together. Non-volatile memory in the above

Type, second conductivity type ο type. The N electrical layer is in the body array, and further includes a gate dielectric including oxygen and a substrate, and a gate dielectric layer is selected: a non-volatile memory array, and the charge storage structure is further covered by a material including Yttrium oxide. Tunneling dielectric 1284· wf.doc/y In the closed non-sex memory array, the charge storage structure is further packaged between the layer Si-loaded fault-storing layer and the control gate. The closed space includes the hair memory _ towel, and the material of the electric radiation transfer layer includes the disordered stone eve, the nitrous oxide eve ((nan〇-cry curry) or the doped polycrystalline 矽. The memory of the same row of the wood day layer The memory cells of the same row of cells are in the non-volatile memory array described above, and the adjacent two memory cells share the source region. In the above non-volatile memory array, the adjacent two memory cells share the drain The non-volatile memory array of the present invention, when programmed using (10) (four) her n) mechanism (pr: g = ming) must apply a high voltage in the bit line of the remote memory cell, because the same two bits = (10) They are all connected together. So all the two bodies of the same line will receive stylized interference (the division is the secret of the division); by this = Ming 'the control lines are connected together by the set number' When the memory is read early, the stroke operation is performed as long as the selected control line group connected to the selected memory unit is biased to be programmed, and the line group is given a bias that does not cause stylized interference. Caused by other factors not selected during the stylization process Early type of memory element through the interference frequency and stylized, reduce the impact of interference is stylized. Moreover, in the decoding operation of the memory array, as long as the bias is applied to the selected control line group, the memory unit connected to the selected control line group can be connected to I284^4£fd〇c/y. It is decoded, so it can be single. Moreover, the type of the applied slanting type is also relatively simpler. simplification = external 'When the memory array is erased, the control line group applies a bias voltage, and it is necessary to & dust, so (4) (4) The line group does not apply bias material (4) to remember to erase the _ mouth. The present invention proposes a kind of facial memory, including the memory unit, the majority of the source line, the recorded element line, and the township number line: ^ Several control lines. A plurality of memory cells are arranged in a row/column array, and each memory cell includes a first conductive type well region, a second conductive type source region, two second conductive type doped regions, and a second conductive type drain region, and is selected. Gate, control gate, charge storage structure. The control gate and the selection gate are formed by the same gate material. A charge storage structure comprising at least one charge storage layer. The first conductivity type well region is disposed in the substrate. The second conductive type source region, the second conductive type doped region and the second conductive type drain region are disposed in the first conductive type well region. The selection gate is disposed on the substrate between the second conductivity type source region and the second conductivity type doping region. The control gate is disposed on the substrate between the second conductive type doped region and the second conductive type drain region. A charge storage structure is disposed between the control gate and the substrate. In the memory unit of the same row, the adjacent two memory cells are arranged in a mirror-symmetrical manner. A plurality of source lines are arranged in parallel in the column direction, and connect the second conductivity type source regions of the memory cells of the same column, and the source lines are electrically connected to the first conductivity type well regions. A plurality of bit lines are arranged in parallel in the row direction to connect the second conductive type drain regions of the memory cells of the same row. Most of the word lines are arranged in parallel in the column direction, connecting the selected gates of the memory cells of the same 1284964]T?8itwf.doc/y column. A plurality of control lines are arranged in rows, and the control terminals of the memory cells connected to the same column are connected. . Flat

In the above non-volatile memory array, the first type and the second conductivity type are p-type. The type is N. In the above-mentioned non-volatile memory, the electric layer is set between the selected gate and the substrate. The choice between the dielectrics includes the yttrium oxide layer. In the above-mentioned sinusoidal memory, the charge storage teeth are disposed between the charge storage layer and the substrate with the dielectric layer. ^ The material of the cladding layer includes yttrium oxide. The tunnel dielectric is in the above non-volatile memory array, and the three dielectric layers are disposed on the charge storage layer and the control material of the dielectric layer includes yttrium oxide. The material of the charge storage layer (~丄丄2, emulsifier), and the nanocrystalline layer are in the above non-volatile memory array, and the adjacent two memory cells share the source region. The potential of the well zone will be greatly improved by the network of the first-electroconductive memorandum component (4). For the record I284^si, doc/y ▲, the above and other objects, features and advantages of the present invention can be more clearly understood. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The following is a detailed description of the preferred embodiment of the present invention. FIG. 1A is a simplified circuit diagram of a preferred embodiment of the non-volatile memory array of the present invention. 1B is a cross-sectional view showing a structure of a preferred embodiment of the non-volatile ZFE unit of the present invention. FIG. 1B is a cross-sectional view of FIG. 1A. First, the structure of the memory unit of the present invention will be described. Please refer to FIG. Recall that the early element includes the base 1 〇〇, the ν type well area 1 〇 2, the Ρ type source area 104, the Ρ type doped area 1〇6, ρ type; and the polar area 1〇8, the selection gate u〇, • Select gate dielectric layer 112, control gate 114, tunnel dielectric layer 116, charge storage layer 118, inter-gate dielectric layer 120. Substrate 100 is, for example, a germanium substrate. It is disposed in the substrate 100. The 源-type source region 104, the Ρ-type doping region 〇6, and the p-type drain region 108 > are disposed, for example, in the substrate 1 。. The selection gate 110 is, for example, disposed on Ρ The source region 1 〇 4 and the p-type doping region 106. The material of the gate 110 is, for example, doped polysilicon. The gate dielectric layer 112 is, for example, disposed between the gate 110 and the substrate 100. The material of the gate dielectric layer 2 is, for example, tantalum oxide. The control gate 114 is, for example, disposed between the p-type doping region ι6 and the p-type drain region 108. The material of the control gate 114 is, for example, doped. The control gate 114 and the selection gate no are, for example, manufactured by the same gate process step 8 12 I284m, doc/y, which can reduce the manufacturing cost. The charge storage structure includes a tunnel dielectric layer 116, a charge storage layer 118, and an inter-gate dielectric layer 120 from bottom to top. The charge storage layer 118 is disposed between the control gate 114 and the substrate 100, for example. The material is, for example, a conductor material (such as doped polysilicon) or a charge trapping material (such as nitrite, SixOyNz, nano-crystal), etc. The tunneling dielectric layer 116 is, for example, a set. The material of the tunneling dielectric layer 116 is, for example, hafnium oxide. The inter-gate dielectric layer 120 is disposed between the charge storage layer 118 and the control gate 114, for example. The material of the inter-gate dielectric layer 120 is, for example, yttrium oxide. The drain region 108 is electrically connected to the bit line, for example, by the plug 122. The BL1 ° source region 1〇4 is electrically connected to the corresponding source line SL1 to SL3 by the plug 124, respectively. Next, the non-volatile memory array of the present invention will be described. Referring to FIG. 1A, the non-volatile memory array of the present invention includes a plurality of memory cells δ δ recall cells Mxy, a plurality of word line lines WL1 WLWLy, a plurality of control lines, CL1 ～CLy, and a plurality of bit elements. Lines BL1 to BLx, a plurality of source lines SL1 to SLj, and an N-type well region NW. The memory cells Mn~memory cells are arranged in a row/column array. In the direction of the row, the memory cells Mn, Mi2.....Mly are connected in series to the memory cell row R1; the memory cells, M22, ..., M2y are connected in series to the memory cell row R2; and so on, the memory cells Μχΐ, Μχ2 .....Mxy is concatenated into a memory cell row Rx. In the direction of the column, the memory cells, M21.....Mxl are arranged into 8 13 I2849Mwf.d〇〇/y memory cell column C1; memory cells Mu, Μ. , ···, mx2 are arranged in the memory cell column C2; and so on, the memory cells Mly, M2y, ..., Mxy are arranged in the memory cell column Cy.

The two memory cells adjacent to each other in the memory cell row R1 to the like are arranged in a mirror-symmetric manner, and the adjacent two memory cells share a source region or a drain region. For example, in the memory cell row R1, the memory cell M" is arranged in a mirror-symmetrical manner with the memory cell Mu, and shares the drain region; the memory cell Mn and the memory cell Mu are arranged in a mirror-symmetrical manner, and The source region is shared; and so on, the memory unit and the memory unit Mly are arranged in a mirror-symmetrical manner and share the drain region. The N-type well region NW is, for example, disposed in a substrate below the memory cell MXy. The bits BL1 to BLx, for example, are arranged in parallel in the row direction to connect the drain regions of the memory cells of the same row. For example, the bit line BL1 is connected to the sum region of the memory cell row R1 to the memory cell Mi i~Miy; the bit line BL2 is connected to the drain region of the cell row R2 to the memory cell (4)~; Bit line BLx is connected to the memory cell row Rx memory cell

The bungee area of Mxl~Mxy. Same as -= mouth? If it is in the wealth of the fight::. And for every two adjacent memory cell columns, the source, the _connected memory cell, the memory cell column (5), the _ meta-connection column C3, the memory cell M, the 3~m2^ source region, and the source of the memory cell x3 Polar region; source line SL3 connection

14

I284%i, doc/y Recall the source region of the memory cell unit it M14~MX4 in the cell column C4 and the source region of the memory cell 歹C5 in the memory cell μ!5~Mm; and so on, the source line SLJ The source regions of the memory cells Mly to Mxy in the memory cell column Cy are connected. The word lines WL1 to WLy are, for example, arranged in parallel in the column direction, and connect the selection gates of the respective memory cells in the same column. For example, the word line WL i is connected to the selection gate of the memory unit M11 Μχ Μχ in the memory cell column C1; the word line WL2 is connected to the memory cell column C2 + the memory cell Μΐ 2 Μχ 2 is selected, the gate; and so on. The word line WLy is connected to the selection gate of the memory unit Mly to Mxy in the memory cell column Cy. The control lines CL1 to CLy are, for example, arranged in parallel in the column direction, and are connected to the control side electrodes of the respective memory cells in the same column. For example, the control gate cu element column C1 in the memory cell Μιι~Μχι control gate; the control element "control closed, and so on, the control line CLy connected to the memory cell column Cy in the memory Mly ~ Mxy control gate The control line cu~ is a positive integer greater than or equal to 2) is a group, and the electrical connection is at -. Example ί ί ilT is a group of four as a control line. _ Electrical connection in - The control lines CL5~CL8 are electrically connected to the number of control points that can be connected to each other, and are determined by the visual (5). For example, there may be 32 or 64 memory cell arrays. , 128 or 256 $ - π are formed in # ϋ 〜 早凡列. Therefore, in 4 early 7C arrays can have 32, 64, 128 lines, and then these control lines are every n pieces (Π Positive or equal to or greater than V is divided into one group, for example, every 2, 4 final s κ, spoon positive mother & 4, 8, 16, or 32, etc. 8 15

V 1284? The control lines that are present and also grouped are electrically connected together.于:整;; '!Connection ί: The fewer the number of control lines, the more you can avoid; =: 疋a has recalled the stylized interference of 7C now",, / with erase operation t, electrical connection In the second "the number of control lines in the wide horse with f2 together, the more

= and the erase operation, and the number of control lines that can be electrically connected to the type of bias * can be taken into account by stylized operations, translation operations and erase operations, etc., and the preferred number . /Ν

In the present invention, since the control lines are connected together in a set number, the operation can be simplified. For example, as indicated by @1Α, the control line (1) to the control line CL4 are electrically connected together; the control line CL5 to the control line CL8 are electrically connected together. When the selected memory cells connected to the control line CL1 to the control line CL4 (selected control line group) are programmed, a bias voltage is applied to the control lines CL1 to CL4, and other unselected control line groups (for example, The control line CL5 to the control line CL8) are biased without causing stylized interference, thereby avoiding stylized interference to other groups of memory cells. For example, A ' initially set up a non-volatile memory array with 256 memory cell columns. The minimum array area is considered as a design consideration. In order to achieve the minimum area, 256 memory cells are bound to be listed. The control lines (CL1~CL256) are all electrically connected together, but as a result, 8 16 I284%i, doc/y may be in the worst case of unselected memory cells (eg memory cells) during the stylization process. There will be 255 stylized interferences (stylized, y=256, except Μ%); however, if the control lines of 2 memory cells are split into 64 groups, each group of 4 control lines is electrically connected (for example, Μ %, Μ%, Μ" and Μ% control lines are electrically connected), then 呈% will see that the *formed interference is reduced to 3 times, greatly improving the non-volatile memory operating characteristics. When the memory array performs a decoding operation, as long as a bias voltage is applied to the control line CL1 to the control line CL4 (the selected control line group), the control line CL1 to the control line CL4 (the selected control line group) can be connected. The memory unit decodes, so the decoding operation can be simplified. Moreover, the type of bias applied is also relatively simple, and the decoding circuit can be more space-saving. In addition, when erasing the memory array, only the control line CL1 to the control line CL4 (selected control line group) The bias voltage is applied, and the other selected control line groups (for example, the control line CL5 to the control line CL8)* are biased, so that the soft erase phenomenon can be avoided for the other groups of memory cells. Another improvement aspect, as shown in Figure 1C, is that all source lines (SL1 ~ SLj) will be electrically connected to the N-type well region. Usually, the well region NW is only n-type around the s-resonance array. The well areas are connected, and the shoulder potential seen by all the memory cells in the k-body array may not be very uniform. In particular, in the case of a large current operation mode, the NW potential of the array and the central memory unit may be very high. Large difference; usually the source line will be self-aligned to the metal deuterium active area (Salicided 8 17 12849M wf.doc / y and through the upper metal wire network connection the entire array area, if electrically connected to all source line hunger 1~SLj), then Within the memory unit = there is a network-like source line and the average sentence distribution, for the record, the body characteristics of the body 70 will be greatly improved. %, although the invention has been disclosed in the preferred embodiment as above, iron defines the invention, any Familiar with this technique (4), not leaving;

In the meantime, when some changes and refinements can be made, the invention of the invention is subject to the definition of the application. ... [Simple description of the diagram] It is a schematic diagram of the non-volatile memory array of the present invention. Millennium implementation =:::: non-volatile memory unit of the invention - preferred non-volatile memory array of the invention

[Main component symbol description] 1〇〇: base 102, NW: Ν type well area 104 · Ρ type source area 106 : Ρ type doped area 108 · · Ρ type drain area 110: select gate 112: selection Gate dielectric layer 114: control gate 8 18 I284^44wf.doc/y 116: tunneling dielectric layer '118: charge storage layer/120: gate dielectric layer 122, 124: plug Μη~Mxy: Memory cells WL1 to WLy · Word lines CL1 to CLy: Control lines BL1 to BLx: Bit line parameters SL1 to SLj: Source lines R1 to Rx: Memory cell lines C1 to Cy: Memory cell columns

Claims (1)

1284944 twf.doc/y Patent Application Range: 1. A non-volatile memory array comprising: a memory of a plurality of δ hexagram units arranged in a row/column array, each of which includes a first conductivity type well a second conductive type source region, a second conductive type doped region and a second conductive type drain region are disposed in the first conductive type well region; a gate is disposed on the substrate between the second conductive type source region and the second conductive type doped region; a first control gate is disposed on the second conductive type doped region and the a substrate between the conductive drain regions, and the control electrode is formed of a homo-phase material; and a charge storage structure is included in the gate electrode, wherein at least one charge is included: the control idle Between the substrate and the substrate, wherein the memory cells are in the same direction as the mirror lines, and the source lines are arranged in parallel in the column direction, and the first column is connected to the same column. Two conductive source regions; connecting the same column connecting the same column a plurality of bit lines arranged in parallel in the row direction for the second conductivity type drain region of each of the cells; > a number of word line lines arranged in parallel in the column direction, the selection of the cell a gate electrode; and each of the ΐϊΐ control lines, which are arranged in parallel in the column direction as a large control gate, wherein the control lines are each set of n (n is a positive integer of 4 to 2) The non-volatile memory array of claim 1, wherein the first conductivity type is N-type. 3. The non-volatile memory array of claim 1, wherein the second conductivity type is P-type. 4. The non-volatile memory array of claim 1, further comprising a select gate dielectric layer disposed between the select gate and the substrate. 5. The non-volatile memory array of claim 1, wherein the charge storage structure further comprises a pass-through dielectric layer disposed between the charge storage layer and the substrate. 6. The non-volatile memory array of claim 1, wherein the material of the tunneling dielectric layer comprises yttrium oxide. 7. The non-volatile memory array of claim 1, wherein the charge storage structure further comprises an inter-gate dielectric layer disposed between the charge storage layer and the control gate. 8. The non-volatile memory array of claim 1, wherein the material of the inter-gate dielectric layer comprises yttrium oxide. 9. The non-volatile memory array of claim 1, wherein the material of the charge storage layer comprises tantalum nitride, hafnium oxynitride or a nanocrystalline layer. 10. The non-volatile memory array of claim 1, wherein the material of the charge storage layer comprises doped polycrystalline stone. 11. The non-volatile memory array according to claim 1, wherein in the memory cells of the same row, the adjacent two memory cells 8 21 I284^44wf.doc/y ^ yuan share the same Source area. 12. The non-volatile memory array according to claim 1, wherein in the memory cells of the same row, the adjacent two memory cells share the drain region. 13. A non-volatile memory array comprising: a plurality of memory cells arranged in a row/column array, each of the memory cells comprising: a first conductivity type well region disposed in a substrate; a conductive source region-second conductive type doped region and a second conductive type drain region are disposed in the first conductive type well region; a selection gate is disposed in the second conductive type source region and a substrate between the first and second conductive type doped regions; a control gate disposed on the substrate between the second conductive type doped region and the second conductive type drain region, and the The control gate and the selection gate are formed by the same gate material; and a charge storage structure including at least one charge storage layer, Φ is disposed between the control gate and the substrate, wherein the memory cells are in the same row The two adjacent memory cells are arranged in a mirror-symmetric manner; a plurality of source lines are arranged in parallel in the column direction, and the second conductive type source regions of the memory cells connected to the same column are connected And the source lines are electrically connected The first conductive type well region; a plurality of bit lines arranged in parallel in the row direction, connecting the second row of the memory cells of the same row and the polar regions, the plurality of word lines, in the column direction Arranging in parallel, connecting 22 f.doc/y of the same column to the selection gate of each memory cell; and a plurality of control lines arranged in parallel in the column direction to connect the control gates of the memory cells of the same column 14. The non-volatile memory array of claim 13, wherein the first conductivity type is N-type. 15. The non-volatile memory array of claim 13, wherein The non-volatile memory array of claim 13 further comprising a selective gate dielectric layer disposed between the select gate and the substrate. 17. The non-volatile memory array of claim 13, wherein the charge storage structure further comprises a tunneling dielectric layer disposed between the charge storage layer and the substrate. 13 non-swing The memory memory array, wherein the material of the tunneling dielectric layer comprises ruthenium oxide. 19. The non-volatile memory array according to claim 13, wherein the charge storage structure further comprises a gate dielectric layer. The non-volatile memory array according to claim 13, wherein the material of the inter-gate dielectric layer comprises ruthenium oxide. The non-volatile memory array of claim 13, wherein the material of the charge storage layer comprises tantalum nitride, hafnium oxynitride or a nanocrystalline layer. 22. Non-volatile as described in claim 13 Memory Memory Array (§) 23 I2849M twf.doc/y column, wherein the material of the charge storage layer comprises doped polycrystalline stone. 23. The non-volatile memory array of claim 13, wherein in the memory cells of the same row, two adjacent memory cells share the source region. 24. The non-volatile memory array of claim 13, wherein in the memory cells of the same row, two adjacent memory cells share the drain region. twenty four