CN110137348B - A Multiplexing Multi-valued Resistive Switching Structure and Its Neural Network Formed - Google Patents

Abstract

The invention discloses a multiplexing multivalue resistance change structure, which comprises a resistance change memory unit and an MOS (metal oxide semiconductor) selection unit, wherein the resistance change memory unit comprises M resistance change memory sub-units, and the MOS selection unit comprises N multiplexing MOS tubes which are connected in parallel; the resistive random access memory subunit comprises a resistive random access memory and control MOS tubes, one end of the resistive random access memory is connected with control signals corresponding to the resistive random access memory subunit, the other end of the resistive random access memory is connected with drain electrodes of the control MOS tubes, grid electrodes of the control MOS tubes are connected with selection signals corresponding to the resistive random access memory subunit, and source electrodes of the M control MOS tubes and drain electrodes of the N multiplexing MOS tubes are connected to the same node; the source electrodes of the N multiplexing MOS tubes are connected to the output port, and the grid electrode of each multiplexing MOS tube is connected with the corresponding conducting signal. The invention realizes multi-value analog quantity output by using the simplified MOS selection unit, reduces circuit modules such as a sensitive amplifier, a digital-analog converter and the like, and saves circuit area.

Description

A Multiplexing Multi-valued Resistive Switching Structure and Its Neural Network Formed

technical field

The invention relates to a resistive variable memory, in particular to a multiplexing multi-value resistive variable structure and a neural network formed therefrom.

Background technique

In recent years, the development of new types of memory such as resistive RAM (RRAM) has become a new impetus in the field of memory. Due to the characteristics of low power consumption, high speed and small area, resistive memory has very broad application prospects in the future. In addition to the traditional storage field, it can also play an important role in the neural network system architecture in the field of artificial intelligence. Resistive variable memory has already been researched, and the unit is developed in the direction of multi-value storage, that is, one unit completes the storage of multi-bit data through different resistance sizes.

The resistance-change analog characteristic of the multi-valued memory is an ideal device that can be used as a brain-like synapse in the brain-like neural network system because it can output the current value of the analog quantity change. At present, there is no mature preparation result of multi-valued memory, so at this stage, multiple single-valued RRAM cells can be used to simulate this multi-valued characteristic, as shown in Figure 1.

However, when this type of structure is applied to a neural network, there are some disadvantages as follows. First of all, each single-valued RRAM unit needs to be equipped with a sense amplifier (SA) for data readout, and secondly, a digital-to-analog converter (DAC) is required to convert the single-valued data digital signal data into an analog with multi-valued characteristics. quantity. These additional circuit structures will increase the overhead of the entire neural network system in terms of area and power consumption. Even if it is averaged on a single RRAM, the overhead will be relatively large. Therefore, it is realistic to design a method that can directly convert the resistance characteristics of RRAM into electrical quantities with multi-valued analog properties through some simple additional circuit structures, thereby saving area and power consumption. meaningful things.

Contents of the invention

The purpose of the present invention is to provide a multiplexing multi-valued resistive variable structure and the neural network formed thereof, which utilizes a simplified MOS selection unit to realize multi-valued analog output, thereby realizing multiplexing of circuit modules and reducing sensitivity Circuit modules such as amplifiers and digital-to-analog converters save circuit area.

In order to achieve the above object, the present invention adopts the following technical solution: a multiplexing multi-valued resistive switch structure, including a resistive switch memory unit and a MOS selection unit, the resistive switch memory unit includes M resistive switch memory subunits, the The MOS selection unit includes N parallel multiplexing MOS transistors; wherein, M and N are integers greater than 1;

The resistive memory subunit includes a resistive memory and a control MOS transistor, wherein one end of the resistive memory is connected to the control signal corresponding to the resistive memory subunit, and the other end is connected to the drain of the control MOS transistor. The gate of the control MOS transistor is connected to the selection signal corresponding to the RRAM subunit, and the sources of the M control MOS transistors and the drains of the N multiplexing MOS transistors are connected to the same node, and the N The sources of the multiplexed MOS transistors are commonly connected to the output port, and the gates of each multiplexed MOS transistor are connected to corresponding conduction signals.

Further, when the N multiplexing MOS transistors are turned on, the corresponding conductance values are different.

Further, when the N multiplexing MOS transistors are turned on, the corresponding conductance values are G _T , 2G _T , 2 ² G _T to 2 ^N-1 G _T , and by controlling the conduction signal, all The MOS selection unit can generate 2 ^N -1 different conductance values, wherein G _T is greater than zero.

其中，R_on表示所述阻变存储器处于低阻状态时的电阻值，R_off表示所述阻变存储器处于高阻状态时的电阻值。Further, the conductance value in the N multiplexing MOS transistors satisfies:

Wherein, R _on represents the resistance value when the RRAM is in a low-resistance state, and R _off represents the resistance value when the RRAM is in a high-resistance state.

Further, by controlling the control signal so that only one of the M resistive variable memory subunits is in a readable and writable state, the multiplexed multi-valued resistive variable structure can generate 2 ^N+1-2 resistors value.

Further, the source and drain of the control MOS transistor and the multiplexing MOS transistor can be interchanged.

Further, the multiplexed multi-valued resistive switch structure further includes a peripheral circuit for controlling only one of the M resistive switch memory subunits to be in a readable and writable state.

Further, the peripheral circuit further includes a storage unit for storing the ON and OFF states of the N multiplexed MOS transistors.

A neural network includes a multi-valued resistive variable array, A front neuron circuits, B rear neuron circuits and peripheral control circuits, the multi-valued resistive variable array includes multiplexing as described above in A row and B column Multi-valued resistive structure, the multiplexed multi-valued resistive structure of each row is connected to a pre-neuron circuit, the multiplexed multi-valued resistive structure of each column is connected to a post-neuron circuit, and the peripheral control circuit uses One of the multiplexed multi-valued resistive structures is selected for control, and the control and output of the multiplexed multi-valued resistive structure is completed by the corresponding pre-neuron circuit and post-neuron circuit, wherein, A and B are both integers greater than 1.

The beneficial effects of the present invention are: the present invention utilizes the simplified MOS selection unit to realize multi-valued analog output, thereby realizing multiplexing of circuit modules, reducing circuit modules such as sensitive amplifiers and digital-to-analog converters, and saving circuit area ; In addition, due to the multiplexing structure, the multiplexing MOS tube is used as the multiplexing part, and the area and power consumption overhead will be allocated to each resistive memory subunit, so the required average power consumption will also be obtained Significantly lower.

Description of drawings

Figure 1 is a schematic diagram of a multi-valued resistive variable unit based on a RRAM single-valued storage unit in the prior art.

Figure 2 is a schematic diagram of a multiplexed multi-valued resistive switching structure of the present invention.

Figure 3 is a schematic diagram of the peripheral architecture of a multiplexed multi-valued resistive switching structure according to the present invention.

Accompanying drawing 4 is the schematic diagram of a kind of neural network of the present invention.

In the figure: 1 storage unit, 2 peripheral circuit, 3 front neuron circuit, 4 post neuron circuit, 5 standard process circuit layer, 6 resistive variable memory subunit, 7 multiplexing multi-value resistive variable structure, 8 peripheral control circuit.

Detailed ways

In order to make the purpose, technical solution and advantages of the present invention clearer, the specific implementation manners of the present invention will be further described in detail below in conjunction with the accompanying drawings.

As shown in FIG. 2 , a multiplexing multi-valued resistive switch structure provided by the present invention includes a resistive switch memory unit and a MOS selection unit. The resistive memory unit includes M resistive memory subunits, and each resistive memory subunit is composed of a common 1T1R structure, that is, includes a resistive memory and a control MOS tube, wherein one end of the resistive memory is connected to the resistive memory The control signal corresponding to the subunit, the other end is connected to the drain of the control MOS transistor, the gate of the control MOS transistor is connected to the selection signal corresponding to the resistive variable memory subunit, and the sources of the M control MOS transistors are connected to the N multiplexed MOS transistors. The drains of the tubes are commonly connected to the same node. Wherein, the control MOS transistor is used as the control transistor of the resistive variable memory subunit, and the level level externally applied to the gate of the control MOS transistor is used as a judgment condition for whether to select the resistive variable memory subunit. The source and drain of the above-mentioned control MOS transistors can be interchanged, and M is an integer greater than 1.

The MOS selection unit includes N multiplexing MOS transistors connected in parallel; the sources of the N multiplexing MOS transistors are commonly connected to the output port, and the gate of each multiplexing MOS transistor is connected to a corresponding conduction signal. The level applied externally to the gate of the multiplexing MOS transistor is used as the judgment condition for whether to select the multiplexing MOS transistor. The source and drain of the above multiplexing MOS transistor can be interchanged, and N is an integer greater than 1.

Please continue to refer to Figure 2. The RRAM itself has two resistance values in a low-resistance state and a high-resistance state, which are R _on and R _off respectively. When the control MOS transistor is turned on, there is also a resistance R _T , which is far from It is smaller than the two resistance values of the RRAM in the low-resistance state and the high-resistance state. By externally adding the level of the control signal corresponding to the resistive memory subunit as the judgment condition of whether to select the resistive memory subunit, the conductance value of the multiplexed MOS transistor can be adjusted by adjusting its width-to-length ratio, in order to make In the present invention, the variable resistance values of the multiplexed multi-value resistive structure are as many as possible, and when N multiplexed MOS transistors are turned on, the corresponding conductance values are different. Specifically, it can be set that when the N multiplexed MOS transistors are turned on, the corresponding conductance values are distributed in an exponential ladder shape of 2. By controlling the above-mentioned turn-on signal, the number of multiplexed MOS transistors in the circuit is selected. The change of the pass signal can make 0-N multiplexing MOS transistors connected in the multi-value resistance switching structure of the present invention, so that the MOS selection unit can generate 2 ^N -1 different conductance values; and 2 ^N -1 different conductance values The conductance value of RRAM can be used as an effective supplement for RRAM's own resistance change. When only one RRAM subunit is in the read-write state, since its corresponding RRAM has two states of low resistance and high resistance, the structure of the present invention has a total of (2 ^N+1 -2) different resistance values can be generated, and at the same time, the change of RRAM resistance value can be regarded as the highest bit of resistance value change.

The control signal mentioned above in the present invention is used to control the resistive memory connected to it to be in a low-impedance state or a high-impedance state; the selection signal is used to control the selection of a certain resistive memory subunit among the M resistive memory subunits It is in a readable and writable state; the conduction signal is used to control whether the corresponding multiplexed MOS transistor needs to be conducted.

一共(2^N+1-2)个。因为R_on<R_off，通过设计使得

当只有一个阻变存储器子单元处于读写状态时，由于其对应的阻变存储器具有低阻和高阻两种状态，本发明的多路复用多值阻变结构一定可以得到共(2^N+1-2)种不同的电阻值。Preferably, the on-conductance values of the N multiplexed MOS transistors are set to G _T , 2G _T to 2 ^N-1 G _T , and by controlling the corresponding conduction signal applied to the multiplexed MOS transistors, the MOS selection unit can 2 ^N -1 different conductance values are produced, where G _T is greater than zero. After being connected in series with RRAM, the resistance that can be obtained is

A total of (2 ^N+1 -2) pieces. Since R _on < R _off , by design such that

When only one resistive variable memory subunit is in the read-write state, since its corresponding resistive variable memory has two states of low resistance and high resistance, the multiplexing multi-valued resistive variable structure of the present invention must be able to obtain a total of (2 ^{N +1} -2) different resistor values.

The present invention utilizes the simplified MOS selection unit to realize multi-valued analog output, thereby realizing multiplexing of circuit modules, reducing circuit modules such as sensitive amplifiers and digital-to-analog converters, and saving circuit area; in addition, due to the use of multiple Multiplexing structure, multiplexing MOS transistors as the multiplexing part, the area and power consumption overhead will be allocated to each resistive memory subunit, and the required average power consumption will also be significantly reduced.

Please refer to accompanying drawing 3, the multiplexing multi-valued resistive variable structure in the present invention also includes the peripheral circuit 2, wherein, the storage unit 1 is also included in the peripheral circuit 2, and the peripheral circuit 2 is used to ensure that when in use, each time only Select one of the resistive memory subunits to make it in a readable and writable state, and the rest of the resistive memory subunits are in an off state; the storage unit 1 is used to store the on and off of M multiplexed MOS transistors state. Specifically, a non-volatile storage unit can be used to record the switching state of the corresponding multiplexed MOS transistor, so as to ensure that the resistance value will not be lost after power-off.

Please refer to accompanying drawing 4, the neural network formed by the multiplexing multi-valued resistive structure of the present invention includes a multi-valued resistive array, A front neuron circuits 3, B rear neuron circuits 4 and peripheral control circuits 8 , the multi-valued resistive switch array includes a multiplexed multi-valued resistive switch structure 7 in row A and column B; in terms of process preparation, the resistive switchable memory subunit 6 is a single layer, vertically On the standard process circuit layer 5 in the direction, the corresponding multiplexing MOS transistors, control MOS transistors and other circuit structures that need to be built using MOS transistors are fabricated. The multiplexed multi-valued resistive structure 7 in each row is connected to a pre-neuron circuit 3, the multiplexed multi-valued resistive structure 7 in each column is connected to a post-neuron circuit 4, and the peripheral control circuit 8 is used to control the selection One of the multiplexed multi-valued resistive structures, and the control and output of the multiplexed multi-valued resistive structures are completed by the corresponding pre-neuron circuit and post-neuron circuit, and the multiplexed multi-valued The analog output of the resistive switching structure can be directly received and processed by the post-neurons. Compared with the typical RRAM memory array, the corresponding sensitive amplifier circuit structure is omitted.

The neural network can also integrate a non-volatile storage array of appropriate size to store resistance information that needs power-down memory. Because the multi-value resistive variable array theoretically has multiple parallel multiplexed multi-valued resistive structures, it is equivalent to using a set of peripheral circuits to realize the control of multiple multiplexed multi-valued resistive structures, so it is A neural network system that saves area and power.

The above are only preferred embodiments of the present invention, and the embodiments are not intended to limit the scope of patent protection of the present invention, so all equivalent structural changes made by using the description and drawings of the present invention should be included in the same reason Within the protection scope of the appended claims of the present invention.

Claims (9)

1. A multiplexing multivalue resistance change structure is characterized by comprising a resistance change memory unit and an MOS (metal oxide semiconductor) selection unit, wherein the resistance change memory unit comprises M resistance change memory sub-units, and the MOS selection unit comprises N multiplexing MOS tubes connected in parallel; wherein M and N are integers greater than 1;

the resistive random access memory comprises a resistive random access memory and control MOS tubes, wherein one end of the resistive random access memory is connected with a control signal corresponding to the resistive random access memory subunit, the other end of the resistive random access memory is connected with a drain electrode of the control MOS tube, a grid electrode of the control MOS tube is connected with a selection signal corresponding to the resistive random access memory subunit, and source electrodes of M control MOS tubes and drain electrodes of N multiplexing MOS tubes are connected to the same node;

the source electrodes of the N multiplexing MOS tubes are connected to the output port, and the grid electrode of each multiplexing MOS tube is connected with a corresponding conducting signal.

2. The multiplexing multivalue resistance change structure according to claim 1, wherein when the N multiplexing MOS transistors are turned on, the corresponding conductance values are different.

3. The multiplexing multivalue resistive switching structure according to claim 2, wherein when the N multiplexing MOS transistors are turned on, the corresponding conductance values are G respectively _T ，2G _T ，2 ² G _T To 2 ^N-1 G _T By controlling the on signal, the MOS selection unit can generate 2 ^N 1 different values of the conductance, wherein G _T Greater than zero.

4. The multiplexing multivalue resistive switching structure according to claim 3, wherein the conductance values in the N multiplexing MOS transistors satisfy:

wherein R is _on Represents a resistance value R of the resistive random access memory in a low resistance state _off And the resistance value of the resistive random access memory in a high resistance state is shown.

5. The multiplexing multi-value resistive switching structure according to claim 4, wherein the multiplexing multi-value resistive switching structure is capable of generating 2 by controlling the control signals so that only one of the M resistive switching memory sub-units is in a readable and writable state ^N+1 -2 resistance values.

6. The multiplexing multivalue resistance change structure according to claim 1, wherein the source and drain of the control MOS transistor and the multiplexing MOS transistor are interchangeable.

7. The multiplexing multivalue resistive switching structure according to claim 1, further comprising a peripheral circuit for controlling only one of the M resistive switching memory sub-units to be in a readable and writable state.

8. The multiplexing multivalue resistive switching structure according to claim 7, wherein the peripheral circuit further comprises a memory cell for storing on and off states of the N multiplexing MOS transistors.

9. A neural network formed by the multiplexing multivalued resistance change structure of claim 1, comprising a multivalued resistance change array, a front neuron circuit, B rear neuron circuits, and a peripheral control circuit, wherein the multivalued resistance change array comprises a row a and a column B of the multiplexing multivalued resistance change structure of claim 1, the multiplexing multivalued resistance change structure of each row is connected with one front neuron circuit, the multiplexing multivalued resistance change structure of each column is connected with one rear neuron circuit, the peripheral control circuit is used for controlling and selecting one multiplexing multivalued resistance change structure, and the control and output of the multiplexing multivalued resistance change structure are completed by the front neuron circuit and the rear neuron circuit corresponding to the multiplexing multivalued resistance change structure in a coordinated manner, wherein a and B are integers greater than 1.

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