CN110137348B - Multiplexing multivalue resistance change structure and neural network formed by same - Google Patents
Multiplexing multivalue resistance change structure and neural network formed by same Download PDFInfo
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- CN110137348B CN110137348B CN201910290334.XA CN201910290334A CN110137348B CN 110137348 B CN110137348 B CN 110137348B CN 201910290334 A CN201910290334 A CN 201910290334A CN 110137348 B CN110137348 B CN 110137348B
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- 238000013528 artificial neural network Methods 0.000 title claims description 14
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- 108010001267 Protein Subunits Proteins 0.000 claims abstract description 5
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 3
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 3
- 239000004065 semiconductor Substances 0.000 claims abstract description 3
- 210000002569 neuron Anatomy 0.000 claims description 21
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Abstract
The invention discloses a multiplexing multivalue resistance change structure, which comprises a resistance change memory unit and an MOS (metal oxide semiconductor) selection unit, wherein the resistance change memory unit comprises M resistance change memory sub-units, and the MOS selection unit comprises N multiplexing MOS tubes which are connected in parallel; the resistive random access memory subunit comprises a resistive random access memory and control MOS tubes, one end of the resistive random access memory is connected with control signals corresponding to the resistive random access memory subunit, the other end of the resistive random access memory is connected with drain electrodes of the control MOS tubes, grid electrodes of the control MOS tubes are connected with selection signals corresponding to the resistive random access memory subunit, and source electrodes of the M control MOS tubes and drain electrodes of the N multiplexing MOS tubes are connected to the same node; the source electrodes of the N multiplexing MOS tubes are connected to the output port, and the grid electrode of each multiplexing MOS tube is connected with the corresponding conducting signal. The invention realizes multi-value analog quantity output by using the simplified MOS selection unit, reduces circuit modules such as a sensitive amplifier, a digital-analog converter and the like, and saves circuit area.
Description
Technical Field
The invention relates to a resistive random access memory, in particular to a multiplexing multivalue resistive random access structure and a neural network formed by the same.
Background
In recent years, the development of new memories such as Resistive Random Access Memories (RRAMs) has become a new driving force in the memory field. The resistive random access memory has very wide application prospect in the future due to the characteristics of low power consumption, high speed and small area. Besides the traditional storage field, the method can also play an important role in the neural network system architecture in the artificial intelligence field. Research already exists in resistive random access memories, and cells are developed towards multi-value storage, namely, one cell completes multi-bit data storage through different resistance sizes.
The analog characteristic of the resistance change of the multi-value memory can output the current value of analog quantity change, so that the analog characteristic is an ideal device which can be used as a brain-like nerve synapse in a brain-like neural network system. At present, the multi-value memory has not been prepared as a mature result, so that a plurality of single-value RRAM cells can be adopted to simulate the multi-value characteristic at the present stage, as shown in fig. 1.
However, when such a structure is applied to a neural network, there are some disadvantages as follows. First, each single-valued RRAM cell needs to be provided with a Sense Amplifier (SA) for data readout, and second, a digital-to-analog converter (DAC) is required to convert single-valued digital signal data into an analog quantity having a multivalued characteristic. These additional circuit configurations increase the overhead in area and power consumption of the entire neural network system, which can be significant even if averaged over a single RRAM. Therefore, it is a realistic matter under the existing technical conditions to design a circuit which can directly convert the resistance characteristics of the RRAM into electrical quantities with multi-valued analog properties through some simple additional circuit structures, thereby saving area and power consumption.
Disclosure of Invention
The invention aims to provide a multiplexing multivalue resistance change structure and a neural network formed by the same, which utilize a simplified MOS selection unit to realize multivalue analog quantity output, further realize circuit module multiplexing, reduce circuit modules such as a sensitive amplifier and a digital-analog converter and save circuit area.
In order to achieve the purpose, the invention adopts the following technical scheme: a multiplexing multivalue resistance change structure comprises a resistance change memory unit and an MOS (metal oxide semiconductor) selection unit, wherein the resistance change memory unit comprises M resistance change memory sub-units, and the MOS selection unit comprises N multiplexing MOS tubes connected in parallel; wherein M and N are integers greater than 1;
the RRAM sub-unit comprises a RRAM and control MOS tubes, wherein one end of the RRAM is connected with control signals corresponding to the RRAM sub-unit, the other end of the RRAM is connected with drain electrodes of the control MOS tubes, grid electrodes of the control MOS tubes are connected with selection signals corresponding to the RRAM sub-unit, source electrodes of M control MOS tubes and drain electrodes of N multiplexing MOS tubes are connected to the same node, source electrodes of N multiplexing MOS tubes are connected to an output port, and grid electrodes of all multiplexing MOS tubes are connected with corresponding conduction signals.
Furthermore, when the N multiplexing MOS tubes are conducted, the corresponding conductance values are different.
Furthermore, when the N multiplexing MOS tubes are conducted, the corresponding conductance values are G respectively T ，2G T ，2 2 G T To 2 N-1 G T By controlling the on signal, the MOS selection unit can generate 2 N 1 different values of conductance, wherein G T Greater than zero.
Further, the conductance values in the N multiplexing MOS transistors satisfy:
wherein R is on Represents a resistance value R of the resistive random access memory in a low resistance state off And the resistance value of the resistive random access memory in a high resistance state is shown.
Furthermore, the multiplexing multivalue resistance changing structure can generate 2 by controlling the control signal to ensure that only one of the M resistance changing memory subunits is in a readable and writable state N+1 -2 resistance values.
Further, the source electrode and the drain electrode of the control MOS tube and the multiplexing MOS tube can be interchanged.
Furthermore, the multiplexing multivalue resistance change structure further comprises a peripheral circuit which is used for controlling only one of the M resistance change memory subunits to be in a readable and writable state.
Further, the peripheral circuit further comprises a storage unit for storing the on and off states of the N multiplexing MOS tubes.
A neural network comprises a multi-value resistance change array, A front neuron circuits, B rear neuron circuits and a peripheral control circuit, wherein the multi-value resistance change array comprises A rows and B columns of multiplexing multi-value resistance change structures as described above, each row of multiplexing multi-value resistance change structure is connected with one front neuron circuit, each column of multiplexing multi-value resistance change structures is connected with one rear neuron circuit, the peripheral control circuit is used for controlling and selecting one multiplexing multi-value resistance change structure, control and output of the multiplexing multi-value resistance change structure are completed by the front neuron circuit and the rear neuron circuit which correspond to the multiplexing multi-value resistance change structure in a coordinated mode, and A and B are integers larger than 1.
The beneficial effects of the invention are as follows: the invention utilizes the simplified MOS selection unit to realize multi-valued analog quantity output, thereby realizing circuit module multiplexing, reducing circuit modules such as a sensitive amplifier, a digital-analog converter and the like, and saving circuit area; in addition, due to the adoption of a multiplexing structure and the multiplexing of the MOS tube as a multiplexing part, the area and the power consumption overhead are distributed to each resistive random access memory subunit, and the average power consumption overhead required is also obviously reduced.
Drawings
Fig. 1 is a schematic diagram of a multi-value resistive switching unit formed based on a RRAM single-value memory cell in the prior art.
Fig. 2 is a schematic diagram of a multiplexing multivalue resistance change structure according to the present invention.
Fig. 3 is a schematic diagram of a peripheral architecture of a multiplexing multivalue resistance change structure according to the present invention.
FIG. 4 is a schematic diagram of a neural network of the present invention.
In the figure: the circuit comprises a memory unit 1, a peripheral circuit 2, a front neuron circuit 3, a rear neuron circuit 4, a standard process circuit layer 5, a resistive random access memory subunit 6, a multiplexing multi-valued resistive random access structure 7 and a peripheral control circuit 8.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention are described in detail below with reference to the accompanying drawings.
As shown in fig. 2, the multiplexing multivalue resistance change structure provided by the invention comprises a resistance change memory unit and a MOS selection unit. The resistive random access memory unit comprises M resistive random access memory subunits, each resistive random access memory subunit is composed of a recognized 1T1R structure and comprises a resistive random access memory and a control MOS tube, wherein one end of the resistive random access memory is connected with a control signal corresponding to the resistive random access memory subunit, the other end of the resistive random access memory is connected with a drain electrode of the control MOS tube, a grid electrode of the control MOS tube is connected with a selection signal corresponding to the resistive random access memory subunit, and source electrodes of the M control MOS tubes and drain electrodes of the N multiplexing MOS tubes are connected to the same node. The control MOS tube is used as a control tube of the resistive random access memory subunit, and the level which is externally added to the grid electrode of the control MOS tube is used as a judgment condition for judging whether to select the resistive random access memory subunit. The source electrode and the drain electrode of the control MOS tube can be interchanged, and M is an integer larger than 1.
The MOS selection unit comprises N multiplexing MOS tubes which are connected in parallel; the source electrodes of the N multiplexing MOS tubes are connected to the output port, and the grid electrode of each multiplexing MOS tube is connected with a corresponding conducting signal. The source electrode and the drain electrode of the multiplexing MOS tube can be interchanged by using the level which is externally added on the grid electrode of the multiplexing MOS tube as a judgment condition for selecting the multiplexing MOS tube, and N is an integer which is more than 1.
With reference to fig. 2, the resistive random access memory has two resistance values, R respectively, in a low resistance state and a high resistance state on And R off The control MOS tube also has a resistor R when being conducted T The resistance is far smaller than two resistances of the resistive random access memory in a low resistance state and a high resistance state. The level externally added on a control signal corresponding to the resistive random access memory subunit is used as a judgment condition for judging whether the resistive random access memory subunit is selected, the conductance value of the multiplexing MOS tube can be adjusted by adjusting the width-length ratio of the multiplexing MOS tube, and in order to enable the variable resistance value of the multiplexing multi-valued resistive random access structure to be as much as possible, N multiplexing MOS tubes are arranged on the conduction of the multiplexing MOS tubeWhen the current is on, the corresponding conductance values are different. Specifically, when N multiplexing MOS transistors are turned on, the corresponding conductance values may be distributed in an exponential ladder shape of 2, and by controlling the above-mentioned turn-on signal, that is, the number of multiplexing MOS transistors in the selection circuit, wherein by a change in the turn-on signal, 0 to N multiplexing MOS transistors may be connected in the multi-value resistance change structure of the present invention, so that the MOS selection unit may generate 2 multiplexing MOS transistors N -1 different conductance values; and 2 is N The-1 different conductance values can be used as an effective supplement for RRAM self resistance change, when only one resistive random access memory subunit is in a read-write state, the structure of the invention can be generated (2) because the corresponding resistive random access memory has two states of low resistance and high resistance N+1 -2) different resistance values, and the RRAM resistance value change can be considered as the highest order of resistance value change.
The control signal mentioned above is used for controlling the resistance change memory connected with the resistance change memory to be in a low resistance state or a high resistance state; the selection signal is used for controlling one resistive random access memory subunit from the M resistive random access memory subunits to be in a readable and writable state; the conduction signal is used for controlling whether the corresponding multiplexing MOS tube needs to be conducted or not.
Preferably, the conduction conductance values of the N multiplexing MOS tubes are set as G T ，2G T To 2 N-1 G T The MOS selection unit can generate 2 by controlling the corresponding conducting signal applied to the multiplexing MOS tube N 1 different values of conductance, wherein G T Greater than zero. After being connected in series with the RRAM, the obtained resistance value is
In all (2) N+1 -2) of the cells. Because R on <R off By design such that
When only one resistive random access memory subunit is in a read-write state, the resistive random access memory subunit is in a corresponding resistive random access memoryThe memory has two states of low resistance and high resistance, and the multiplexing multivalue resistance change structure can obtain 2 N+1 -2) different resistance values.
The invention utilizes the simplified MOS selection unit to realize multi-valued analog quantity output, thereby realizing circuit module multiplexing, reducing circuit modules such as a sensitive amplifier, a digital-analog converter and the like, and saving circuit area; in addition, due to the adoption of a multiplexing structure, the multiplexing MOS tube is used as a multiplexing part, the area and the power consumption expense are distributed to each resistive random access memory subunit, and the required average power consumption expense is also obviously reduced.
Referring to fig. 3, the multiplexing multivalue resistive switching structure further includes a peripheral circuit 2, where the peripheral circuit 2 further includes a memory unit 1, and the peripheral circuit 2 is used to ensure that only one resistive switching memory subunit can be selected each time to be in a readable and writable state, and the remaining resistive switching memory subunits are in an off state; the memory unit 1 is used for storing the on and off states of M multiplexing MOS tubes. The on-off state of the corresponding multiplexing MOS tube can be recorded by adopting the non-volatile memory unit, so that the resistance value is not lost after power is off.
Referring to fig. 4, the neural network formed by the multiplexing multivalued resistance change structure of the present invention includes a multivalued resistance change array, a front neuron circuit 3, B rear neuron circuits 4, and a peripheral control circuit 8, where the multivalued resistance change array includes a row a and a column B multiplexing multivalued resistance change structure 7; in the process preparation of the multiplexing multivalue resistance change structure, a resistance change memory subunit 6 is a layer, and corresponding multiplexing MOS tubes, control MOS tubes and other circuit structures which need to be built by using the MOS tubes are manufactured on a standard process circuit layer 5 in the vertical direction. The multiplexing multivalue resistance change structure 7 of each row is connected with a front neuron circuit 3, the multiplexing multivalue resistance change structure 7 of each column is connected with a rear neuron circuit 4, the peripheral control circuit 8 is used for controlling and selecting one multiplexing multivalue resistance change structure, the control and output of the multiplexing multivalue resistance change structure are completed by the front neuron circuit and the rear neuron circuit which correspond to the multiplexing multivalue resistance change structure in a coordinated mode, the analog output of the multiplexing multivalue resistance change structure can be directly received and processed by the rear neuron, and compared with a typical RRAM memory array, a corresponding sensitive amplifier circuit structure is omitted.
The neural network can also integrate a nonvolatile memory array with proper scale for storing resistance value information needing power-down memory. Because the multi-value resistance change array theoretically has a plurality of multiplexing multi-value resistance change structures connected in parallel, a set of peripheral circuits are equivalently used for realizing the control of the multiplexing multi-value resistance change structures, and therefore the neural network system saves area and power consumption.
The above description is only a preferred embodiment of the present invention, and the embodiment is not intended to limit the scope of the present invention, so that all equivalent structural changes made by using the contents of the specification and the drawings of the present invention should be included in the scope of the appended claims.
Claims (9)
1. A multiplexing multivalue resistance change structure is characterized by comprising a resistance change memory unit and an MOS (metal oxide semiconductor) selection unit, wherein the resistance change memory unit comprises M resistance change memory sub-units, and the MOS selection unit comprises N multiplexing MOS tubes connected in parallel; wherein M and N are integers greater than 1;
the resistive random access memory comprises a resistive random access memory and control MOS tubes, wherein one end of the resistive random access memory is connected with a control signal corresponding to the resistive random access memory subunit, the other end of the resistive random access memory is connected with a drain electrode of the control MOS tube, a grid electrode of the control MOS tube is connected with a selection signal corresponding to the resistive random access memory subunit, and source electrodes of M control MOS tubes and drain electrodes of N multiplexing MOS tubes are connected to the same node;
the source electrodes of the N multiplexing MOS tubes are connected to the output port, and the grid electrode of each multiplexing MOS tube is connected with a corresponding conducting signal.
2. The multiplexing multivalue resistance change structure according to claim 1, wherein when the N multiplexing MOS transistors are turned on, the corresponding conductance values are different.
3. The multiplexing multivalue resistive switching structure according to claim 2, wherein when the N multiplexing MOS transistors are turned on, the corresponding conductance values are G respectively T ，2G T ，2 2 G T To 2 N-1 G T By controlling the on signal, the MOS selection unit can generate 2 N 1 different values of the conductance, wherein G T Greater than zero.
4. The multiplexing multivalue resistive switching structure according to claim 3, wherein the conductance values in the N multiplexing MOS transistors satisfy:
wherein R is on Represents a resistance value R of the resistive random access memory in a low resistance state off And the resistance value of the resistive random access memory in a high resistance state is shown.
5. The multiplexing multi-value resistive switching structure according to claim 4, wherein the multiplexing multi-value resistive switching structure is capable of generating 2 by controlling the control signals so that only one of the M resistive switching memory sub-units is in a readable and writable state N+1 -2 resistance values.
6. The multiplexing multivalue resistance change structure according to claim 1, wherein the source and drain of the control MOS transistor and the multiplexing MOS transistor are interchangeable.
7. The multiplexing multivalue resistive switching structure according to claim 1, further comprising a peripheral circuit for controlling only one of the M resistive switching memory sub-units to be in a readable and writable state.
8. The multiplexing multivalue resistive switching structure according to claim 7, wherein the peripheral circuit further comprises a memory cell for storing on and off states of the N multiplexing MOS transistors.
9. A neural network formed by the multiplexing multivalued resistance change structure of claim 1, comprising a multivalued resistance change array, a front neuron circuit, B rear neuron circuits, and a peripheral control circuit, wherein the multivalued resistance change array comprises a row a and a column B of the multiplexing multivalued resistance change structure of claim 1, the multiplexing multivalued resistance change structure of each row is connected with one front neuron circuit, the multiplexing multivalued resistance change structure of each column is connected with one rear neuron circuit, the peripheral control circuit is used for controlling and selecting one multiplexing multivalued resistance change structure, and the control and output of the multiplexing multivalued resistance change structure are completed by the front neuron circuit and the rear neuron circuit corresponding to the multiplexing multivalued resistance change structure in a coordinated manner, wherein a and B are integers greater than 1.
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| JP4728726B2 (en) * | 2005-07-25 | 2011-07-20 | 株式会社東芝 | Semiconductor memory device |
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| US4378595A (en) * | 1980-03-25 | 1983-03-29 | The Regents Of The University Of California | Synchronous multivalued latch |
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