CN104425412A - 具有可插拔式引线的模制的半导体封装 - Google Patents

具有可插拔式引线的模制的半导体封装 Download PDF

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Publication number
CN104425412A
CN104425412A CN201410438376.0A CN201410438376A CN104425412A CN 104425412 A CN104425412 A CN 104425412A CN 201410438376 A CN201410438376 A CN 201410438376A CN 104425412 A CN104425412 A CN 104425412A
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Prior art keywords
electric conductor
plug type
wire
terminal
type lead
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CN201410438376.0A
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CN104425412B (zh
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陈天山
龙登超
许德祥
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

本发明公开了一种具有可插拔式引线的模制的半导体封装，该半导体封装包括具有多个端子的半导体晶片、封装该半导体晶片的模制化合物，以及为了插入外部插座形成所需尺寸的可插拔式引线。该可插拔式引线从模制化合物中突出，并且提供用于半导体晶片的不止一个端子的单独的电气通路。可插拔式引线的单独的电气通路可由导电体提供，该导电体被电绝缘体比如模制化合物或者其他绝缘材料/绝缘媒介彼此隔离。

Description

具有可插拔式引线的模制的半导体封装
技术领域
本申请涉及半导体封装，特别是用于模制的半导体封装的引线配置。
背景技术
功率半导体晶体管封装通常包括用模制化合物(moldingcompound)封装的功率晶体管裸片(power transistor die)，以及从模制化合物中突出的三个引线。每个引线电连接至晶体管裸片的不同端子(例如，源极、栅极和漏极)，并且共同地提供用于晶体管裸片的必要的外部电连接。装配功率半导体晶体管封装以包括用于模制的功率晶体管裸片的每个端子的物理上单独的引线，增加了封装的大小和成本。另外，常规的功率半导体晶体管封装的引线通常焊接(soldered)至另一个部件比如电路板。许多硬化的应用(hardenedapplication)要求无焊料连接(solder-less connection)，限制了对允许引线焊接的应用使用常规的功率半导体晶体管封装。
发明内容
根据半导体封装的实施例，半导体封装包括具有多个端子的半导体裸片、封装该半导体裸片的模制化合物以及为了插入外部插座(receptacle)而具有所需尺寸的可插拔式引线。该可插拔式引线从模制化合物中突出，并为半导体裸片的不止一个端子提供单独的电气通路。
当阅读下面的具体实施方式和查看附图，本领域的技术人员将会认出附加的特征和优点。
附图说明
附图中元件不一定是相对彼此按比例的。相似的附图标记指对应的相似的部分。各种举例说明的实施例的特征可以结合，除非他们彼此排斥。实施例在附图进行了描述，并在下面的具体实施方式中进行了详细说明。
图1A示出了具有可插拔式引线的模制的半导体封装的一个实施例的平面图；
图1B示出了一种具有所需的尺寸以接收图1A中所示的可插拔式引线的插座的截面图；
图2示出了具有可插拔式引线的模制的半导体封装的另一个实施例的剖视图；
图3示出了具有可插拔式引线的模制的半导体封装的另一个实施例的剖视图；
图4示出了具有可插拔式引线的模制的半导体封装的又一个实施例的剖视图；
图5A示出了具有可插拔式引线的模制的半导体封装的一个实施例的平面图；
图5B示出了一种具有所需的尺寸以接收图5A中所示的可插拔式引线的插座的截面图；
图6A到图6C示出了具有可插拔式引线的模制的半导体封装的另一个实施例的不同视图；
图7示出了用于模制的半导体封装的可插拔式引线的一个实施例的剖视图；
图8示出了用于模制的半导体封装的可插拔式引线的另一个实施例的剖视图；
图9示出了用于模制的半导体封装的可插拔式引线的另一个实施例的剖视图；
图10示出了用于具有不止一个半导体裸片的模制的半导体封装的可插拔式引线的一个实施例的剖视图；
图11A到图11C示出了一种依照一个实施例制造具有可插拔式引线的模制的半导体封装的方法的不同阶段；
图12A到图12C示出了一种依照另一个实施例制造具有可插拔式引线的模制的半导体封装的方法的不同阶段；
图13A到图13C示出了一种依照另一个实施例制造具有可插拔式引线的模制的半导体封装的方法的不同阶段；
图14示出了包括在根据图13A到图13C的方法制造的模制的半导体封装中的可插拔式引线的剖视图。
具体实施方式
本文中描述的实施例提供了具有可插拔式引线的模制的半导体封装。该可插拔式引线为了插入外部的插座(例如在电路板上)而具有所需的尺寸。虽然该引线是可插拔的，若需要该引线可以焊接，但并不需要用焊接来形成与引线的可靠连接。可插拔式引线为包括在模制的封装中的半导体裸片的不止一个端子提供单独的电气通路。例如，就晶体管裸片而言，可插拔式引线可为该晶体管裸片的漏极端子、源极端子和栅极端子提供电气通路。就二极管裸片而言，可插拔式引线可为二极管裸片的阳极端子和阴极端子提供电气通路。通常，引线可具有任何所期望的横截面形状，并且引线和模制的半导体裸片的端子之间的电连接能以本文下面将更详细描述的不同方式来实现。
图1包括图1A和图1B，示出了包括为了插入外部的插座104中具有所需的尺寸的可插拔式引线102的模制的半导体封装100的实施例。图1A示出了可插拔式引线102的平面图，和图1B示出了插座104的剖视图。插座104在封装100之外，并且能附接至任何所期望的部件比如电路板、衬底、卡片等。插座104具有与可插拔式引线102互补所需的尺寸，以安全地接收引线102。
除可插拔式引线102之外，封装100还包括具有多个端子(图1A中未示出)的半导体裸片106和封装半导体裸片106的模制化合物108。由于模制化合物108包围了裸片106，因此在图1A中半导体裸片106以虚线框说明。可插拔式引线102从模制化合物108中突出，并为半导体裸片106的不止一个端子提供单独的电气通路。在一个实施例中，可插拔式引线102是电连接至半导体裸片106的唯一引线，并为裸片106的每个端子提供单独的电气通路。例如，就晶体管裸片106而言，可插拔式引线102可为晶体管裸片106的漏极端子、源极端子和栅极端子提供单独的电气通路。就二极管裸片106而言，可插拔式引线102可为晶体管裸片106的阳极端子和阴极端子提供单独的电气通路。
在一些情况下，埋置于模制化合物108中的半导体裸片106是垂直晶体管裸片，在垂直晶体管裸片中电流流经裸片106的前侧和后侧之间的半导体材料。例如，晶体管的源极端子和栅极端子可被布置在裸片106的一侧，而且漏极端子被布置在裸片106的后侧。本文使用的术语“源极端子”指的是FET(场效应晶体管)(比如，MOSFET(金属氧化物半导体FET)或者GaN HEMT(高电子迁移率晶体管))的源极端子，或者双极型晶体管(比如IGBT(绝缘栅双极型晶体管))的发射极端子。同样地，本文中使用的术语“漏极端子”指的是FET的漏极端子或者双极型晶体管的集电极端子。例如就反向平行连接至单独的二极管裸片的半桥电路或者GaN HEMT裸片而言，在模制的封装100中可包括不止一个半导体裸片106。
在不同情况下，可插拔式引线102的电气通路由导电体110、112、114形成，该导电体被电绝缘体116彼此隔离。图1中所示的可插拔式引线102包括从模制化合物108中突出并电连接至半导体裸片106的第一端子的第一导电体110、从模制化合物108中突出并电连接至半导体裸片106的第二端子的第二导电体112，以及将第一导电体和第二导电体110、112彼此隔离的电绝缘体116。图1中示出的半导体裸片106是晶体管裸片，则可插拔式引线102进一步包括从模制化合物108中突出并电连接至半导体裸片106的第三端子的第三导电体114。
可插拔式引线102的导电体110、112、114被制成为所需的尺寸，以当引线102插入到插座104时接触外部插座104的对应的导电区域118、120、122。可插拔式引线102的导电体110、112、114和外部插座104的对应的导电区域118、120、122之间的接触点可以是焊接的或者无料焊接的(例如，压合连接或者所谓的防错连接(poka-yoke connection))。在一个实施例中，将可插拔式引线102的导电体110、112、114彼此隔离的电绝缘体116是模制化合物。可以使用相同或者不同的类型的模制化合物来可隔离插拔式引线102的导电体110、112、114，如同作封装半导体裸片106的模制化合物108。
进一步根据图1所示的实施例，可插拔式引线102的第二导电体112被部分地布置在引线102的第一导电体110中，并与引线102的第一导电体110隔离。类似地，可插拔式引线102的第三导电体114被部分地布置在引线102的第二导电体112中，并与引线102的第二导电体112隔离。而且，第二导电体112比第一导电体110从模制化合物108中向外突出更长，并且第三导电体114比第二导电体112从模制化合物108中向外突出更长。
可插拔式引线102的导电体110、112、114的每一个具有保留未被模制化合物108覆盖的远端110’、112’、114’。第一导电体110的远端110’的宽度(w1)大于第二导电体112的远端112’的宽度(w2)，以使第二导电体112可如图1A中较大间隔的虚线所示，安装在第一导电体110内部。第二导电体112的远端112’的宽度(w2)大于第三导电体114的远端114’的宽度(w3)，从而第三导电体114可如图1A中较近间隔的虚线所示，安装在第二导电体112内部。外部插座104具有与可插拔式引线102的形状互补的形状，以使可插拔式引线102的不同宽度部分安全地接收于插座104的对应大小的开放区域124、126、128中。
图2示出了根据一个实施例的图1的模制的封装100的剖视图。在该实施例中，可插拔式引线102的每个导电体110、112、114具有在模制化合物108外面的成曲形的、有棱的(edged)或者成某种形状的远端110’、112’、114’，以及在模制化合物108里面的平坦近端110”、112”、114”。导电体110、112、114能通过冲压或其任何其他适当的工艺成形，以在模制化合物108的里面和外面出产所期望的形状。第一导电体110的平坦近端110”与第二导电体和第三导电体112、114的平坦近端112”、114”隔开，并且与半导体裸片106隔开。另外根据该实施例，第二导电体112的平坦近端112”和第三导电体114的平坦近端114”在模制化合物108里面的相同点处终止(terminate)，在模制化合物108中与第三导电体114被布置在第二导电体112之上。第二导电体112的平坦近端112”在晶体管裸片106顶部处的端子(例如源极端子)之上延伸，并通过焊膏或者其他导电附接材料130附接至该端子。第三导电体114通过一根或者多根键合线132电连接至在晶体管106顶部的晶体管裸片106的不同端子(例如栅极端子)。对垂直器件而言，半导体裸片106裸片被布置于在该裸片106的底部处的第一导电体110的平坦近端110”上。布置在晶体管裸片106的底部处的晶体管裸片106的端子(例如漏极端子)，通过焊膏或者其他导电附接材料134附接至第一导电体110的平坦近端110”。根据该实施例，第一导电体110的平坦近端110”起裸片焊盘(die paddle)的作用，并且消除了对单独的裸片焊盘的需求。
图3示出了根据另一个实施例图1的模制的封装100的剖视图。图3所示的实施例类似于图2中的实施例，但是，可插拔式引线102的第三导电体114的平坦近端114”比该引线102的第二导电体112的平坦近端112”向模制化合物108内延伸得更长。
图4示出了根据另一个实施例图1的模制的封装100的剖视图。图4所示的实施例类似于图3中的实施例，但是，第三导电体114通过代替键合线132的金属片136电连接至在半导体裸片106的顶部处的对应端子。金属片136的顶部，也即面向远离裸片106的侧面在一些情况下可以暴露。也就是说，金属片136的顶部不一定要被模制化合物108覆盖。
图5包括图5A和图5B，示出了模制的半导体封装100的另一个实施例，该模制的半导体封装100包括为了插入外部插座104而具有所需尺寸的可插拔式引线102。图5A示出了引线102的平面图，和图5B示出了插座104的剖视图。图5中所示的可插拔式引线102和插座104分别地类似于图1中所示的引线102和插座104，但是可插拔式引线102的每个导电体110、112、114的远端110’、112’、114’具有相同的宽度(w1)。插座104被制成具有与可插拔式引线102互补所需的尺寸，以使可插拔式引线102的宽度统一的部分安全地接收于插座104的大小统一的开放区域138中。
图6包括图6A到图6C，示出了模制的半导体封装100的另一个实施例，该模制的半导体封装100包括为了插入外部插座104具有所需尺寸的可插拔式引线102。图6A示出了封装100沿着平行于封装100的顶部的平面的截面图，从而对引线导体110、112、114和半导体裸片106的查看不被模制化合物108所阻挡。图6B示出了根据第一个实施例的可插拔式引线102的剖视图，而图6C示出了根据第二实施例的可插拔式引线102的剖视图。可插拔式引线102具有如图6A中所示的沿着引线102的长度的细长的管状形状，或者如图6B和图6C中所示的呈圆形似(round)的或者圆形(circular)的横截面形状。
可插拔式引线102的每个导电体110、112、114具有如图6B和图6C所示的从模制化合物108中突出的曲形的远端110’、112’、114’，以及如图6A所示的布置在模制化合物108里面的平坦的近端110”、112”、114”。导电体110、112、114可如本文先前解释的方式，通过冲压或者其他任何适当的工艺成形。
对垂直器件而言，半导体裸片106裸片被布置在裸片106的底部处的第一导电体110的平坦近端110”上。布置在裸片106的底部处的晶体管裸片106的端子(例如漏极端子)，通过焊膏或者其他导电附接材料(在图6中未示出)附接至第一导电体110的平坦近端110”。根据该实施例，第一导电体110的平坦近端110”起裸片焊盘的作用，并且如本文先前描述的不再需要单独的裸片焊盘。在模制化合物108里面，第二导电体和第三导电体112、114被布置在半导体裸片106之上。根据该实施例，第二导电体和第三导电体112、114裸片通过焊膏或者其他导电附接材料(在图6中未示出)分别附接至在半导体裸片106的顶部的端子。这就不需要键合线或者金属片来完成可插拔式引线102的导电体110、112、114和半导体裸片106的各自的端子之间的电连接。反而，导电体110、112、114附接至半导体裸片106的对应的端子。
根据图6B的实施例，可插拔式引线102的第一导电体110的远端110’具有曲形的横截面形状，并且被布置在引线102的底部处。第二导电体112的远端112’类似地具有曲形的横截面形状，并且被布置在引线102的顶部处。第一导电体和第二导电体110、112可以是相同或者不同的大小，并且形成围墙(enclosure)，可插拔式引线102的第三导电体114被布置在该围墙中。第三导电体114的远端114’具有圆形或者椭圆形的横截面形状。导电体110、112、114通过电绝缘体116(比如模制化合物或者其他绝缘材料/绝缘媒介)彼此隔离。第二导电体112可具有突出部(tab)或者突起140，以确保引线102在插入外部插座104期间的适当方位。
根据图6C的实施例，可插拔式引线102的第二导电体112的远端112’具有曲形的横截面形状，并且被布置在引线102的底部处。第三导电体114的远端114’具有曲形的横截面形状，并且被布置在引线102的顶部。第二导电体112比第三导电体114具有更大的面积。第一导电体110具有圆形或者椭圆形的横截面形状，并被布置在由第二导电体和第三导电体112、114形成的围墙中。导电体110、112、114通过电绝缘体116(比如模制化合物或者其他绝缘材料/绝缘媒介)彼此隔离。
图7示出了可插拔式引线102的另一个实施例的剖视图。根据该实施例，可插拔式引线102具有八边形的横截面形状。可插拔式引线102的第二导电体112具有在相对彼此成钝角处具有三个平坦侧面的外表面，并且被布置在引线102的底部处。第三导电体114类似地具有在相对彼此成钝角处具有三个平坦侧面的外表面，并且被布置在引线102的顶部处。第一导电体110具有圆形或者椭圆形的横截面形状，并被布置在由第二导电体和第三导电体112、114形成的围墙中。导电体110、112、114通过电绝缘体116(比如模制化合物或者其他绝缘材料/绝缘媒介)彼此隔离。
图8示出了可插拔式引线102的另一个实施例的剖视图。根据该实施例，可插拔式引线102具有三角形的横截面形状。可插拔式引线的第二导电体和第三导电体112、114均具有平坦的外表面，并且第一导电体110具有圆形或者椭圆形的横截面形状且被布置在第二导电体和第三导电体112、114之间。导电体110、112、114通过电绝缘体116(比如模制化合物或者其他绝缘材料/绝缘媒介)彼此隔离。
图9示出了可插拔式引线102的又一个实施例的剖视图。根据该实施例，可插拔式引线102具有正方形或者矩形的横截面形状，并且包括用于电连接至晶体管裸片106的第二端子的两个第二导电体112a、112b和用于电连接至晶体管裸片106的第三端子的两个第三导电体114a、114b。该两个第二导电体112a、112b和两个第三导电体114a、114b形成正方形或者矩形的围墙，第一导电体110被布置在该围墙中。第一导电体110电连接至晶体管裸片106的第一端子。导电体110、112a、112b、114a、114通过电绝缘体116(比如模制化合物或者其他绝缘材料/绝缘媒介)彼此隔离。
图10示出了可插拔式引线102的剖视图，该引线102配置为用于连接至包括在模制的封装中的不止一个的半导体裸片。例如对包括高压侧晶体管裸片和低压侧晶体管裸片的半桥电路而言，可插拔式引线102可包括用于电连接至高压侧晶体管裸片的源极端子的第一导电体112a、用于电连接至低压侧晶体管裸片的源极端子的第二导电体112b、用于电连接至高压侧晶体管裸片的栅极端子的第三导电体114a，以及用于电连接至低压侧晶体管裸片的栅极端子的第四导电体114b。第一导电体到第四导电体112a-114b形成正方形或者矩形的围墙，第五导电体和第六导电体110a、110b被布置在该围墙中。第五导电体110a电连接至高压侧晶体管裸片的漏极端子，和第六导电体110b电连接至低压侧晶体管裸片的漏极端子。如果高压侧晶体管裸片的源极端子和低压侧晶体管裸片的漏极端子在模制的封装内连接以形成半桥电路的输出端，则可以省略第一导电体112a(电连接至高压侧晶体管裸片的源极端子)或者第六导电体110b(电连接至低压侧晶体管裸片的漏极端子)。导电体110a、110b、112a、112b、114a、114通过电绝缘体116(比如模制化合物或者其他绝缘材料/绝缘媒介)彼此隔离。
图11A到图11C示出了制造具有可插拔式引线102的模制的半导体封装100的一个实施例。在图11A中，可插拔式引线102具有三个单独的导电体110、112、114，该三个导电体通过电绝缘体(未示出)比如模制化合物或者其他绝缘材料/绝缘媒介彼此隔离。两个外部的导电体112、114形成圆形或者椭圆形的围墙，内部的导电体110被布置在该围墙中。导电体110、112、114冲压成为或者以其他方法成形为具有待模制的平坦近端110”、112”、114”和保留不被模制的成曲形的远端110’、112’、114’。照此，可插拔式引线102的每个导电体110、112、114的外部表面在模制化合物108外面的区域中与在被模制化合物108封装的区域中面向不同的方向。
如图11B所示，垂直晶体管裸片106通过焊膏或者其他裸片附接材料(在视图之外)附接至内部的导电体110的平坦近端110”。该连接提供可插拔式引线102的内部的导电体110和布置在晶体管芯片106底部处的端子(在视图之外)之间的电接触点。电连接件200形成在可插拔式引线102的外部的导电体112、114和布置在晶体管芯片106顶部处的对应端子202、204之间。电连接件200在图11B中示为线，并且可以是键合线、带状键合(ribbon bond)或者金属片。然后，晶体管裸片106、引线导体110、112、114的近端110”、112”、114”，以及在裸片端子202、204和引线导体110、112、114之间的电连接件200如图11C所示的被模制化合物108封装。
图12A到图12C示出了制造具有可插拔式引线102的模制的半导体封装100的另一个实施例。在图12A到图12C所示实施例类似于在图11A到图11C所示的实施例，但是成形为接收晶体管芯片106的可插拔式引线102的导电体110是引线102的外部导体110、112其中一个，而不是内部导体114，。
图13A到图13C示出了制造具有可插拔式引线102的模制的半导体封装100的另一个实施例。在图13A到图13C所示实施例类似于在图11A到图11C所示的实施例，但是可插拔式引线102的形状对应于图1A中所示的实施例。可插拔式引线102的最外面的、最宽的导电体110例如通过冲压成形，以接收晶体管裸片106。
图14示出了图13A到图13C所示的可插拔式引线102的放大的侧面透视图。可插拔式引线102的最外面的、最宽的导电体110的近端110”(即将被模制化合物108封装的末端)可以成形以使次宽的导电体112的近端112”的一部分未被最外面的、最宽的导电体110覆盖。类似地，中间的导电体112的近端112”可以成形为，以使最里面的、最窄的导电体114的近端114”的一部分未被中间的导电体112覆盖。这种导体引线110、112、114的结构允许在可插拔式引线102的中间导电体和最里面的导电体112、114与对应的裸片端子202、204之间建立必要的电连接。
空间相关术语比如“下(under、below、lower)、“上(over、upper)”等等，用于简化描述，以解释一个元件相对于第二元件的定位。这些术语旨在涵盖除了图中描述的不同方位之外的器件的不同方位。此外，术语比如“第一(first)”、“第二(second)”等等，也用于描述各自元件、区域、部分等，并且也并非意在限制。贯穿整个描述同样的术语指同样的元件。
如本文所用的，术语“具有(having)”、“包括(containing、including、comprising)等是开放性术语，表明所述元件或者特征的存在，但并不排除其他的元件或者特征。冠词”一(a、an)“和”该(the)“旨在包括复数以及单数，除非上下文中另有明确表明。
考虑到上述范围的变化和应用，应该可以理解的是本发明不受前述描述限制，也不由附图限制。反而，本发明仅由下面的权利要求和他们的法律等同物限制。

Claims (20)

1.一种半导体封装，包括
半导体裸片，具有多个端子；
模制化合物，封装所述半导体裸片；和
可插拔式引线，为了插入外部插座而具有所需尺寸，所述可插拔式引线从所述模制化合物中突出并且为所述半导体裸片的不止一个端子提供单独的电气通路。
2.如权利要求1所述的半导体封装，
其中所述可插拔式引线是电连接至所述半导体裸片的唯一引线，并且为所述半导体裸片的每个端子提供单独的电气通路。
3.如权利要求1所述的半导体封装，进一步包括
另一半导体裸片，被所述模制化合物封装且电连接至所述半导体裸片。
4.如权利要求3所述的半导体封装，
其中所述可插拔式引线是电连接至两个半导体裸片的唯一引线，并且为每个半导体裸片的每个端子提供单独的电气通路。
5.如权利要求1所述的半导体封装，
其中所述可插拔式引线包括从所述模制化合物中突出并电连接至所述裸片端子中的第一个端子的第一导电体、从所述模制化合物中突出并电连接至所述裸片端子中的第二个端子的第二导电体以及将所述第一导电体和所述第二导电体彼此隔离的电绝缘体，所述第一导电体和所述第二导电体具有所需尺寸以当将所述可插拔式引线插入所述插座时接触所述外部插座的不同区域。
6.如权利要求5所述的半导体封装，
其中所述电绝缘体是模制化合物。
7.如权利要求5所述的半导体封装，
其中所述可插拔式引线的所述第一导电体通过一个或者多个键合线电连接至所述第一裸片端子，并且所述可插拔式引线的所述第二导电体通过一个或者多个另外的键合线电连接至所述第二裸片端子。
8.如权利要求5所述的半导体封装，
其中所述可插拔式引线的所述第一导电体通过第一金属片电连接至所述第一裸片端子，而且所述可插拔式引线的所述第二导电体通过第二金属片电连接至所述第二裸片端子。
9.如权利要求5所述的半导体封装，
其中从所述模制化合物中突出的所述可插拔式引线的所述第一导电体的末端相较于被所述模制化合物封装的所述第一导电体的末端具有不同横截面形状，并且
其中从所述模制化合物中突出的所述可插拔式引线的所述第二导电体的末端相较于被所述模制化合物封装的所述第二导电体的末端具有不同横截面形状。
10.如权利要求5所述的半导体封装，
其中所述可插拔式引线的所述第一导电体的外表面，在所述模制化合物外面的区域中与在被所述模制化合物封装的区域中面向不同方向，并且
其中所述可插拔式引线的所述第二导电体的外表面，在所述模制化合物外面的区域中与在被所述模制化合物封装的区域中面向不同方向。
11.如权利要求5所述的半导体封装，
其中所述可插拔式引线的所述第一导电体在所述模制化合物外面的区域中是曲形，而在被所述模制化合物封装的区域中是平坦的，并且
其中所述可插拔式引线的所述第二导电体在所述模制化合物外面的区域中是曲形，而在被所述模制化合物封装的区域中是平坦的。
12.如权利要求5所述的半导体封装，
其中所述可插拔式引线的所述第一导电体具有被所述模制化合物封装的平坦区域，所述半导体裸片被布置于在所述半导体裸片的第一侧的所述第一导电体的所述平坦区域上，并且所述第一裸片端子被布置在所述半导体裸片的所述第一侧并附接至所述第一导电体的所述平坦区域。
13.如权利要求12所述的半导体封装，
其中所述可插拔式引线的所述第二导电体具有被所述模制化合物封装的平坦区域，所述第二导电体的所述平坦区域与所述第一导电体的所述平坦区域隔开，并与所述半导体裸片隔开，并且所述第二个裸片端子被布置在与所述第一侧相对的所述半导体裸片的第二侧处并电连接至所述第二导电体的所述平坦区域。
14.如权利要求13所述半导体封装，
其中所述第二裸片端子通过金属片或者一个或多个键合线电连接至所述第二导电体的所述平坦区域。
15.如权利要求13所述的半导体封装，
所述第二导电体的所述平坦区域在所述第二裸片端子之上延伸并且附接至所述第二裸片端子。
16.如权利要求5所述的半导体封装，
其中所述半导体裸片是具有漏极端子、源极端子和栅极端子的晶体管裸片，所述可插拔式引线的所述第一导电体电连接至所述晶体管裸片的所述漏极端子，所述可插拔式引线的所述第二导电体电连接至所述晶体管裸片的所述源极端子，并且所述可插拔式引线进一步包括第三导电体，所述第三导电体电连接至所述晶体管裸片的所述栅极端子并与所述可插拔式引线的所述第一导电体和所述第二导电体隔离。
17.如权利要求16所述的半导体封装，
其中所述可插拔式引线的所述第二导电体被部分地布置在所述可插拔式引线的所述第一导电体中并与所述可插拔式引线的所述第一导电体隔离，而且所述可插拔式引线的所述第三导电体被部分地布置在所述可插拔式引线的所述第二导电体中并与所述可插拔式引线的所述第二导电体隔离。
18.如权利要求17所述的半导体封装，
其中所述可插拔式引线的所述第二导电体比所述可插拔式引线的所述第一导电体从所述模制化合物中向外突出更长，而且其中所述可插拔式引线的所述第三导电体比所述可插拔式引线的所述第二导电体从所述模制化合物中向外突出更长。
19.如权利要求18所述的半导体封装，
其中所述可插拔式引线的所述导电体中的每个具有未被所述模制化合物覆盖的远端，并且
其中每个导电体的所述远端具有相同的宽度。
20.如权利要求5所述的半导体封装，
其中所述半导体裸片是具有阳极端子和阴极端子的二极管裸片，所述可插拔式引线的所述第一导电体电连接至所述二极管裸片的所述阳极端子，并且所述可插拔式引线的所述第二导电体电连接至所述二极管裸片的所述阴极端子。
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US9153518B2 (en) 2015-10-06

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