CN104409495A - Right-angle gate field plate HFET (Heterojunction Field Effect Transistor) and manufacturing method thereof - Google Patents
Right-angle gate field plate HFET (Heterojunction Field Effect Transistor) and manufacturing method thereof Download PDFInfo
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- CN104409495A CN104409495A CN201410660230.0A CN201410660230A CN104409495A CN 104409495 A CN104409495 A CN 104409495A CN 201410660230 A CN201410660230 A CN 201410660230A CN 104409495 A CN104409495 A CN 104409495A
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- 230000005669 field effect Effects 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title abstract description 6
- 230000004888 barrier function Effects 0.000 claims abstract description 75
- 238000000034 method Methods 0.000 claims abstract description 56
- 230000007704 transition Effects 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000010410 layer Substances 0.000 claims description 140
- 238000002161 passivation Methods 0.000 claims description 55
- 229910052751 metal Inorganic materials 0.000 claims description 50
- 239000002184 metal Substances 0.000 claims description 50
- 238000000151 deposition Methods 0.000 claims description 28
- 239000000463 material Substances 0.000 claims description 21
- 239000011241 protective layer Substances 0.000 claims description 20
- 239000004065 semiconductor Substances 0.000 claims description 13
- 238000004151 rapid thermal annealing Methods 0.000 claims description 6
- 229910052594 sapphire Inorganic materials 0.000 claims description 5
- 239000010980 sapphire Substances 0.000 claims description 5
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 5
- 239000012298 atmosphere Substances 0.000 claims description 4
- 239000003989 dielectric material Substances 0.000 claims description 4
- 238000011049 filling Methods 0.000 claims description 4
- 239000002210 silicon-based material Substances 0.000 claims description 2
- 230000008569 process Effects 0.000 abstract description 30
- 230000015556 catabolic process Effects 0.000 abstract description 14
- 238000005516 engineering process Methods 0.000 description 35
- 229910002601 GaN Inorganic materials 0.000 description 32
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 14
- 238000005566 electron beam evaporation Methods 0.000 description 11
- 238000005530 etching Methods 0.000 description 11
- 230000004907 flux Effects 0.000 description 10
- 230000005684 electric field Effects 0.000 description 9
- 238000001020 plasma etching Methods 0.000 description 9
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 230000008020 evaporation Effects 0.000 description 8
- 238000001704 evaporation Methods 0.000 description 8
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 7
- 229910021529 ammonia Inorganic materials 0.000 description 7
- 229910052739 hydrogen Inorganic materials 0.000 description 7
- 239000001257 hydrogen Substances 0.000 description 7
- 238000004544 sputter deposition Methods 0.000 description 7
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 6
- 229910052733 gallium Inorganic materials 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
- 238000011160 research Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 4
- 238000001451 molecular beam epitaxy Methods 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 239000004411 aluminium Substances 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 239000012159 carrier gas Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000012937 correction Methods 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 150000004678 hydrides Chemical class 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 229920006395 saturated elastomer Polymers 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 229910002704 AlGaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910010413 TiO 2 Inorganic materials 0.000 description 1
- 235000010724 Wisteria floribunda Nutrition 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
Abstract
The invention discloses a right-angle gate field plate HFET (Heterojunction Field Effect Transistor) and a manufacturing method thereof and mainly solves the problem of complex processes of high breakdown voltage achievement in the prior art of field plates. The right-angle gate field plate HFET comprises a substrate (1), a transition layer (2), a barrier layer (3), a source electrode (4), a drain electrode (5), a mesa (6), a gate electrode (7), a passivating layer (8) and a protection layer (11), wherein a groove (9) is arranged inside the passivating layer (8), a right-angle gate field plate (10) is deposited between the passivating layer (8) and the protection layer (11), the edge of the side of the right-angle gate field plate (10), which is close to the gate electrode, is level with the edge of the side of the groove, which is close to the gate electrode, the right-angle gate field plate is electrically connected with the gate electrode (7), and the lower end of the right-angle gate field plate is completed filled inside the groove (9). The right-angle gate field plate HFET has the advantages of simple process and high breakdown voltage, field plate efficiency, reliability and finished product rate.
Description
Technical field
The invention belongs to technical field of semiconductor device, particularly a kind of right angle grid field plate heterojunction field effect transistor, can be used as the basic device of power electronic system.
Technical background
Power semiconductor is the critical elements of power electronic system, is to carry out electric treatable effective tool.In recent years, along with becoming increasingly conspicuous of the energy and environmental problem, research and development novel high-performance, low-loss power device have become one of the effective way improving utilization rate of electrical, energy savings, alleviating energy crisis.But in power device research, at a high speed, there is serious restricting relation between high pressure and low on-resistance, rationally, effectively improving this restricting relation is the key improving overall device performance.Along with market constantly proposes the requirement of more high efficiency, more small size, higher frequency to power system, traditional Si base semiconductor power device performance has approached its theoretical limit.In order to chip area can be reduced further, improves operating frequency, improve working temperature, reduce conducting resistance, improve puncture voltage, reduce machine volume, improve overall efficiency, take gallium nitride as the semiconductor material with wide forbidden band of representative, by means of the electronics saturation drift velocity of its larger energy gap, higher critical breakdown electric field and Geng Gao, and the outstanding advantages such as stable chemical performance, high temperature resistant, radioresistance, show one's talent preparing in high performance power device, application potential is huge.Particularly adopt the High Electron Mobility Transistor of GaN base heterojunction structure, i.e. GaN base HEMT device, especially because of its characteristic such as low on-resistance, high operate frequency, can meet that electronics of future generation are more high-power to power device, the requirement of higher frequency, more small size and more severe hot operation, in economy and military field, there is wide and special application prospect.
But, there is inherent shortcoming in conventional GaN base HEMT device structure, device channel electric field strength can be caused in deformity distribution, especially near drain electrode, there is high peak electric field at device grids.Cause the puncture voltage of actual GaN base HEMT device often far below theoretical eapectation, and there is the integrity problem such as current collapse, inverse piezoelectric effect, seriously constrain the application and development in field of power electronics.In order to overcome the above problems, domestic and international researchers propose numerous method, and field plate structure be wherein effect significantly, the one that is most widely used.Field plate structure is successfully applied in GaN base HEMT power device by the people such as the N.Q.Zhang of U.S. UCSB in 2000 first, develop overlapping gate device, Saturated output electric current is 500mA/mm, and breakdown voltage can reach 570V, and this is the GaN device that reported puncture voltage is the highest at that time, see Highbreakdown GaN HEMT with overlapping gate structure, IEEE Electron Device Letters, Vol.21, No.9, pp.421-423,2000.Subsequently, research institution of various countries expands relevant research work one after another, and the U.S. and Japan are the main leaders in this field.In the U.S., mainly UCSB, Nan Ka university, Cornell University and famous IR company of power electronic device manufacturer etc. are engaged in the research.Japan starts late relatively, but they pay much attention to the work of this respect, fund input great efforts, and it is numerous to be engaged in mechanism, comprising: the major companies such as Toshiba, Furukawa, Panasonic, Toyota and Fuji.Along with going deep into of research, researchers find correspondingly to increase field plate length, can improve device electric breakdown strength.But the increase of field plate length can make field plate efficiency, namely puncture voltage compares field plate length, continuous reduction, the ability that namely field plate improves device electric breakdown strength is tending towards saturated gradually along with the increase of field plate length, see Enhancement of breakdown voltage in AlGaN/GaN highelectron mobility transistors using a field plate, IEEE Transactions on Electron Devices, Vol.48, No.8, pp.1515-1521, 2001, and Development and characteristic analysis of a field-platedAl
2o
3/ AlInN/GaN MOS HEMT, Chinese Physics B, Vol.20, No.1, pp.0172031-0172035,2011.Therefore, in order to improve device electric breakdown strength further, take into account field plate efficiency simultaneously, the people such as the H.L.Xing of UCSB in 2004 propose a kind of double-deck field plate structure, the double-layer grid field plate GaN base HEMT device of their development can obtain the puncture voltage up to 900V, maximum output current 700mA/mm, see High breakdown voltage AlGaN-GaN HEMTs achieved bymultiple field plates, IEEE Electron Device Letters, Vol.25, No.4, pp.161-163,2004.This double-deck field plate structure has become current being used in the world and has improved GaN base power device breakdown characteristics, improves the main flow field plate techniques of overall device performance.But the complex process of the double-deck field plate HEMT device of GaN base, manufacturing cost is higher, and the making of every one deck field plate all needs the processing steps such as photoetching, depositing metal, deposit dielectric passivation.And under will optimizing each layer field plate, dielectric material thickness maximizes to realize puncture voltage, must carry out loaded down with trivial details process debugging and optimization, therefore considerably increase the difficulty that device manufactures, reduce the rate of finished products of device.
Summary of the invention
The object of the invention is to the deficiency for above-mentioned prior art, right angle grid field plate heterojunction field effect transistor that a kind of manufacturing process is simple, puncture voltage is high, field plate efficiency is high and reliability is high and preparation method thereof is provided, to reduce the manufacture difficulty of device, improve breakdown characteristics and the reliability of device, improve the rate of finished products of device.
For achieving the above object, technical scheme of the present invention is achieved in that
One, device architecture
The heterojunction structure that device architecture provided by the invention adopts GaN base semiconductor material with wide forbidden band to form, comprise from bottom to top: substrate, transition zone, barrier layer, passivation layer and protective layer, source electrode is deposited with above barrier layer, drain electrode and grid, table top is carved with in the side of barrier layer, and the degree of depth of table top is greater than the thickness of barrier layer, it is characterized in that, groove is carved with in passivation layer, right angle grid field plate is deposited with between passivation layer and protective layer, this right angle grid field plate and grid are electrically connected, and its lower end is completely in filling groove, right angle grid field plate near grid one lateral edges and groove near grid one side edge-justified calibrations.
As preferably, described depth of groove s is 0.18 ~ 8.9 μm, and width b is 0.51 ~ 7.3 μm.
As preferably, the distance d between described bottom portion of groove and barrier layer is 0.069 ~ 0.42 μm.
As preferably, described groove is 0.69 ~ 8.8 μm near drain electrode one lateral edges and right angle grid field plate near the distance c drained between a lateral edges.
As preferably, described right angle grid field plate is s × (d) near grid one lateral edges and grid near the distance a drained between a lateral edges
0.5, wherein s is depth of groove, and d is the distance between bottom portion of groove and barrier layer.
Two, manufacture method
The first step, extension GaN base semiconductor material with wide forbidden band on substrate, forms transition zone;
Second step, extension GaN base semiconductor material with wide forbidden band on transition zone, forms barrier layer;
3rd step, on barrier layer, first time makes mask, utilizes this mask at the two ends depositing metal of barrier layer, then at N
2carry out rapid thermal annealing in atmosphere, make source electrode and drain electrode respectively;
4th step, on barrier layer, second time makes mask, utilize this mask to etch on the left of source electrode with on the barrier layer on drain electrode right side, and the etched area degree of depth is greater than barrier layer thickness, forms table top;
5th step, on barrier layer, third time makes mask, utilizes depositing metal on this mask barrier layer between the source and drain, makes grid;
6th step, respectively on source electrode top, drain electrode top, grid top and barrier layer other area top deposit passivation layers;
7th step, make mask 4th time over the passivation layer, utilize in the passivation layer of this mask between grid and drain electrode and etch, it is 0.18 ~ 8.9 μm to make degree of depth s, width b is the groove of 0.51 ~ 7.3 μm, distance d between bottom portion of groove and barrier layer is 0.069 ~ 0.42 μm, and this groove is s × (d) near grid one lateral edges and the close distance a drained between a lateral edges of grid
0.5, wherein s is depth of groove, and d is the distance between bottom portion of groove and barrier layer;
8th step, make mask 5th time over the passivation layer, utilize depositing metal on the passivation layer of this mask in groove and between grid and drain electrode, this metal near grid one lateral edges and groove near grid one side edge-justified calibrations, the metal of institute's deposit wants complete filling groove, to make the right angle grid field plate that thickness is 0.18 ~ 8.9 μm, and right angle grid field plate and grid are electrically connected, right angle grid field plate is 0.69 ~ 8.8 μm near drain electrode one lateral edges and the close distance c drained between a lateral edges of groove;
9th step, at other area top deposit insulating dielectric materials of grid field plate top, right angle and passivation layer, forms protective layer, completes the making of whole device.
Device of the present invention with adopt the HFET of traditional grid field plate to compare to have the following advantages:
1. further increase puncture voltage.
The present invention is owing to adopting right angle grid field plate structure, make device in running order be especially in the operating state of OFF state time, barrier layer surface potential raises from grid gradually to drain electrode, thus add depletion region in barrier layer, i.e. high resistance area, area, improve the distribution of depletion region, impel the depletion region between grid and drain electrode in barrier layer to bear larger drain-source voltage, thus substantially increase the puncture voltage of device.
2. further reduce gate leakage current, improve the reliability of device.
The present invention is owing to adopting right angle grid field plate structure, the distribution of electric field line in device barrier layer depletion region is made to obtain more effective modulation, in device, grid is near drain electrode one lateral edges, right angle grid field plate all can produce a peak electric field near drain electrode one lateral edges and groove near drain electrode one lateral edges, and by adjusting the thickness of right angle grid field plate underlying passivation layer, depth of groove and width, groove near grid one lateral edges and grid near distance drain between a lateral edges and right angle grid field plate near a lateral edges and the close distance drained between a lateral edges of groove of draining, each peak electric field above-mentioned can be made equal and be less than the breakdown electric field of GaN base semiconductor material with wide forbidden band, thus decrease electric field line edge collected by of grid near drain electrode side to greatest extent, significantly reduce the electric field at this place, substantially reduce gate leakage current, the reliability of device and breakdown characteristics is made all to obtain remarkable enhancing.
3. technique is simple, is easy to realize, and improves rate of finished products.
In device architecture of the present invention, the making of right angle grid field plate only needs a step process just can complete, and avoids the process complications problem that traditional stack layers field plate structure brings, substantially increases the rate of finished products of device.
Simulation result shows, the puncture voltage of device of the present invention is far longer than the HFET adopting traditional grid field plate.
Technology contents of the present invention and effect is further illustrated below in conjunction with drawings and Examples.
Accompanying drawing explanation
Fig. 1 is the structure chart of the HFET adopting traditional grid field plate;
Fig. 2 is the structure chart of right angle of the present invention grid field plate heterojunction field effect transistor;
Fig. 3 is the Making programme figure of right angle of the present invention grid field plate heterojunction field effect transistor;
Fig. 4 punctures curve chart to traditional devices and device simulation gained of the present invention.
Embodiment
With reference to Fig. 2; right angle of the present invention grid field plate heterojunction field effect transistor is that it comprises based on GaN base wide bandgap semiconductor heterojunction structure: substrate 1, transition zone 2, barrier layer 3, source electrode 4, drain electrode 5, table top 6, grid 7, passivation layer 8, groove 9, right angle grid field plate 10 and protective layer 11.Substrate 1, transition zone 2 and barrier layer 3 are for distribute from bottom to top, source electrode 4 and drain electrode 5 are deposited on the two ends of barrier layer 3, grid 7 is deposited on the barrier layer 3 between source electrode 4 and drain electrode 5, and table top 6 is produced on the left of source electrode and drain electrode right side, and this land depth is greater than barrier layer thickness; Passivation layer 8 is positioned at other area top of source electrode top, drain electrode top, grid top and barrier layer.Groove 9 is positioned at passivation layer 8, this depth of groove s is 0.18 ~ 8.9 μm, width b is 0.51 ~ 7.3 μm, distance d bottom groove 9 and between barrier layer is 0.069 ~ 0.42 μm, and near grid one lateral edges and grid, the distance d bottom the distance a, groove 9 degree of depth s that drain between a lateral edges, groove 9 and between barrier layer meets relation a=s × (d) to groove 9
0.5.Right angle grid field plate 10 is deposited between passivation layer 8 and protective layer 11, and right angle grid field plate is near grid one lateral edges and groove near grid one side edge-justified calibrations, and this right angle grid field plate 10 is electrically connected with grid 7.Right angle grid field plate is 0.69 ~ 8.8 μm near drain electrode one lateral edges and the close distance c drained between a lateral edges of groove.Protective layer 11 is positioned at other area top of grid field plate 10 top, right angle and passivation layer.
The substrate 1 of above-mentioned device adopts sapphire or carborundum or silicon materials; Transition zone 2 is made up of the GaN base semiconductor material with wide forbidden band that some layers are identical or different, and its thickness is 1 ~ 5 μm; Barrier layer 3 is made up of the GaN base semiconductor material with wide forbidden band that some layers are identical or different, and its thickness is 5 ~ 50nm; Passivation layer 8 and protective layer 11 all can adopt SiO
2, SiN, Al
2o
3, HfO
2, La
2o
3, TiO
2in any one or other insulating dielectric materials, the thickness of passivation layer is the distance d sum bottom the degree of depth s of groove 9 and groove 9 and between barrier layer 3, namely 0.249 ~ 9.32 μm; The thickness of protective layer is 0.21 ~ 5.2 μm; Right angle grid field plate 10 adopts the combination of three layers of different metal to form, and its thickness is 0.18 ~ 8.9 μm.
With reference to Fig. 3, the present invention makes the process of right angle grid field plate heterojunction field effect transistor, provides following three kinds of embodiments:
Embodiment one: making substrate is sapphire, passivation layer is Al
2o
3, protective layer is SiO
2, right angle grid field plate is the right angle grid field plate heterojunction field effect transistor of Ti/Mo/Au metallic combination.
Step 1. is the transition zone 2 of extension GaN material making from bottom to top in Sapphire Substrate 1, as Fig. 3 a.
Use metal organic chemical vapor deposition technology epitaxial thickness in Sapphire Substrate 1 is the transition zone 2 that do not adulterate of 1 μm, and the GaN material that this transition zone is respectively 30nm and 0.97 μm by thickness is from bottom to top formed.The process conditions that extension lower floor GaN material adopts are: temperature is 530 DEG C, and pressure is 45Torr, and hydrogen flowing quantity is 4400sccm, and ammonia flow is 4400sccm, and gallium source flux is 22 μm of ol/min; The process conditions that extension upper strata GaN material adopts are: temperature is 960 DEG C, and pressure is 45Torr, and hydrogen flowing quantity is 4400sccm, and ammonia flow is 4400sccm, and gallium source flux is 120 μm of ol/min.
Step 2. is the unadulterated Al of deposit in GaN transition layer 2
0.5ga
0.5n makes barrier layer 3, as Fig. 3 b.
Use metal organic chemical vapor deposition technology deposition thickness in GaN transition layer 2 to be 5nm, and al composition is the non-doped with Al of 0.5
0.5ga
0.5n barrier layer 3, its process conditions adopted are: temperature is 980 DEG C, and pressure is 45Torr, and hydrogen flowing quantity is 4400sccm, and ammonia flow is 4400sccm, and gallium source flux is 35 μm of ol/min, and aluminium source flux is 7 μm of ol/min.
Step 3. makes source electrode 4 and drain electrode 5, as Fig. 3 c at the two ends depositing metal Ti/Al/Ni/Au of barrier layer 3.
At Al
0.5ga
0.5on N barrier layer 3, first time makes mask, uses electron beam evaporation technique at its two ends depositing metal, then at N
2rapid thermal annealing is carried out in atmosphere, make source electrode 4 and drain electrode 5, wherein the metal of institute's deposit is Ti/Al/Ni/Au metallic combination, namely Ti, Al, Ni and Au is respectively from bottom to top, its thickness is 0.018 μm/0.135 μm/0.046 μm/0.052 μm, and namely the thickness of Ti, Al, Ni and Au is respectively 0.018 μm, 0.135 μm, 0.046 μm and 0.052 μm.The process conditions that depositing metal adopts are: vacuum degree is less than 1.8 × 10
-3pa, power bracket is 200 ~ 1000W, and evaporation rate is less than
the process conditions that rapid thermal annealing adopts are: temperature is 850 DEG C, and the time is 35s.
Step 4. is carried out etching and is made table top 6, as Fig. 3 d on the barrier layer of the source electrode left side with drain electrode the right.
At Al
0.5ga
0.5on N barrier layer 3, second time makes mask, and use reactive ion etching technology to etch on the source electrode left side with the barrier layer on drain electrode the right, form table top 6, etching depth is 10nm.The process conditions that etching adopts are: Cl
2flow is 15sccm, and pressure is 10mTorr, and power is 100W.
On step 5. barrier layer between the source and drain, depositing metal Ni/Au makes grid 7, as Fig. 3 e.
At Al
0.5ga
0.5on N barrier layer 3, third time makes mask, use depositing metal on electron beam evaporation technique barrier layer between the source and drain, make grid 7, wherein the metal of institute's deposit is Ni/Au metallic combination, namely lower floor is Ni, upper strata is Au, its thickness is 0.041 μm/0.23 μm, and namely the thickness of Ni and Au is respectively 0.041 μm and 0.23 μm.The process conditions that depositing metal adopts are: vacuum degree is less than 1.8 × 10
-3pa, power bracket is 200 ~ 1000W, and evaporation rate is less than
Step 6. on source electrode top, drain electrode top, grid top and barrier layer other area top deposits Al
2o
3, make passivation layer 8, as Fig. 3 f.
Use atomic layer deposition technology to cover other area top of source electrode top, drain electrode top, grid top and barrier layer respectively, complete the Al that deposition thickness is 0.249 μm
2o
3passivation layer 8.The process conditions that deposit passivation layer adopts are: with TMA and H
2o is reaction source, and carrier gas is N
2, carrier gas flux is 200sccm, and underlayer temperature is 300 DEG C, and air pressure is 700Pa.
Carry out etching in the passivation layer of step 7. between grid 7 and drain electrode 5 and make groove 9, as Fig. 3 g.
Passivation layer 8 makes mask the 4th time, use in the passivation layer of reactive ion etching technology between grid 7 and drain electrode 5 and etch, to make groove 9, its further groove 9 degree of depth s is 0.18 μm, width b is 0.51 μm, distance d bottom groove 9 and between barrier layer 3 is 0.069 μm, and groove 9 is 0.047 μm near grid one lateral edges and the close distance a drained between a lateral edges of grid.The process conditions that etching adopts are: CF
4flow is 45sccm, O
2flow is 5sccm, and pressure is 15mTorr, and power is 250W.
Depositing metal Ti/Mo/Au on the passivation layer of step 8. in groove 9 and between grid and drain electrode, makes right angle grid field plate 10, as Fig. 3 h.
Passivation layer 8 makes mask the 5th time, use depositing metal on the passivation layer of electron beam evaporation technique in groove 9 and between grid and drain electrode, this metal near grid one lateral edges and groove near grid one side edge-justified calibrations, form right angle grid field plate 10, and right angle grid field plate and grid are electrically connected, the metal of institute's deposit is Ti/Mo/Au metallic combination, namely lower floor is Ti, middle level is Mo, upper strata is Au, its thickness is 0.08 μm/0.06 μm/0.04 μm, i.e. Ti, the thickness of Mo and Au is respectively 0.08 μm, 0.06 μm and 0.04 μm, right angle grid field plate is 0.69 μm near drain electrode one lateral edges and the close distance c drained between a lateral edges of groove.The process conditions that depositing metal adopts are: vacuum degree is less than 1.8 × 10
-3pa, power bracket is 200 ~ 1000W, and evaporation rate is less than
Step 9. is at other area top deposit SiO of grid field plate 10 top, right angle and passivation layer 8
2make protective layer 11, as Fig. 3 i.
Use plasma enhanced CVD technology at other area top deposit SiO of grid field plate 10 top, right angle and passivation layer 8
2make protective layer 11, its thickness is 0.21 μm, thus completes the making of whole device.The process conditions that deposit protective layer adopts are: N
2o flow is 850sccm, SiH
4flow is 200sccm, and temperature is 250 DEG C, and RF power is 25W, and pressure is 1100mTorr.
Embodiment two: making substrate is carborundum, passivation layer is SiO
2, protective layer is SiN, and right angle grid field plate is the right angle grid field plate heterojunction field effect transistor of Ti/Ni/Au metallic combination.
Step one. in silicon carbide substrates 1, extension AlN and GaN material make transition zone 2 from bottom to top, as Fig. 3 a.
1.1) the unadulterated AlN material that metal organic chemical vapor deposition technology epitaxial thickness in silicon carbide substrates 1 is 50nm is used; The process conditions of its extension are: temperature is 1000 DEG C, and pressure is 45Torr, and hydrogen flowing quantity is 4600sccm, and ammonia flow is 4600sccm, and aluminium source flux is 5 μm of ol/min;
1.2) use metal organic chemical vapor deposition technology epitaxial thickness on AlN material to be the GaN material of 2.45 μm, complete the making of transition zone 2; The process conditions of its extension are: temperature is 1000 DEG C, and pressure is 45Torr, and hydrogen flowing quantity is 4600sccm, and ammonia flow is 4600sccm, and gallium source flux is 120 μm of ol/min.
The extension of this step is not limited to metal organic chemical vapor deposition technology, also can adopt molecular beam epitaxy technique or hydride gas-phase epitaxy technology.
Step 2. extension Al from bottom to top on transition zone 2
0.3ga
0.7n and GaN material make barrier layer 3, as Fig. 3 b.
2.1) use that metal organic chemical vapor deposition technology deposition thickness in GaN transition layer 2 is 27nm, al composition is the Al of 0.3
0.3ga
0.7n material; The process conditions of its extension are: temperature is 1100 DEG C, and pressure is 45Torr, and hydrogen flowing quantity is 4600sccm, and ammonia flow is 4600sccm, and gallium source flux is 16 μm of ol/min, and aluminium source flux is 8 μm of ol/min;
2.2) use metal organic chemical vapor deposition technology at Al
0.3ga
0.7on N material, epitaxial thickness is the GaN material of 3nm, completes the making of barrier layer 3; The process conditions of its extension are: temperature is 1040 DEG C, and pressure is 41Torr, and hydrogen flowing quantity is 4300sccm, and ammonia flow is 4300sccm, and gallium source flux is 14 μm of ol/min.
The extension of this step is not limited to metal organic chemical vapor deposition technology, also can adopt molecular beam epitaxy technique or hydride gas-phase epitaxy technology.
Step 3. make source electrode 4 and drain electrode 5, as Fig. 3 c at the two ends depositing metal Ti/Al/Ni/Au of barrier layer 3.
3.1) on barrier layer 3, first time makes mask, use electron beam evaporation technique at its two ends depositing metal, the metal of deposit is Ti/Al/Ni/Au metallic combination, namely Ti, Al, Ni and Au is respectively from bottom to top, its thickness is 0.018 μm/0.135 μm/0.046 μm/0.052 μm, and its depositing metal process conditions are: vacuum degree is less than 1.8 × 10
-3pa, power bracket is 200 ~ 1000W, and evaporation rate is less than
3.2) at N
2carry out rapid thermal annealing in atmosphere, complete the making of source electrode 4 and drain electrode 5, the process conditions of its rapid thermal annealing are: temperature is 850 DEG C, and the time is 35s.
The Metal deposition of this step is not limited to electron beam evaporation technique, also can adopt sputtering technology.
Step 4. on the barrier layer 3 on the left side of source electrode and the right of drain electrode, carry out etching make table top 6, as Fig. 3 d.
On barrier layer 3, second time makes mask, and use reactive ion etching technology to etch on the source electrode left side with the barrier layer 3 on drain electrode the right, form table top 6, wherein etching depth is 100nm; The process conditions that reactive ion etching technology etching table top 6 adopts are: Cl
2flow is 15sccm, and pressure is 10mTorr, and power is 100W.
The etching of this step is not limited to reactive ion etching technology, also can adopt sputtering technology or plasma etching technology.
Step 5. on barrier layer between the source and drain, depositing metal Ni/Au makes grid 7, as Fig. 3 e.
On barrier layer 3, third time makes mask, and use depositing metal on electron beam evaporation technique barrier layer between the source and drain, make grid 7, the metal of wherein institute's deposit is Ni/Au metallic combination, and its thickness is 0.041 μm/0.23 μm; The process conditions that electron beam evaporation technique deposit Ni/Au adopts are: vacuum degree is less than 1.8 × 10
-3pa, power bracket is 200 ~ 1000W, and evaporation rate is less than
The Metal deposition of this step is not limited to electron beam evaporation technique, also can adopt sputtering technology.
Step 6. on source electrode top, drain electrode top, grid top and barrier layer other area top deposits SiO
2make passivation layer 8, as Fig. 3 f.
Use plasma enhanced CVD technology to cover other area top of source electrode top, drain electrode top, grid top and barrier layer respectively, complete the SiO that deposition thickness is 5.4 μm
2passivation layer 8; Its process conditions adopted are: N
2o flow is 850sccm, SiH
4flow is 200sccm, and temperature is 250 DEG C, and RF power is 25W, and pressure is 1100mTorr.
The deposit of the passivation layer of this step is not limited to plasma enhanced CVD technology, also can adopt evaporation technique or atomic layer deposition technology or sputtering technology or molecular beam epitaxy technique.
Step 7. carry out etching in the passivation layer 8 between grid 7 and drain electrode 5 and make groove 9, as Fig. 3 g.
Passivation layer 8 makes mask the 4th time, use in the passivation layer of reactive ion etching technology between grid 7 and drain electrode 5 and etch, to make groove 9, its further groove 9 degree of depth s is 5.2 μm, width b is 4.5 μm, distance d bottom groove 9 and between barrier layer is 0.2 μm, and groove 9 is 2.326 μm near grid one lateral edges and the close distance a drained between a lateral edges of grid; The process conditions that etched recesses 9 adopts are: CF
4flow is 45sccm, O
2flow is 5sccm, and pressure is 15mTorr, and power is 250W.
The etching of this step is not limited to reactive ion etching technology, also can adopt sputtering technology or plasma etching technology.
Step 8. depositing metal Ti/Ni/Au on the passivation layer in groove 9 and between grid and drain electrode, makes right angle grid field plate 10, as Fig. 3 h.
Passivation layer 8 makes mask the 5th time, use depositing metal on the passivation layer of electron beam evaporation technique in groove 9 and between grid and drain electrode, this metal near grid one lateral edges and groove near grid one side edge-justified calibrations, form right angle grid field plate 10, and right angle grid field plate and grid are electrically connected, the metal of institute's deposit is Ti/Ni/Au metallic combination, namely lower floor is Ti, middle level is Ni, upper strata is Au, its thickness is 3 μm/1.8 μm/0.4 μm, and right angle grid field plate is 5 μm near drain electrode one lateral edges and the close distance c drained between a lateral edges of groove.The process conditions that electron beam evaporation technique deposit Ti/Ni/Au adopts are: vacuum degree is less than 1.8 × 10
-3pa, power bracket is 200 ~ 1000W, and evaporation rate is less than
The Metal deposition of this step is not limited to electron beam evaporation technique, also can adopt sputtering technology.
Step 9. make protective layer 11, as Fig. 3 i at other area top deposit SiN of grid field plate 10 top, right angle and passivation layer 8.
Use plasma enhanced CVD technology to make protective layer 11 at other area top deposit SiN of grid field plate 10 top, right angle and passivation layer 8, its thickness is 2.5 μm, thus completes the making of whole device; Its process conditions adopted are: gas is NH
3, N
2and SiH
4, gas flow is respectively 2.5sccm, 950sccm and 250sccm, and temperature, RF power and pressure are respectively 300 DEG C, 25W and 950mTorr.
The deposit of the protective layer of this step is not limited to plasma enhanced CVD technology, also can adopt evaporation technique or atomic layer deposition technology or sputtering technology or molecular beam epitaxy technique.
Embodiment three: making substrate is silicon, passivation layer is SiN, and protective layer is SiO
2, right angle grid field plate is the right angle grid field plate heterojunction field effect transistor of Ti/Pt/Au metallic combination.
Steps A. on silicon substrate 1, extension AlN and GaN material make transition zone 2 from bottom to top, as Fig. 3 a.
A1) metal organic chemical vapor deposition technology is used to be 800 DEG C in temperature, pressure is 40Torr, and hydrogen flowing quantity is 4000sccm, and ammonia flow is 4000sccm, aluminium source flux is under the process conditions of 25 μm of ol/min, and on silicon substrate 1, epitaxial thickness is the AlN material of 200nm;
A2) metal organic chemical vapor deposition technology is used to be 980 DEG C in temperature, pressure is 45Torr, hydrogen flowing quantity is 4000sccm, ammonia flow is 4000sccm, gallium source flux is under the process conditions of 120 μm of ol/min, on AlN material, epitaxial thickness is the GaN material of 4.8 μm, completes the making of transition zone 2.
Step B. deposit Al from bottom to top on transition zone
0.1ga
0.9n and GaN material make barrier layer 3, as Fig. 3 b.
B1) metal organic chemical vapor deposition technology is used to be 1000 DEG C in temperature, pressure is 40Torr, hydrogen flowing quantity is 4000sccm, ammonia flow is 4000sccm, gallium source flux is 12 μm of ol/min, aluminium source flux is under the process conditions of 12 μm of ol/min, and in GaN transition layer 2, epitaxial thickness is 46nm, and al composition is the Al of 0.1
0.1ga
0.9n material;
B2) use metal organic chemical vapor deposition technology to be 1000 DEG C in temperature, pressure is 40Torr, and hydrogen flowing quantity is 4000sccm, and ammonia flow is 4000sccm, and gallium source flux is under the process conditions of 3 μm of ol/min, at Al
0.1ga
0.9on N material, epitaxial thickness is the GaN material of 4nm, completes the making of barrier layer 3.
Step C. makes source electrode 4 and drain electrode 5, as Fig. 3 c at barrier layer 3 two ends depositing metal Ti/Al/Ni/Au.
C1) on barrier layer 3, first time makes mask, uses electron beam evaporation technique to be less than 1.8 × 10 in vacuum degree
-3pa, power bracket is 200 ~ 1000W, and evaporation rate is less than
process conditions under, at its two ends depositing metal, the metal of wherein institute's deposit is Ti/Al/Ni/Au metallic combination, is namely respectively Ti, Al, Ni and Au from bottom to top, and its thickness is 0.018 μm/0.135 μm/0.046 μm/0.052 μm;
C2) at N
2atmosphere, temperature is 850 DEG C, and the time is carry out rapid thermal annealing under the process conditions of 35s, completes the making of source electrode 4 and drain electrode 5.
Step D. carries out etching and makes table top 6, as Fig. 3 d on the barrier layer 3 of the source electrode left side with drain electrode the right.
On barrier layer 3, second time makes mask, uses reactive ion etching technology at Cl
2flow is 15sccm, and pressure is 10mTorr, and power is under the process conditions of 100W, and the source electrode left side with the barrier layer 3 on drain electrode the right etch, and form table top 6, wherein etching depth is 200nm.
Step e. on barrier layer between the source and drain, depositing metal Ni/Au makes grid 7, as Fig. 3 e.
On barrier layer 3, third time makes mask, uses electron beam evaporation technique to be less than 1.8 × 10 in vacuum degree
-3pa, power bracket is 200 ~ 1000W, and evaporation rate is less than
process conditions under, depositing metal on barrier layer between the source and drain, make grid 7, the metal of institute's deposit is Ni/Au metallic combination, and namely lower floor is Ni, upper strata is Au, and its thickness is 0.041 μm/0.23 μm.
Step F. on source electrode top, drain electrode top, grid top and barrier layer other area top deposits SiN material make passivation layer 8, as Fig. 3 f.
Plasma enhanced CVD technology is used to be NH at gas
3, N
2and SiH
4gas flow is respectively 2.5sccm, 950sccm and 250sccm, temperature, RF power and pressure are respectively 300 DEG C, under the process conditions of 25W and 950mTorr, on source electrode top, drain electrode top, grid top and barrier layer other area top deposition thicknesses be the SiO of 9.32 μm
2make passivation layer 8.
Carry out etching in the passivation layer 8 of step G. between grid 7 and drain electrode 5 and make groove 9, as Fig. 3 g.
Passivation layer 8 makes mask, CF the 4th time
4flow is 45sccm, O
2flow is 5sccm, pressure is 15mTorr, power is under the process conditions of 250W, etch in passivation layer between grid 7 and drain electrode 5, to make groove 9, its further groove 9 degree of depth s is 8.9 μm, and width b is 7.3 μm, distance d bottom groove 9 and between barrier layer is 0.42 μm, and groove 9 is 5.768 μm near grid one lateral edges and the close distance a drained between a lateral edges of grid.
Depositing metal Ti/Pt/Au on the passivation layer of step H. in groove 9 and between grid and drain electrode, makes right angle grid field plate 10, as Fig. 3 h.
Passivation layer 8 makes mask the 5th time, uses electron beam evaporation technique to be less than 1.8 × 10 in vacuum degree
-3pa, power bracket is 200 ~ 1000W, and evaporation rate is less than
process conditions under, depositing metal on passivation layer in groove 9 and between grid and drain electrode, this metal near grid one lateral edges and groove near grid one side edge-justified calibrations, form right angle grid field plate 10, and right angle grid field plate and grid are electrically connected, the metal of institute's deposit is thickness is Ti/Pt/Au metallic combination, namely lower floor is Ti, middle level is Pt, upper strata is Au, its thickness is 5 μm/3 μm/0.9 μm, and right angle grid field plate is 8.8 μm near drain electrode one lateral edges and the close distance c drained between a lateral edges of groove.
Step I. is at other area top deposit SiO of grid field plate 10 top, right angle and passivation layer 8
2, make protective layer 11, as Fig. 3 i.
Use plasma enhanced CVD technology at N
2o flow is 850sccm, SiH
4flow is 200sccm, and temperature is 250 DEG C, and RF power is 25W, and pressure is under the process conditions of 1100mTorr, at other area top deposit SiO of grid field plate 10 top, right angle and passivation layer 8
2make protective layer 11, its thickness is 5.2 μm, thus completes the making of whole device.
Effect of the present invention further illustrates by following emulation.
Emulate the employing HFET of traditional grid field plate and the breakdown characteristics of device of the present invention, result is as Fig. 4.
As seen from Figure 4, the HFET of traditional grid field plate is adopted to puncture, namely drain current increases sharply, time drain-source voltage greatly about 580V, and the drain-source voltage of device of the present invention when puncturing is greatly about 1380V, proves that the puncture voltage of device of the present invention is far longer than the puncture voltage of the HFET adopting traditional grid field plate.
For those skilled in the art; after having understood content of the present invention and principle; can when not deviating from the principle and scope of the present invention; carry out various correction in form and details and change according to method of the present invention, but these are based on correction of the present invention with change still within claims of the present invention.
Claims (8)
1. a right angle grid field plate heterojunction field effect transistor, comprise from bottom to top: substrate (1), transition zone (2), barrier layer (3), passivation layer (8) and protective layer (11), source electrode (4) is deposited with above barrier layer (3), drain electrode (5) and grid (7), table top (6) is carved with in the side of barrier layer (3), and the degree of depth of table top is greater than the thickness of barrier layer, it is characterized in that, groove (9) is carved with in passivation layer (8), right angle grid field plate (10) is deposited with between passivation layer (8) and protective layer (11), this right angle grid field plate (10) and grid (7) are electrically connected, and its lower end is completely in filling groove (9), right angle grid field plate near grid one lateral edges and groove near grid one side edge-justified calibrations.
2. right angle according to claim 1 grid field plate heterojunction field effect transistor, it is characterized in that the degree of depth s of groove (9) is 0.18 ~ 8.9 μm, width b is 0.51 ~ 7.3 μm; Distance d between groove (9) bottom and barrier layer (3) is 0.069 ~ 0.42 μm.
3. right angle according to claim 1 grid field plate heterojunction field effect transistor, is characterized in that groove (9) is s × (d) near grid one lateral edges and the close distance a drained between a lateral edges of grid (7)
0.5, wherein s is depth of groove, and d is the distance between bottom portion of groove and barrier layer; Right angle grid field plate (10) is 0.69 ~ 8.8 μm near drain electrode one lateral edges and the close distance c drained between a lateral edges of groove (9).
4. right angle according to claim 1 grid field plate heterojunction field effect transistor, is characterized in that substrate (1) adopts sapphire or carborundum or silicon materials.
5. make a method for right angle grid field plate heterojunction field effect transistor, comprise the steps:
The first step, at the upper extension GaN base semiconductor material with wide forbidden band of substrate (1), forms transition zone (2);
Second step, extension GaN base semiconductor material with wide forbidden band on transition zone, forms barrier layer (3);
3rd step, made mask in barrier layer (3) upper first time, and utilized this mask at the two ends depositing metal of barrier layer (3), then at N
2carry out rapid thermal annealing in atmosphere, make source electrode (4) and drain electrode (5) respectively;
4th step, makes mask in the upper second time of barrier layer (3), utilize this mask to etch on the left of source electrode with on the barrier layer on drain electrode right side, and the etched area degree of depth is greater than barrier layer thickness, forms table top (6);
5th step, made mask in barrier layer (3) upper third time, and utilized depositing metal on this mask barrier layer between the source and drain, make grid (7);
6th step, respectively on source electrode top, drain electrode top, grid top and barrier layer other area top deposit passivation layers (8);
7th step, mask is made upper 4th time at passivation layer (8), utilize in the passivation layer (8) of this mask between grid and drain electrode and etch, it is 0.18 ~ 8.9 μm to make degree of depth s, width b is the groove (9) of 0.51 ~ 7.3 μm, distance d between groove (9) bottom and barrier layer (3) is 0.069 ~ 0.42 μm, and this groove is s × (d) near grid one lateral edges and the close distance a drained between a lateral edges of grid
0.5, wherein s is depth of groove, and d is the distance between bottom portion of groove and barrier layer;
8th step, mask is made upper 5th time at passivation layer (8), utilize depositing metal on the passivation layer of this mask in groove (9) and between grid and drain electrode, this metal near grid one lateral edges and groove near grid one side edge-justified calibrations, institute's depositing metal wants complete filling groove, to make right angle grid field plate (10) that thickness is 0.18 ~ 8.9 μm, and right angle grid field plate (10) and grid (7) are electrically connected, right angle grid field plate (10) is 0.69 ~ 8.8 μm near drain electrode one lateral edges and the close distance c drained between a lateral edges of groove (9),
9th step, at other area top deposit insulating dielectric materials of grid field plate (10) top, right angle and passivation layer (8), forms protective layer (11), completes the making of whole device.
6. method according to claim 5, it is characterized in that the metal of deposit on the passivation layer in groove (9) and between grid and drain electrode adopts three-layer metal combination Ti/Mo/Au, namely lower floor is Ti, middle level is Mo, upper strata is Au, and its thickness is 0.08 ~ 5 μm/0.06 ~ 3 μm/0.04 ~ 0.9 μm.
7. method according to claim 5, it is characterized in that the metal of institute's deposit on the passivation layer in groove (9) and between grid and drain electrode, all adopt three-layer metal combination Ti/Ni/Au, namely lower floor is Ti, middle level is Ni, upper strata is Au, and its thickness is 0.08 ~ 5 μm/0.06 ~ 3 μm/0.04 ~ 0.9 μm.
8. method according to claim 5, it is characterized in that the metal of deposit on the passivation layer in groove (9) and between grid and drain electrode, all adopt three-layer metal combination Ti/Pt/Au further, namely lower floor is Ti, middle level is Pt, upper strata is Au, and its thickness is 0.08 ~ 5 μm/0.06 ~ 3 μm/0.04 ~ 0.9 μm.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101414625A (en) * | 2008-12-01 | 2009-04-22 | 西安电子科技大学 | Groove gate type gate-leakage composite field plate transistor with high electron mobility |
| US20090261384A1 (en) * | 2006-09-22 | 2009-10-22 | Korea Advanced Institute Of Science And Technology | Gallium nitride high electron mobility transistor having inner field-plate for high power applications |
| CN103137476A (en) * | 2011-12-01 | 2013-06-05 | 电力集成公司 | GaN high voltage HFET with passivation plus gate dielectric multilayer structure |
| US20130313613A1 (en) * | 2012-04-26 | 2013-11-28 | Asif Khan | Selectively Area Regrown III-Nitride High Electron Mobility Transistor |
-
2014
- 2014-11-18 CN CN201410660230.0A patent/CN104409495B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090261384A1 (en) * | 2006-09-22 | 2009-10-22 | Korea Advanced Institute Of Science And Technology | Gallium nitride high electron mobility transistor having inner field-plate for high power applications |
| CN101414625A (en) * | 2008-12-01 | 2009-04-22 | 西安电子科技大学 | Groove gate type gate-leakage composite field plate transistor with high electron mobility |
| CN103137476A (en) * | 2011-12-01 | 2013-06-05 | 电力集成公司 | GaN high voltage HFET with passivation plus gate dielectric multilayer structure |
| US20130313613A1 (en) * | 2012-04-26 | 2013-11-28 | Asif Khan | Selectively Area Regrown III-Nitride High Electron Mobility Transistor |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107068739A (en) * | 2017-03-29 | 2017-08-18 | 西安电子科技大学 | Arc grid field plate current apertures power device |
| CN107068739B (en) * | 2017-03-29 | 2019-12-03 | 西安电子科技大学 | Arc grid field plate current apertures power device |
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