CN104394113B - A kind of reception terminal for the air-ground narrow-band communication system of unmanned plane - Google Patents
A kind of reception terminal for the air-ground narrow-band communication system of unmanned plane Download PDFInfo
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- CN104394113B CN104394113B CN201410689481.1A CN201410689481A CN104394113B CN 104394113 B CN104394113 B CN 104394113B CN 201410689481 A CN201410689481 A CN 201410689481A CN 104394113 B CN104394113 B CN 104394113B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
- H04L7/002—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation
- H04L7/0029—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation interpolation of received data signal
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
- H04B1/7073—Synchronisation aspects
- H04B1/7087—Carrier synchronisation aspects
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0071—Use of interleaving
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/14—Relay systems
- H04B7/15—Active relay systems
- H04B7/185—Space-based or airborne stations; Stations for satellite systems
- H04B7/18502—Airborne stations
- H04B7/18506—Communications with or from aircraft, i.e. aeronautical mobile service
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- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The invention discloses a kind of reception terminals for the air-ground narrow-band communication system of unmanned plane, it includes Receiver Module, intermediate frequency filtering module, ADC and FPGA, Receiver Module receives the control signal from external signal of communication and from FPGA, the output of Receiver Module is connected with intermediate frequency filtering module, the output of intermediate frequency filtering module is connected with ADC, the output of ADC is connected with FPGA, the clock control output of FPGA is connected with ADC, the gain control output of FPGA is connected with Receiver Module, and FPGA also passes through internal interface demodulated output data.The present invention pair can telemetering, remote control, number pass unmanned plane system in air-ground narrow band signal communication subsystem carry out it is perfect, suitable for aerial unmanned plane terminal.
Description
Technical field
The present invention relates to a kind of reception terminals for the air-ground narrow-band communication system of unmanned plane.
Background technology
Unmanned plane has many advantages, such as that low cost effectiveness, zero injures and deaths and deployment are flexible, can help even to replace the mankind very
It plays a role in more scenes, such as the personnel after calamity search and rescue, infrastructure supervision.No matter in civilian or military domain, nobody
Machine has wide application and development prospect.
Can telemetering, remote control, number pass unmanned plane system include Air-Ground two-way communication and ground-ground two-way communication two parts,
It is divided according to wire data type, wideband signal communication and narrow band signal communication two types, middle width strip letter can be divided into
Number for unmanned plane reconnaissance image data transmission service and unmanned plane telemetry service, narrow band signal it is distant between handheld terminal and unmanned plane
Control communication service, communication service between handheld terminal and car-mounted terminal.And a link critically important in narrow band communication is exactly it
Terminal is received, reception terminal is unmanned plane terminal.
The content of the invention
It is an object of the invention to overcome the deficiencies of the prior art and provide a kind of resource loss is low, data processing is accurate
The reception terminal for the air-ground narrow-band communication system of unmanned plane.
The purpose of the present invention is what is be achieved through the following technical solutions：One kind is used for the air-ground narrow-band communication system of unmanned plane
Reception terminal, it include Receiver Module, intermediate frequency filtering module, ADC and FPGA, Receiver Module receive from outside
Signal of communication and control signal from FPGA, the output of Receiver Module be connected with intermediate frequency filtering module, intermediate frequency filter
The output of ripple module is connected with ADC, and the output of ADC is connected with FPGA, and the clock control output of FPGA is connected with ADC, FPGA's
Gain control output is connected with Receiver Module, and FPGA also passes through internal interface demodulated output data；
The FPGA includes down conversion module, decimal abstraction module, thick frequency offset correction module, narrow-band filtering module, position
Synchronization module, fine frequency offset synchronization module, decoding/judging module, de-interleaving block and uniform buffer module, down conversion module it is defeated
Enter and be connected with ADC, the output of down conversion module is connected with decimal abstraction module, the output of decimal abstraction module and thick frequency offset correction
Module connects, and the output of thick frequency offset correction module is connected with narrow-band filtering module, output and the bit synchronization mould of narrow-band filtering module
Block connects, and the output of bit sync module is connected with fine frequency offset synchronization module, output and the decoding/judgement mould of fine frequency offset synchronization module
Block connects, and the output of decoding/judging module is connected with de-interleaving block, and output and the uniform buffer module of de-interleaving block connect
It connects, the output of uniform buffer module exports demodulation gain by internal interface.
The down conversion module includes orthogonal mixting circuit, low-pass filter circuit and digital controlled oscillation circuit, orthogonal mixing
The input of circuit is connected respectively with ADC input signals and digital controlled oscillation circuit, and orthogonal mixting circuit exports I, Q two paths of signals to low
Bandpass filter circuit, low-pass filter circuit export I, Q two paths of signals to decimal abstraction module, and the digital controlled oscillation circuit uses
Cordic algorithm.Digital controlled oscillation circuit is realized using cordic algorithm, is only consumed a small amount of register and adder resource, is not disappeared
RAM is consumed, resource loss, which is substantially negligible, to be disregarded.
The decimal abstraction module carries out small several times extraction to the baseband signal that down conversion module obtains, and exports signal sample
It is worth to thick frequency offset correction module.
Since signal bandwidth only has 180kHz or so after despreading, and highest Doppler shift reaches 3kHz, in some interference feelings
Under condition, frequency deviation may be outside transnormal phaselocked loop capture zone, so here by carrier synchronization partial resolution into " thick frequency deviation
Correction " and " fine frequency offset synchronization " two links.
The thick frequency offset correction module includes orthogonal mixting circuit, elimination modulation intelligence circuit, fft circuit, spectral line peak
It is worth search circuit, calculates frequency deviation circuit and digital controlled oscillation circuit, orthogonal mixting circuit is received from the output of decimal abstraction module
Signal, the output of orthogonal mixting circuit are connected respectively with narrow-band filtering module and elimination modulation intelligence circuit, eliminate modulation intelligence
The output of circuit is connected with fft circuit, and the output of fft circuit is connected with spectral line peak search circuit, spectral line peak search circuit
Output with calculate frequency deviation circuit be connected, calculating frequency deviation circuit output be connected with digital controlled oscillation circuit, digital controlled oscillation circuit
Output is connected with orthogonal mixting circuit.
Input signal is 4 times of symbol sampler rates, into 4 power computing modules, eliminates the modulation intelligence of QPSK, obtains single-tone
Frequency point information.By FFT and spectral line peak value searching, you can obtain coarse frequency offset information.Wherein the points of FFT use at 2048 points, can
To obtain sufficiently low residual frequency deviation, ensure the normal capture of fine frequency offset synchronization module.After correction once, subsequently FFT is obtained several times
To coarse frequency offset information approach, peak value is enough, then it is assumed that it is stable, without correcting again；Otherwise it is assumed that system step-out, again into
The thick frequency offset correction of row.
Since frequency deviation is larger, DDC, implementation be slightly broadband filtering, ensure signal spectrum it is without damage；In thick frequency deviation school
After the completion of just, then a narrow-band filtering is carried out, further filter out remaining out-of-band noise.The narrow-band filtering module be used for into
One step filters out remaining out-of-band noise.
Since the signal bandwidth of narrow band signal is smaller, without using balancing techniques such as SCFDE.
Bit synchronization uses Gardner algorithms, insensitive to a small amount of residual frequency deviation (according to 3kHz maximum frequency deviations,
4.5Mbaud/s or so baud rates are calculated, and residual frequency deviation is about 0.1% of chip rate or so), frequency synchronization module can be located at
Before.After input data carries out fractional times of interpolation extraction, the signal of 4 times of symbol sampler rates is obtained；4 times of sample value signals are carried out
Gardner bit timing estimation errors, obtain instantaneous error value, and after filtering out high-frequency noise by loop filter, driving NCO is generated
Timing interpolation enables and interpolated parameter；" Farrow timings interpolation " module uses farrow structures, and interpolation obtains accurate symbol
Determination point, eventually by output Buffer output；The Farrow structures are that a kind of efficient polynomial interpolation realizes structure.
The bit sync module include input buffer module, reg modules, Timing error estimate module, loop filter,
Digital controlled oscillation circuit, timing interpolation module, output buffer module and two shift registers, input the input of buffer module with it is narrow
Band filter module connects, and the output for inputting buffer module is connected with reg modules, and the output of reg modules is posted with one of displacement
Storage connects, and the output of this shift register is connected with timing interpolation module, the output all the way of timing interpolation module and another
Shift register connects, and the output of this shift register is connected with timing error module, the output of Timing error estimate module and
Loop filter connects, and the output of loop filter is connected with digital controlled oscillation circuit, in the output and timing of digital controlled oscillation circuit
Module connection is inserted, the another way of timing interpolation module is exported by exporting buffer module output data.
The fine frequency offset synchronization module include orthogonal mixting circuit, digital controlled oscillation circuit, phase error estimation and phase error circuit and
Loop filter circuit, orthogonal mixting circuit, digital controlled oscillation circuit, phase error estimation and phase error circuit and loop filter circuit composition number
Phaselocked loop, exterior I, the input of Q two-way are connected with bit sync module, and the output of orthogonal mixting circuit is electric with phase error estimation and phase error respectively
Road is connected with decoding/judging module, and the output of phase error estimation and phase error circuit is connected with loop filter circuit, loop filter circuit
Output is connected with digital controlled oscillation circuit, and the output of digital controlled oscillation circuit is connected with orthogonal mixting circuit.The numerical control vibration electricity
The realization on road uses DDS algorithms rather than cordic algorithms because in FPGA cordic logics sequential amount of delay compared with
Greatly, cause loop delay big, influence capturing frequency deviation ability, and DDS only has the delay of 1 to 3 clk, it is ensured that loop captures
Behavior and the performance of tracking behavior.
Decoding/the judging module uses Viterbi soft-decision algorithm, and the de-interleaving block is used to implement simply
Buffering read-write.
The uniform buffer module includes data buffering module, buffering capacity monitoring modular, loop filtering module and numerical control
Oscillation module, data buffering module receive input data and input clock, and output all the way and the buffering capacity of data buffering module are supervised
Survey module connection, the another way output output data of data buffering module, output and the loop filtering mould of buffering capacity monitoring modular
Block connects, and the output of loop filtering module is connected with numerical control oscillation module, the output all the way of numerical control oscillation module and data buffering
Module connects, the another way output clock signal of numerical control oscillation module.
The Receiver Module includes duplexer, transmitting terminal processing module, receiving terminal processing module and drive module,
The duplexer for sending and receiving data, the output of the transmitting terminal processing module is connected with duplexer, receiving terminal
The input of processing module is connected with duplexer, the output of drive module respectively with transmitting terminal processing module and receiving terminal processing module
Connection；
The drive module includes crystal oscillator, local oscillator, work(sub-module, two drive amplification modules and driver, local oscillator
Two-way input is connected respectively with crystal oscillator and SPI codes, and the output of local oscillator is connected with work(sub-module, the two-way output difference of work(sub-module
It is connected with two drive amplification modules, the output of two drive amplification modules is handled respectively with transmitting terminal processing module and receiving terminal
Module connects, and the output of driver is connected with transmitting terminal processing module, and the driver exports 5 parallel-by-bit control codes；
The transmitting terminal processing module is put including frequency mixing module, filter module, amplification module, numerical control attenuation module, drive
Module and power amplifier module, the input all the way of frequency mixing module is intermediate-freuqncy signal, in the another way input of frequency mixing module and drive module
The connection of one of drive amplification module, the output of frequency mixing module is connected with filter module, the output and amplification of filter module
Module connects, and the output of amplification module and the output of the driver of drive module are connected with numerical control attenuation module, numerical control attenuation
The output of module is connected with driving amplification module, and the output for driving amplification module is connected with power amplifier module, the output of power amplifier module and duplexer
Connection；
The receiving terminal processing module includes low noise amplification module, filter module, amplification module, frequency mixing module, filtering
Module and amplification module, the input of low noise amplification module are connected with duplexer, and output and the filter module of low noise amplification module connect
It connects, the output of filter module is connected with amplification module, the output of amplification module and another drive amplification module of drive module
Output be connected with frequency mixing module, the output of frequency mixing module is connected with filter module, and filter module is connected with amplification module, is put
Big module output signal.
The beneficial effects of the invention are as follows：（1）The signal of ADC inputs obtains baseband signal by down coversion, in down coversion
Digital controlled oscillation circuit is realized using cordic algorithm, only consumes a small amount of register and adder resource, does not consume RAM, resource
Loss, which is substantially negligible, to be disregarded；（2）Baseband signal carries out small several times extraction, obtains the signal sample of 4 times of chip rates, then
Matched filtering is carried out, the advantage of doing so is that the calculating beneficial to matched filtering coefficient；（3）Since signal bandwidth only has after despreading
180kHz or so, and highest Doppler shift reaches 3kHz, at certain interference situations, frequency deviation may transnormal phaselocked loop
Outside capture zone, so here by carrier synchronization partial resolution into " thick frequency offset correction " and " fine frequency offset synchronization " two links；（4）
Since frequency deviation is larger, DDC, implementation be slightly broadband filtering, ensure signal spectrum it is without damage；（5）It is complete in thick frequency offset correction
Cheng Hou, then a narrow-band filtering is carried out, further filter out remaining out-of-band noise；（6）The signal bandwidth of narrow band signal is smaller, no
The balancing techniques such as SCFDE are reused, it is cost-effective；（7）Bit information after judgement obtains the knot after error correction by channel decoding
Fruit, in order to support the precise time label of telemetering, demodulating data will be exported at the uniform velocity；（8）Due to front some, the present invention can fit
For it is a kind of can telemetering, remote control, number pass unmanned plane air-ground narrow-band communication system reception terminal, receive terminal include nobody
Machine terminal.
Description of the drawings
Fig. 1 is block diagram of the present invention；
Fig. 2 is FPGA function module structure chart；
Fig. 3 is down conversion module structure chart；
Fig. 4 is thick frequency offset correction function structure chart；
Fig. 5 is bit sync module structure chart；
Fig. 6 is Farrow structure diagrams；
Fig. 7 is fine frequency offset synchronization structure chart；
Fig. 8 is uniform buffer module structure chart；
Fig. 9 is radio frequency receiving block structural diagram.
Specific embodiment
Technical scheme is described in further detail below in conjunction with the accompanying drawings：As shown in Figure 1, one kind is for unmanned plane
The reception terminal of empty narrow-band communication system, it includes Receiver Module, intermediate frequency filtering module, ADC and FPGA, radio frequency receiving
Block receives the control signal from external signal of communication and from FPGA, output and the intermediate frequency filtering mould of Receiver Module
Block connects, and the output of intermediate frequency filtering module be connected with ADC, and the output of ADC is connected with FPGA, the clock control of FPGA export and
ADC connections, the gain control output of FPGA are connected with Receiver Module, and FPGA also passes through internal interface demodulated output data；
As shown in Fig. 2, the FPGA includes down conversion module, decimal abstraction module, thick frequency offset correction module, narrowband filter
Ripple module, bit sync module, fine frequency offset synchronization module, decoding/judging module, de-interleaving block and uniform buffer module, lower change
The input of frequency module is connected with ADC, and the output of down conversion module is connected with decimal abstraction module, the output of decimal abstraction module with
Thick frequency offset correction module connection, the output of thick frequency offset correction module are connected with narrow-band filtering module, the output of narrow-band filtering module
Be connected with bit sync module, the output of bit sync module is connected with fine frequency offset synchronization module, the output of fine frequency offset synchronization module with
Decoding/judging module connection, the output of decoding/judging module are connected with de-interleaving block, the output of de-interleaving block and at the uniform velocity
Buffer module connects, and the output of uniform buffer module exports demodulation gain by internal interface.
As shown in figure 3, the down conversion module includes orthogonal mixting circuit, low-pass filter circuit and numerical control vibration electricity
Road, the input of orthogonal mixting circuit are connected respectively with ADC input signals and digital controlled oscillation circuit, and orthogonal mixting circuit exports I, Q
Two paths of signals is to low-pass filter circuit, and low-pass filter circuit exports I, Q two paths of signals to decimal abstraction module, and the numerical control is shaken
It swings circuit and uses cordic algorithm.Digital controlled oscillation circuit is realized using cordic algorithm, only consumes a small amount of register and addition
Device resource does not consume RAM, and resource loss, which is substantially negligible, to be disregarded.Digital controlled oscillation circuit at the beginning, sets standard
160MHz intermediate frequencies mirror image (numerical frequency is 2 * pi * 3/10) frequency point., it is necessary to the thick of signal in acquisition procedure is de-spread
Slightly frequency deviation value scans for, so carrying " frequency point search parameter " input from despreading module here.
The decimal abstraction module carries out the baseband signal that down conversion module obtains small several times extraction, output output 4
The signal sample of times chip rate is to thick frequency offset correction module.
Since signal bandwidth only has 180kHz or so after despreading, and highest Doppler shift reaches 3kHz, in some interference feelings
Under condition, frequency deviation may be outside transnormal phaselocked loop capture zone, so here by carrier synchronization partial resolution into " thick frequency deviation
Correction " and " fine frequency offset synchronization " two links.
The thick frequency offset correction module includes orthogonal mixting circuit, elimination modulation intelligence circuit, fft circuit, spectral line peak
It is worth search circuit, calculates frequency deviation circuit and digital controlled oscillation circuit, orthogonal mixting circuit is received from the output of decimal abstraction module
Signal, the output of orthogonal mixting circuit are connected respectively with narrow-band filtering module and elimination modulation intelligence circuit, eliminate modulation intelligence
The output of circuit is connected with fft circuit, and the output of fft circuit is connected with spectral line peak search circuit, spectral line peak search circuit
Output with calculate frequency deviation circuit be connected, calculating frequency deviation circuit output be connected with digital controlled oscillation circuit, digital controlled oscillation circuit
Output is connected with orthogonal mixting circuit.
Since frequency deviation is larger, DDC, implementation be slightly broadband filtering, ensure signal spectrum it is without damage；In thick frequency deviation school
After the completion of just, then a narrow-band filtering is carried out, further filter out remaining out-of-band noise.The narrow-band filtering module be used for into
One step filters out remaining out-of-band noise.
Since the signal bandwidth of narrow band signal is smaller, without using balancing techniques such as SCFDE.
Bit synchronization uses Gardner algorithms, insensitive to a small amount of residual frequency deviation (according to 3kHz maximum frequency deviations,
4.5Mbaud/s or so baud rates are calculated, and residual frequency deviation is about 0.1% of chip rate or so), frequency synchronization module can be located at
Before.After input data carries out fractional times of interpolation extraction, the signal of 4 times of symbol sampler rates is obtained；4 times of sample value signals are carried out
Gardner bit timing estimation errors, obtain instantaneous error value, and after filtering out high-frequency noise by loop filter, driving NCO is generated
Timing interpolation enables and interpolated parameter；" Farrow timings interpolation " module uses farrow structures, and interpolation obtains accurate symbol
Determination point, eventually by output Buffer output；The Farrow structures are that a kind of efficient polynomial interpolation realizes structure.Institute
The bit sync module stated includes input buffer module, reg modules, Timing error estimate module, loop filter, numerical control vibration electricity
Road, timing interpolation module, output buffer module and two shift registers input the input of buffer module and narrow-band filtering module
Connection, the output for inputting buffer module are connected with reg modules, and the output of reg modules is connected with one of shift register, this
The output of shift register is connected with timing interpolation module, and output all the way and another shift register of timing interpolation module connect
It connects, the output of this shift register is connected with timing error module, and output and the loop filter of Timing error estimate module connect
It connects, the output of loop filter is connected with digital controlled oscillation circuit, and the output of digital controlled oscillation circuit is connected with timing interpolation module, fixed
When interpolation module another way export by exporting buffer module output data.
The fine frequency offset synchronization module include orthogonal mixting circuit, digital controlled oscillation circuit, phase error estimation and phase error circuit and
Loop filter circuit, orthogonal mixting circuit, digital controlled oscillation circuit, phase error estimation and phase error circuit and loop filter circuit composition number
Phaselocked loop, exterior I, the input of Q two-way are connected with bit sync module, and the output of orthogonal mixting circuit is electric with phase error estimation and phase error respectively
Road is connected with decoding/judging module, and the output of phase error estimation and phase error circuit is connected with loop filter circuit, loop filter circuit
Output is connected with digital controlled oscillation circuit, and the output of digital controlled oscillation circuit is connected with orthogonal mixting circuit.The numerical control vibration electricity
The realization on road uses DDS algorithms rather than cordic algorithms because in FPGA cordic logics sequential amount of delay compared with
Greatly, cause loop delay big, influence capturing frequency deviation ability, and DDS only has the delay of 1 to 3 clk, it is ensured that loop captures
Behavior and the performance of tracking behavior.
Decoding/the judging module uses Viterbi soft-decision algorithm, calls Xilinx official IPCORE.
The de-interleaving block is used to implement simple buffering read-write.
The uniform buffer module includes data buffering module, buffering capacity monitoring modular, loop filtering module and numerical control
Oscillation module, data buffering module receive input data and input clock, and output all the way and the buffering capacity of data buffering module are supervised
Survey module connection, the another way output output data of data buffering module, output and the loop filtering mould of buffering capacity monitoring modular
Block connects, and the output of loop filtering module is connected with numerical control oscillation module, the output all the way of numerical control oscillation module and data buffering
Module connects, the another way output clock signal of numerical control oscillation module.
The Receiver Module includes duplexer, transmitting terminal processing module, receiving terminal processing module and drive module,
The duplexer for sending and receiving data, the output of the transmitting terminal processing module is connected with duplexer, receiving terminal
The input of processing module is connected with duplexer, the output of drive module respectively with transmitting terminal processing module and receiving terminal processing module
Connection；
The drive module includes crystal oscillator, local oscillator, work(sub-module, two drive amplification modules and driver, local oscillator
Two-way input is connected respectively with crystal oscillator and SPI codes, and the output of local oscillator is connected with work(sub-module, the two-way output difference of work(sub-module
It is connected with two drive amplification modules, the output of two drive amplification modules is handled respectively with transmitting terminal processing module and receiving terminal
Module connects, and the output of driver is connected with transmitting terminal processing module, and the driver exports 5 parallel-by-bit control codes；
The transmitting terminal processing module is put including frequency mixing module, filter module, amplification module, numerical control attenuation module, drive
Module and power amplifier module, the input all the way of frequency mixing module is intermediate-freuqncy signal, in the another way input of frequency mixing module and drive module
The connection of one of drive amplification module, the output of frequency mixing module is connected with filter module, the output and amplification of filter module
Module connects, and the output of amplification module and the output of the driver of drive module are connected with numerical control attenuation module, numerical control attenuation
The output of module is connected with driving amplification module, and the output for driving amplification module is connected with power amplifier module, the output of power amplifier module and duplexer
Connection；
The receiving terminal processing module includes low noise amplification module, filter module, amplification module, frequency mixing module, filtering
Module and amplification module, the input of low noise amplification module are connected with duplexer, and output and the filter module of low noise amplification module connect
It connects, the output of filter module is connected with amplification module, the output of amplification module and another drive amplification module of drive module
Output be connected with frequency mixing module, the output of frequency mixing module is connected with filter module, and filter module is connected with amplification module, is put
Big module output signal.
In receiving channel, 1430MHz（Uplink remote signal）Signal amplifies again through low noise amplification post filtering, it is mixed to 70 ±
2MHz intermediate frequencies.It is exported after intermediate frequency is amplified, output power is -5dBm~0dBm.
Claims (1)
1. a kind of reception terminal for the air-ground narrow-band communication system of unmanned plane, it is characterised in that：It include Receiver Module,
Intermediate frequency filtering module, ADC and FPGA, Receiver Module receive the control letter from external signal of communication and from FPGA
Number, the output of Receiver Module is connected with intermediate frequency filtering module, and the output of intermediate frequency filtering module is connected with ADC, the output of ADC
It being connected with FPGA, the clock control output of FPGA is connected with ADC, and the gain control output of FPGA is connected with Receiver Module,
FPGA also passes through internal interface demodulated output data；
The FPGA includes down conversion module, decimal abstraction module, thick frequency offset correction module, narrow-band filtering module, bit synchronization
Module, fine frequency offset synchronization module, decoding/judging module, de-interleaving block and uniform buffer module, the input of down conversion module with
ADC connections, the output of down conversion module are connected with decimal abstraction module, the output of decimal abstraction module and thick frequency offset correction module
Connection, the output of thick frequency offset correction module are connected with narrow-band filtering module, and output and the bit sync module of narrow-band filtering module connect
It connects, the output of bit sync module is connected with fine frequency offset synchronization module, and output and the decoding/judging module of fine frequency offset synchronization module connect
It connects, the output of decoding/judging module is connected with de-interleaving block, and the output of de-interleaving block is connected with uniform buffer module, even
The output of fast buffer module exports demodulation gain by internal interface；Decoding/the judging module uses Viterbi soft-decision
Algorithm；
The down conversion module include the first orthogonal mixting circuit, low-pass filter circuit and the first digital controlled oscillation circuit, first
The input of orthogonal mixting circuit is connected respectively with ADC input signals and the first digital controlled oscillation circuit, and the first orthogonal mixting circuit is defeated
Go out I, Q two paths of signals to low-pass filter circuit, low-pass filter circuit exports I, Q two paths of signals to decimal abstraction module, described
First digital controlled oscillation circuit uses cordic algorithm；
The thick frequency offset correction module includes the second orthogonal mixting circuit, elimination modulation intelligence circuit, fft circuit, spectral line peak
It is worth search circuit, calculates frequency deviation circuit and the second digital controlled oscillation circuit, the second orthogonal mixting circuit is received extracts mould from decimal
The signal of block output, the output of the second orthogonal mixting circuit are connected respectively with narrow-band filtering module and elimination modulation intelligence circuit,
The output for eliminating modulation intelligence circuit is connected with fft circuit, and the output of fft circuit is connected with spectral line peak search circuit, spectral line
The output of peak search circuit is connected with calculating frequency deviation circuit, and the output and the second digital controlled oscillation circuit for calculating frequency deviation circuit connect
It connects, the output of the second digital controlled oscillation circuit is connected with orthogonal mixting circuit；
The bit sync module includes input buffer module, reg modules, Timing error estimate module, loop filter, the 3rd
Digital controlled oscillation circuit, timing interpolation module, output buffer module and two shift registers, input the input of buffer module with it is narrow
Band filter module connects, and the output for inputting buffer module is connected with reg modules, and the output of reg modules is posted with one of displacement
Storage connects, and the output of this shift register is connected with timing interpolation module, the output all the way of timing interpolation module and another
Shift register connects, and the output of this shift register is connected with timing error module, the output of Timing error estimate module and
Loop filter connects, and the output of loop filter is connected with the 3rd digital controlled oscillation circuit, the output of the 3rd digital controlled oscillation circuit
It is connected with timing interpolation module, the another way of timing interpolation module is exported by exporting buffer module output data；
The fine frequency offset synchronization module includes the 4th orthogonal mixting circuit, the 4th digital controlled oscillation circuit, phase error estimation and phase error electricity
Road and loop filter circuit, the 4th orthogonal mixting circuit, the 4th digital controlled oscillation circuit, phase error estimation and phase error circuit and loop filtering
Circuit forms digital phase-locked loop, and exterior I, the input of Q two-way are connected with bit sync module, the output difference of the 4th orthogonal mixting circuit
It is connected with phase error estimation and phase error circuit and decoding/judging module, output and the loop filter circuit of phase error estimation and phase error circuit connect
It connects, the output of loop filter circuit is connected with the 4th digital controlled oscillation circuit, and the output of the 4th digital controlled oscillation circuit is orthogonal with the 4th
Mixting circuit connects, and the 4th digital controlled oscillation circuit uses DDS algorithms；
The uniform buffer module includes data buffering module, buffering capacity monitoring modular, loop filtering module and the 5th numerical control
Oscillation module, data buffering module receive input data and input clock, and output all the way and the buffering capacity of data buffering module are supervised
Survey module connection, the another way output output data of data buffering module, output and the loop filtering mould of buffering capacity monitoring modular
Block connects, and the output of loop filtering module is connected with the 5th numerical control oscillation module, the output all the way of the 5th numerical control oscillation module and
Data buffering module connects, the another way output clock signal of the 5th numerical control oscillation module；
The Receiver Module includes duplexer, transmitting terminal processing module, receiving terminal processing module and drive module, described
Duplexer for sending and receiving data, the output of the transmitting terminal processing module is connected with duplexer, and receiving terminal is handled
The input of module is connected with duplexer, and the output of drive module connects respectively with transmitting terminal processing module and receiving terminal processing module
It connects；
The drive module includes crystal oscillator, local oscillator, work(sub-module, two drive amplification modules and driver, the two-way of local oscillator
Input is connected respectively with crystal oscillator and SPI codes, and the output of local oscillator is connected with work(sub-module, and the two-way of work(sub-module is exported respectively with two
The connection of a drive amplification module, the output of two drive amplification modules respectively with transmitting terminal processing module and receiving terminal processing module
Connection, the output of driver are connected with transmitting terminal processing module, and the driver exports 5 parallel-by-bit control codes；
The transmitting terminal processing module include frequency mixing module, the first filter module, the first amplification module, numerical control attenuation module,
Amplification module and power amplifier module are driven, the input all the way of frequency mixing module is intermediate-freuqncy signal, and the another way input of frequency mixing module is with driving mould
One of drive amplification module connection in the block, the output of frequency mixing module are connected with the first filter module, the first filter module
Output be connected with the first amplification module, the output of the first amplification module and the output of the driver of drive module decline with numerical control
Subtract module connection, the output of numerical control attenuation module is connected with driving amplification module, and the output for driving amplification module is connected with power amplifier module, power amplifier
The output of module is connected with duplexer；
The receiving terminal processing module include low noise amplification module, the second filter module, the second amplification module, frequency mixing module,
3rd filter module and the 3rd amplification module, the input of low noise amplification module are connected with duplexer, the output of low noise amplification module
Be connected with the second filter module, the output of the second filter module is connected with the second amplification module, the output of the second amplification module and
The output of another drive amplification module of drive module is connected with frequency mixing module, the output of frequency mixing module and the 3rd filtering mould
Block connects, and the 3rd filter module is connected with the 3rd amplification module, the 3rd amplification module output signal.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1786164A1 (en) * | 2005-11-10 | 2007-05-16 | Research In Motion Limited | Method and apparatus for communicating data upon multiple radio carriers |
| CN101267414A (en) * | 2007-03-12 | 2008-09-17 | 中国科学院上海微系统与信息技术研究所 | A flexible OFDM download communication system and its communication method |
| CN103905131A (en) * | 2014-03-11 | 2014-07-02 | 上海永畅信息科技有限公司 | Expressway vehicle sensing system and method based on space channel detection |
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2014
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1786164A1 (en) * | 2005-11-10 | 2007-05-16 | Research In Motion Limited | Method and apparatus for communicating data upon multiple radio carriers |
| CN101267414A (en) * | 2007-03-12 | 2008-09-17 | 中国科学院上海微系统与信息技术研究所 | A flexible OFDM download communication system and its communication method |
| CN103905131A (en) * | 2014-03-11 | 2014-07-02 | 上海永畅信息科技有限公司 | Expressway vehicle sensing system and method based on space channel detection |
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