CN104392980B - A kind of chip-packaging structure - Google Patents
A kind of chip-packaging structure Download PDFInfo
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- CN104392980B CN104392980B CN201410708119.4A CN201410708119A CN104392980B CN 104392980 B CN104392980 B CN 104392980B CN 201410708119 A CN201410708119 A CN 201410708119A CN 104392980 B CN104392980 B CN 104392980B
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Abstract
The present invention provides a kind of chip-packaging structures, including the first conductive layer, first chip is arranged on the first conductive layer, its input terminal is electrically connected with the first conductive layer, second conductive layer is arranged on the first chip, it is electrically connected with the output end of the first chip, second chip is arranged on the second conductive layer, its input terminal is electrically connected with the second conductive layer, third conductive layer is arranged on the second chip, it is electrically connected with its output end, first chip and the second chip are staggeredly stacked, in the first conductive layer, second conductive layer and third conduction interlayer form the first heat dissipation channel and the second heat dissipation channel.Chip-packaging structure of the present invention, it is simple for structure, multichannel multi-layer heat dissipation is formd by the first heat dissipation channel, second heat dissipation channel etc., improves the service life and reliability of device.
Description
Technical field
The present invention relates to chip encapsulation technology fields.Relate in particular to a kind of chip-packaging structure.
Background technique
It is many that the power electronics semiconductor device of discrete encapsulation is widely used in Switching Power Supply, inverter and motor driver etc.
More occasions.But discrete encapsulating structure not only increases the overall dimensions of device, also adds the distance of chip chamber, therefore discrete
The prefabricated conducting wire that the line of the power electronics semiconductor device of formula encapsulation often passes through pcb board is connected, but this will will increase electricity
The three-dimensional space that road occupies, is unfavorable for the miniaturization of power-supply system.
As " energy-saving and emission-reduction " are increased to fundamental state policy height by country, Energy Efficiency Standard is continuously improved, the hair of power device
Exhibition trend is: high-breakdown-voltage, low on-resistance, high current, elevated operating temperature, low switching losses and high switching speed.Base
It is developed in the power device of third generation semiconductor material, including chip material, encapsulation integrated technique and encapsulation critical material etc.
Cause the extensive concern including academia and industry.It is well known that the structure based on third generation semiconductor chip packaging is set
The collective effect of meter and various crucial encapsulating materials will be obviously improved the comprehensive performance of device.But both at home and abroad currently based on third
Mature wire bonding (wire bonding) technology encapsulation or similar wire are mostly used greatly for the chip of semiconductor
The deriving technology of bonding is realized.Such technology is primarily present encapsulating structure level complexity, and interface resistance is big and is unfavorable for dissipating
Heat, electrode contact surface product is small and contact resistance causes greatly device loss height, device to rely primarily on single channel heat dissipation so that the device longevity
The defects of ordering low and poor reliability.
Summary of the invention
For this purpose, existing technical problem to be solved by the present invention lies in semiconductor chip package in the prior art
Level is complicated, and interface resistance is big and is unfavorable for that heat dissipation, electrode contact surface product be small and contact resistance leads to greatly that device loss is high, device
It relies primarily on single channel to radiate so that the defects of device lifetime is low and poor reliability, to provide a kind of simple for structure, energy is more than enough
The chip-packaging structure of channel heat dissipation.
In order to solve the above technical problems, technical scheme is as follows:
The present invention provides a kind of chip-packaging structures, comprising:
First conductive layer；
First chip is arranged on first conductive layer, the input terminal of first chip and first conductive layer
Electrical connection；
Second conductive layer is arranged on first chip, is electrically connected with the output end of first chip；
Second chip, on the second conductive layer, input terminal and the second conductive layer of second chip are electrically connected for setting
It connects；
Third conductive layer is arranged on second chip, is electrically connected with the output end of second chip；
Wherein, first chip and second chip are staggeredly stacked, in first conductive layer, second conduction
Layer and the third conduction interlayer form the first heat dissipation channel and the second heat dissipation channel.
Chip-packaging structure of the present invention, the appearance of the outer surface of first conductive layer and the third conductive layer
Face is fin shape.
Chip-packaging structure of the present invention, second conductive layer are led beyond first conductive layer and the third
The marginal portion of electric layer is fin shape.
Chip-packaging structure of the present invention, further includes:
First insulating layer is covered in the outer surface of first conductive layer；
Second insulating layer is covered in the outer surface of the third conductive layer.
Multichip packaging structure of the present invention, further includes: the first conductive column, the control terminal electricity with first chip
Connection, extendes back through second conductive layer, second heat dissipation channel, the third conductive layer and the second insulating layer
Out, and with second conductive layer and the third conductive layer it keeps insulating；
Second conductive column is electrically connected with the control terminal of second chip, through the third conductive layer and described second
It is stretched out after insulating layer, and keeps insulating with the third conductive layer.
Chip-packaging structure of the present invention, first conductive column and second conductive layer and the third are conductive
It is had the gap between layer, insulating heat-conduction material is filled between the gap；
It is had the gap between second conductive column and the third conductive layer, insulating heat-conductive material is filled between the gap
Material.
Chip-packaging structure of the present invention, first conductive column are led with second conductive layer and the third
The outer surface that electric layer is in contact is coated with insulating heat-conduction material；
The outer surface that second conductive column is in contact with the third conductive layer is coated with insulating heat-conduction material.
Chip-packaging structure of the present invention, further includes:
First diode chip is located in first heat dissipation channel, and the anode of the first diode chip passes through institute
It states the second conductive layer to be electrically connected with the output end of first chip, the cathode of the first diode chip passes through described first
Conductive layer is electrically connected with the input terminal of first chip；
Second diode chip for backlight unit is located in second heat dissipation channel, and the anode of second diode chip for backlight unit passes through institute
It states third conductive layer to be electrically connected with the output end of second chip, the cathode of second diode chip for backlight unit passes through described second
Conductive layer is electrically connected with the input terminal of second chip.
Chip-packaging structure of the present invention is filled between first heat dissipation channel and second heat dissipation channel
Insulating heat-conduction material.
Chip-packaging structure of the present invention, first chip and second chip are controllable semiconductor chip.
The above technical solution of the present invention has the following advantages over the prior art:
The present invention provides a kind of chip-packaging structure, including the first conductive layer, the first chip is arranged in the first conductive layer
On, input terminal is electrically connected with the first conductive layer, and the second conductive layer is arranged on the first chip, the output end electricity with the first chip
Connection, the second chip are arranged on the second conductive layer, and input terminal is electrically connected with the second conductive layer, and third conductive layer is arranged the
It on two chips, is electrically connected with its output end, the first chip and the second chip are staggeredly stacked, in the first conductive layer, the second conductive layer
And third conduction interlayer forms the first heat dissipation channel and the second heat dissipation channel.Chip-packaging structure of the present invention, structure letter
It is clean, multi-channel cooling is formd by the first heat dissipation channel, second heat dissipation channel etc., improves the service life of device and reliable
Property.
Detailed description of the invention
In order to make the content of the present invention more clearly understood, it below according to specific embodiments of the present invention and combines
Attached drawing, the present invention is described in further detail, wherein
The schematic diagram of chip-packaging structure when Fig. 1 is chip exterior non-parallel diode；
The explosive view of chip-packaging structure when Fig. 2 is chip exterior non-parallel diode；
Fig. 3 is the circuit topology figure of three chip-packaging structure parallel connections；
Fig. 4 is the circuit topology figure of chip-packaging structure；
The schematic diagram of chip-packaging structure when Fig. 5 is chip exterior parallel diode；
The explosive view of chip-packaging structure when Fig. 6 is chip exterior parallel diode.
Appended drawing reference indicates in figure are as follows: the first conductive layer of 1-, the first chip of 2-, the second conductive layer of 3-, the second chip of 4-, 5-
Third conductive layer, the first heat dissipation channel of 6-, the second heat dissipation channel of 7-, the first insulating layer of 8-, 9- second insulating layer, 10- first are led
Electric column, the second conductive column of 11-, 12- first diode chip, the second diode chip for backlight unit of 13-, the input terminal of the first chip of 21-,
The output end of the first chip of 22-, the control terminal of the first chip of 23-, the input terminal of the second chip of 41-, the output of the second chip of 42-
End, the control terminal of the second chip of 43-.
Specific embodiment
A kind of chip-packaging structure is present embodiments provided, as shown in Figure 1 and Figure 2, comprising:
First conductive layer 1；
First chip 2 is arranged on first conductive layer 1, and the input terminal 21 of first chip 2 is led with described first
Electric layer 1 is electrically connected；
Second conductive layer 3 is arranged on first chip 2, is electrically connected with the output end 22 of first chip 2；
Second chip 4 is arranged on second conductive layer 3, the input terminal 41 and the second conductive layer of second chip 4
3 electrical connections；
Third conductive layer 5 is arranged on second chip 4, is electrically connected with the output end 42 of second chip 4；
Wherein, first chip 2 and second chip 4 are staggeredly stacked, in first conductive layer 1, described second
The first heat dissipation channel 6 and the second heat dissipation channel 7 are formed between conductive layer 3 and the third conductive layer 5.
Specifically, the first conductive layer 1, the second conductive layer 3, third conductive layer 5 can be layers of copper, or other to lead
The material of conductance heat, such as aluminium, the first conductive layer 1, the second conductive layer 3, third conductive layer 5, the first heat dissipation channel 6 and second
Heat dissipation channel 7 realizes the multichannel multi-layer heat dissipation of chip-packaging structure, achieves extraordinary heat dissipation effect.
Preferably, the outer surface of first conductive layer 1 and the outer surface of the third conductive layer 5 can be cooling fin shape
Shape.
Preferably, second conductive layer 3 exceeds the marginal portion of first conductive layer 1 and the third conductive layer 5
It can be fin shape.
Specifically, the shapes such as above-mentioned fin shape is including but not limited to needle-shaped, column, sheet or aliform, Ke Yijin
One step enhances the outer surface of the first conductive layer 1, the outer surface of third conductive layer 5 and the second conductive layer 3 and exceeds the first conductive layer 1
With the heat dissipation performance of the marginal portion of third conductive layer 5.
Preferably, chip-packaging structure described in the present embodiment can also include:
First insulating layer 8 is covered in the outer surface of first conductive layer 1；
Second insulating layer 9 is covered in the outer surface of the third conductive layer 5.
Specifically, the first insulating layer 8 and second insulating layer 9 can be covered in the first conduction by the way of spraying or plating
The outer surface of layer 1 and third conductive layer 5.
Preferably, can tile multiple chip-packaging structures, conductive by first between adjacent chip-packaging structure
Layer 1 and the second conductive layer 3 are electrically connected, and the input, output end of two adjacent the first chips 2 can be made to share, be not necessarily to
Increase the parallel connection that extra conducting wire is achieved that two adjacent the first chips 2；By adjacent between each chip-packaging structure
The electrical contact of second conductive layer 3 and third conductive layer 4 can make the input, output end of two adjacent the second chips 4 total
With the parallel connection for being achieved that two adjacent the second chips 4 without increasing extra conducting wire.
It is of course also possible to the area of the first conductive layer 1 and third conductive layer 5 be increased, chip package knot adjacent in this way
Will only have the first conductive layer 1 and third conductive layer 5 to be electrically connected between structure, and keep insulation between the second conductive layer 3, thus real
The parallel connection between multiple chip-packaging structures is showed.
Circuit topology figure Fig. 3 in parallel between three chip-packaging structures, can be applied to current inverter common three
Phase bridge inverter main circuit.It can be seen that the first conductive layer 1 electrical connection in three chip-packaging structures, so that the first chip 2
Input terminal (collector) shares, and the third conductive layer 5 in three chip-packaging structures is electrically connected, so that the output of the second chip 4
(emitter) is held to share, the conducting wire without increasing extra can realize the parallel connection between three chip-packaging structures.
Preferably, multichip packaging structure described in the present embodiment can also include: the first conductive column 10, with described
The control terminal 23 of one chip 2 is electrically connected, through second conductive layer 3, second heat dissipation channel 7, the third conductive layer 5 with
And it is stretched out after the second insulating layer 9, and keep insulating with second conductive layer 3 and the third conductive layer 5；
Second conductive column 11 is electrically connected with the control terminal 43 of second chip 4, through the third conductive layer 5 and institute
It is stretched out after stating second insulating layer 9, and keeps insulating with the third conductive layer 5.
Specifically, first can be controlled by the first conductive column 10 to 23 input control signal of control terminal of the first chip 2
The starting or closing of chip 2 can be controlled by the second conductive column 11 to 43 input control signal of control terminal of the second chip 4
The starting or closing for making the second chip 4 realize the time-sharing multiplex to the first chip 2 and the second chip 4.
Optionally, it is had the gap between first conductive column 10 and second conductive layer 3 and the third conductive layer 5,
Insulating heat-conduction material is filled between the gap；
It is had the gap between second conductive column 11 and the third conductive layer 5, insulating heat-conductive is filled between the gap
Material.
Specifically, by being filled between the gap in the channel of the first conductive column 10 and the second conductive layer 3, third conductive layer 5
Insulating heat-conduction material can also make the while ensure that the first conductive column and the second conductive layer 3, third conductive layer 5 insulate
One conductive column 10 has good thermal diffusivity, is conducive to device and keeps good performance.By the second conductive column 11 with it is described
Insulating heat-conduction material is filled between the gap in the channel of third conductive layer 5 also can achieve identical beneficial effect.
As another optional mode, first conductive column 10 is led with second conductive layer 3 and the third
The outer surface that electric layer 5 is in contact can be coated with insulating heat-conduction material, second conductive column 11 and 5 phase of third conductive layer
The outer surface of contact can be coated with insulating heat-conduction material.Equally it can ensure that the first conductive column 10 and second is led while insulation
Electric column 11 has good thermal diffusivity.
Preferably, first chip 2 and second chip 4 are controllable semiconductor chip.
Specifically, controllable semiconductor chip includes metal-oxide-semiconductor chip, igbt chip, thyristor chip, triode chip etc..
First chip 2 and second chip 4 can be same controllable semiconductor chip, or not of the same race controllably partly to lead
Body chip.By taking triode chip and metal-oxide-semiconductor chip as an example, when first chip 2 and/or second chip 4 are triode
When chip, the base stage of chip is control terminal, and the collector of chip is input terminal, and the emitter of chip is output end；When
When first chip 2 and/or second chip 4 are metal-oxide-semiconductor chip, the grid of chip is control terminal, the source electrode of chip
As input terminal, the drain electrode of chip are output end.
Preferably, insulating heat-conductive material can be filled between first heat dissipation channel 6 and second heat dissipation channel 7
Material.Further enhance the heat dissipation performance of the first heat dissipation channel 6 and the second heat dissipation channel 7.
Fig. 4 is the circuit topology figure of said chip encapsulating structure, be can see in conjunction with Fig. 1, Fig. 2, and electric current is conductive from first
Layer 1 flows into, and the input terminal 21 (collector D) of the first chip 2, the output end 22 through the first chip 2 are flowed into through the first conductive layer 1
(emitter S) output flows into the input terminal 41 (collector D) of the second chip 4 through the second conductive layer 3 to the second conductive layer 3, through the
The output end 42 (emitter S) of two chips 4 flows out to third conductive layer 5, and electric current is drawn, and realizes the first chip 2 and second
The series connection of chip 4.
Preferably, the chip-packaging structure can also include: as shown in Figure 5, Figure 6
First diode chip 12 is located in first heat dissipation channel 6, and the anode of the first diode chip 12 is logical
It crosses second conductive layer 3 to be electrically connected with the output end 22 of first chip 2, the cathode of the first diode chip 12 is logical
First conductive layer 1 is crossed to be electrically connected with the input terminal 21 of first chip 2；
Second diode chip for backlight unit 13 is located in second heat dissipation channel 7, and the anode of second diode chip for backlight unit 13 is logical
It crosses the third conductive layer 5 to be electrically connected with the output end 42 of second chip 4, the cathode of second diode chip for backlight unit 13 is logical
Second conductive layer 3 is crossed to be electrically connected with the input terminal 41 of second chip 4.
Specifically, if there is no integrated diode in chip, chip can be protected with external diode chip for backlight unit, if
In chip when integrated diode, it can be improved with external high-performance diode chip for backlight unit diode is protected or reduced to chip
Switching loss.
As shown in figure 4, in conjunction with Fig. 5 and Fig. 6, it can be seen that the anode of first diode chip 12 passes through the second conductive layer 3
It is electrically connected with the output end 22 (emitter S) of the first chip 2, the cathode of first diode chip 12 passes through first conductive layer
1 is electrically connected with the input terminal 21 (collector D) of first chip 2；The anode of second diode chip for backlight unit 13 passes through the third
Conductive layer 5 is electrically connected with the output end 42 (emitter S) of second chip 4, and the cathode of second diode chip for backlight unit 13 is logical
Second conductive layer 3 is crossed to be electrically connected with the input terminal 41 (collector D) of second chip 4.
Chip-packaging structure described in the present embodiment, it is simple for structure, pass through the first heat dissipation channel 6, the second heat dissipation channel 7,
One insulating layer 8, second insulating layer 9 etc. form multi-channel cooling, improve the service life and reliability of device.
Obviously, the above embodiments are merely examples for clarifying the description, and does not limit the embodiments.It is right
For those of ordinary skill in the art, can also make on the basis of the above description it is other it is various forms of variation or
It changes.There is no necessity and possibility to exhaust all the enbodiments.And it is extended from this it is obvious variation or
It changes still within the protection scope of the invention.
Claims (9)
1. a kind of chip-packaging structure characterized by comprising
First conductive layer (1)；
First chip (2) is arranged on first conductive layer (1), the input terminal (21) of first chip (2) and described the
One conductive layer (1) electrical connection；
Second conductive layer (3) is arranged on first chip (2), is electrically connected with the output end (22) of first chip (2)
It connects；
Second chip (4) is arranged on second conductive layer (3), and the input terminal (41) of second chip (4) is led with second
Electric layer (3) electrical connection；
Third conductive layer (5) is arranged on second chip (4), is electrically connected with the output end (42) of second chip (4)
It connects；
Wherein, first chip (1) and second chip (2) are staggeredly stacked, in first conductive layer (1) and described the
The first heat dissipation channel (6) are formed between two conductive layers (3), are formed between second conductive layer (3) and the third conductive layer (5)
Second heat dissipation channel (7), first heat dissipation channel (6) are located at below second chip (4), second heat dissipation channel
(7) it is located above first chip (2), and is filled out between first heat dissipation channel (6) and second heat dissipation channel (7)
Filled with insulating heat-conduction material.
2. chip-packaging structure according to claim 1, which is characterized in that the outer surface of first conductive layer (1) and
The outer surface of the third conductive layer (5) is fin shape.
3. chip-packaging structure according to claim 1, which is characterized in that second conductive layer (3) is beyond described the
The marginal portion of one conductive layer (1) and the third conductive layer (5) is fin shape.
4. chip-packaging structure according to claim 1, which is characterized in that further include:
First insulating layer (8) is covered in the outer surface of first conductive layer (1)；
Second insulating layer (9) is covered in the outer surface of the third conductive layer (5).
5. chip-packaging structure according to claim 4, which is characterized in that further include: the first conductive column (10), and it is described
The control terminal (23) of first chip (2) is electrically connected, through second conductive layer (3), second heat dissipation channel (7), described the
Three conductive layers (5) and the second insulating layer (9) are stretched out afterwards, and with second conductive layer (3) and the third conductive layer
(5) insulation is kept；
Second conductive column (11) is electrically connected with the control terminal (43) of second chip (4), through the third conductive layer (5) with
And the second insulating layer (9) is stretched out afterwards, and keeps insulating with the third conductive layer (5).
6. chip-packaging structure according to claim 5, which is characterized in that first conductive column (10) and described second
It is had the gap between conductive layer (3) and the third conductive layer (5), insulating heat-conduction material is filled between the gap；
It is had the gap between second conductive column (11) and the third conductive layer (5), insulating heat-conductive is filled between the gap
Material.
7. chip-packaging structure according to claim 5, which is characterized in that first conductive column (10) and described second
The outer surface that conductive layer (3) and the third conductive layer (5) are in contact is coated with insulating heat-conduction material；
The outer surface that second conductive column (11) is in contact with the third conductive layer (5) is coated with insulating heat-conduction material.
8. chip-packaging structure according to claim 1, which is characterized in that further include:
First diode chip (12) is located in first heat dissipation channel (6), the anode of the first diode chip (12)
It is electrically connected by second conductive layer (3) with the output end (22) of first chip (2), the first diode chip
(12) cathode is electrically connected by first conductive layer (1) with the input terminal (21) of first chip (2)；
Second diode chip for backlight unit (13) is located in second heat dissipation channel (7), the anode of second diode chip for backlight unit (13)
It is electrically connected by the third conductive layer (5) with the output end (42) of second chip (4), second diode chip for backlight unit
(13) cathode is electrically connected by second conductive layer (3) with the input terminal (41) of second chip (4).
9. chip-packaging structure according to claim 1, which is characterized in that first chip (2) and second core
Piece (4) is controllable semiconductor chip.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103872027A (en) * | 2012-12-10 | 2014-06-18 | 财团法人工业技术研究院 | Stack type power element module |
| CN204204849U (en) * | 2014-11-27 | 2015-03-11 | 深圳先进技术研究院 | A kind of chip-packaging structure |
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| US9147649B2 (en) * | 2008-01-24 | 2015-09-29 | Infineon Technologies Ag | Multi-chip module |
| JP2013225622A (en) * | 2012-04-23 | 2013-10-31 | Jtekt Corp | Multilayer circuit board for motor control |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103872027A (en) * | 2012-12-10 | 2014-06-18 | 财团法人工业技术研究院 | Stack type power element module |
| CN204204849U (en) * | 2014-11-27 | 2015-03-11 | 深圳先进技术研究院 | A kind of chip-packaging structure |
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