CN104391818A - EtherCAT dual-network data reading and writing system and method thereof - Google Patents
EtherCAT dual-network data reading and writing system and method thereof Download PDFInfo
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Abstract
The invention relates to an EtherCAT dual-network data reading and writing system and a method thereof, wherein the system comprises an asynchronous parallel bus interface module, a data cache region, an EtherCAT reading and writing control module, a configuration information module and an interruption pulse synthesis module; the data cache region comprises an A-network data cache region and a B-network data cache region; the system is connected with a master control chip and an ESC chip respectively; the method comprises a starting method, an EtherCAT data reading method and an EtherCAT data writing method. The EtherCAT dual-network data reading and writing system and the method thereof improve the reliability of communication and the real time nature of the whole master control system. The EtherCAT dual-network data reading and writing system and the method thereof avoid the problem that the master control chip cannot further respond to an ET1100 interruption signal of the ESC chip due to losing a falling edge of the interruption signal once.
Description
Technical field
The present invention relates to a kind of two network data read-write system, specifically relate to the two network data read-write system of a kind of EtherCAT and method thereof.
Background technology
EtherCAT is by a kind of real-time industrial ethernet field bus technique based on standard ethernet technology, developed by German Bei Fu company at first, it has, and transmission capacity is large, transmission speed is fast, real-time is high, realize the features such as cost is low, topological structure is flexible, in recent years, EtherCAT technology is widely used in field of industrial automation control.Along with the continuous progress of technology, the real-time control system of the single EtherCAT network of current employing, its reliability has reached very high level, most of scale and the little Industry Control requirement of risk can be met completely, but be also nowhere near for part high-risk, high value, large-scale Industry Control, especially in fields such as D.C. high voltage transmission, sophisticated semiconductor manufactures, owing to being subject to the interference of the factor such as severe site environment, longer transmission range, may be there is unpredictable mistake in EtherCAT network, thus cause serious consequence.In order to strengthen the fault-tolerant ability of EtherCAT network, improve the reliability of communication, common way is the design adopting two redundant network.
EtherCAT network adopts the communication structure of master-slave mode, by the main website net control cycle, send downlink message, all slave stations of data frames traverse, each from standing in Frame through out-of-date, carry out process frames of data by special ESC chip (EtherCAT slave station control chip).Main control chip (as DSP, ARM etc.) only needs to be connected with the PDI interface (process data interface) of ESC chip, read/write data is carried out by asynchronous parallel bus or spi bus, can with other slave station real-time Communication for Power, without the need to the encoding-decoding process of complexity.
But, by main control chip and ESC chip is direct-connected apply time, some problems can be there are, be illustrated for this conventional ESC chip of ET1100: 1, each network cycle of ET1100 can the look-at-me of output low level, main control chip generally starts read/write network data by the negative edge detecting this look-at-me, and finally, main control chip also needs a particular address read/write number to ET1100, the look-at-me of ET1100 could be set to high level, remove this look-at-me.If main control chip does not have the timely particular address read/write number to ET1100, then main control chip is likely because the negative edge of this look-at-me cannot be detected and suspension; 2, the PDI interface rate of ET1100 is generally hundreds of nanosecond just read/writable 16 bit data, more a lot of slowly than main control chip tens nanosecond read/write 16 bit data, therefore, need ceaselessly to wait for during the direct read/write ET1100 of main control chip, when the data transmitted are more, the bus of main control chip can be taken for a long time, thus affects the real-time of control system; When 3, adopting the design of two redundancy EtherCAT network, main control chip can be increased further in the expense of communication aspects, the real-time of control system entirety is declined.
Summary of the invention
For the deficiencies in the prior art, the invention provides the two network data read-write system of a kind of EtherCAT and method thereof, be added between main control chip and two ESC chips, two ESC chips are connected into EtherCAT network (A net) and EtherCAT network (B net) respectively, two networks are for subsequent use each other, and the data of transmission are identical.The present invention specifically comprises following functional module:
1, asynchronous parallel bus interface module, for the read/write timing conversion of main control chip to FPGA being become the inner read/write sequential of FPGA, this module interface speed is fast, without the need to waiting for during main control chip read/write internal data of the present invention.During main control chip read data, asynchronous parallel bus interface module is different according to address, and the data of buffer memory in dual port RAM 2 module or dual port RAM 4 module are transferred to main control chip; When main control chip writes data, asynchronous parallel bus interface module is different according to address, by deposit data to configuration information module or be stored in dual port RAM 1 module and dual port RAM 3 module simultaneously;
2, A network data buffer area, comprises dual port RAM 2 module and adopts dual port RAM 1 module of ping-pang storage.Dual port RAM 2 module is used for buffer memory ESC chip ET1100 (A net) and downloads from EtherCAT network (A net) and need to be sent to the download area data of main control chip; Adopt dual port RAM 1 module of ping-pang storage be used for buffer memory main control chip be sent to ESC chip ET1100 (A net) and need to upload to EtherCAT network (A net) upload district's data, dual port RAM 1 module comprises dual port RAM 1_0 and dual port RAM 1_1 two parts, and what alternately store this and last time uploads district's data;
3, EtherCAT Read-write Catrol (A net) module, for passing through asynchronous parallel bus, according to the data segment first address stored in configuration information module and data segment, length, read/write operation is carried out to ESC chip ET1100 (A net), download area data reading is also stored in dual port RAM 2 module in order successively, then the district's data of uploading in dual port RAM 1 module of ping-pang storage will be adopted to write successively in order in ESC chip ET1100 (A net).After EtherCAT Read-write Catrol (A net) module runs through download area data, a pulse signal can be exported to interruption pulse synthesis module, write after uploading district's data, the look-at-me of ESC chip ET1100 (A net) can be removed;
4, configuration information module, for depositing the configuration information of main control chip write, configuration information comprises: the data segment start address of download area and data segment, length, the data segment start address uploading district and data segment, length and startup command word in ESC chip ET1100;
5, interruption pulse synthesis module, pulse signal for two EtherCAT Read-write Catrol modules being exported synthesizes an interruption pulse, and send to main control chip, make main control chip enter interrupt service routine, then from dual port RAM 2 module and dual port RAM 4 module, read up-to-date EtherCAT network data;
6, B network data buffer area, comprises dual port RAM 4 module and adopts dual port RAM 3 module of ping-pang storage.Dual port RAM 4 module is used for buffer memory ESC chip ET1100 (B net) and downloads from EtherCAT network (B net) and need to be sent to the download area data of main control chip; Adopt dual port RAM 3 module of ping-pang storage be used for buffer memory main control chip be sent to ESC chip ET1100 (B net) and need to upload to EtherCAT network (B net) upload district's data, dual port RAM 3 module comprises dual port RAM 3_0 and dual port RAM 3_1 two parts, and what alternately store this and last time uploads district's data;
7, EtherCAT Read-write Catrol (B net) module, for passing through asynchronous parallel bus, according to the data segment first address stored in configuration information module and data segment, length, read/write operation is carried out to ESC chip ET1100 (B net), download area data reading is also stored in dual port RAM 4 module in order successively, then the district's data of uploading in dual port RAM 3 module of ping-pang storage will be adopted to write successively in order in ESC chip ET1100 (B net).After EtherCAT Read-write Catrol (B net) module runs through download area data, a pulse signal can be exported to interruption pulse synthesis module, write after uploading district's data, the look-at-me of ESC chip ET1100 (B net) can be removed.
The object of the invention is to adopt following technical proposals to realize:
The two network data read-write system of a kind of EtherCAT, its improvements are, described system comprises asynchronous parallel bus interface module, data buffer area, EtherCAT Read-write Catrol module, configuration information module and interruption pulse synthesis module;
Described data buffer area comprises A network data buffer area and B network data buffer area;
Described system is connected with main control chip and ESC chip respectively;
Described asynchronous parallel bus interface module, data buffer area are connected successively with EtherCAT Read-write Catrol module;
Described asynchronous parallel bus interface module, configuration information module are connected successively with EtherCAT Read-write Catrol module;
Described asynchronous parallel bus interface module, interruption pulse synthesis module are connected successively with EtherCAT Read-write Catrol module.
Preferably, described A network data buffer area comprises dual port RAM 2 module and adopts dual port RAM 1 module of ping-pang storage; Described dual port RAM 1 module comprises dual port RAM 1_0 and dual port RAM 1_1 two parts.
Preferably, described B network data buffer area comprises dual port RAM 4 module and adopts dual port RAM 3 module of ping-pang storage; Described dual port RAM 3 module comprises dual port RAM 3_0 and dual port RAM 3_1 two parts.
Preferably, described asynchronous parallel bus interface module is externally connected with the bus interface of main control chip, is internally connected with dual port RAM module, configuration information module and interruption pulse synthesis module.
Preferably, the bus interface that described EtherCAT Read-write Catrol A net module is externally netted with ESC chip ET1100A is connected, internally with dual port RAM 2 module, adopt dual port RAM 1 module of ping-pang storage, configuration information module and interruption pulse synthesis module to be connected.
Preferably, the bus interface that described EtherCAT Read-write Catrol B net module is externally netted with ESC chip ET1100B is connected, internally with dual port RAM 4 module, adopt dual port RAM 3 module of ping-pang storage, configuration information module and interruption pulse synthesis module to be connected.
The present invention is based on the two network data reading/writing method of a kind of EtherCAT that another object provides, its improvements are, described method comprises starting method, read EtherCAT data method and write EtherCAT data method.
Preferably, described starting method comprises
(8.1) after FPGA powers on, EtherCAT Read-write Catrol module carries out initial configuration to ESC chip ET1100, after completing, waits for the startup command word that main control chip issues;
(8.2) main control chip is by asynchronous parallel bus interface module, by the data segment first address of download area and data segment, length and data segment first address and the data segment, length write configuration information module of uploading district;
(8.3) main control chip is by startup command word write configuration information module;
(8.4) after EtherCAT Read-write Catrol module receives the startup command word in configuration information module, startup optimization.
Preferably, read EtherCAT data method described in comprise
(9.1) EtherCAT Read-write Catrol module waits for the low level look-at-me that ESC chip ET1100 exports;
(9.2), after receiving low level look-at-me, EtherCAT Read-write Catrol module, according to the data segment first address of download area in configuration information module and data segment, length, reads data from ESC chip ET1100;
(9.3) EtherCAT Read-write Catrol A net module by read download area data stored in dual port RAM 2 module, EtherCAT Read-write Catrol B net module by read download area data stored in dual port RAM 4 module;
(9.4), after running through data, EtherCAT Read-write Catrol module exports a pulse signal to interruption pulse synthesis module;
(9.5), after pulse signal synthesizes by interruption pulse synthesis module, an interruption pulse is exported to main control chip;
(9.6) after main control chip receives interruption pulse, by asynchronous parallel bus interface module, from dual port RAM 2 module and dual port RAM 4 module, read EtherCAT data, and select the cumulative data segment that word is continuous, School Affairs is correct to use as valid data.
Preferably, write EtherCAT data method described in comprise
(10.1), after EtherCAT Read-write Catrol module runs through download area data, the flow process writing EtherCAT data is started immediately; EtherCAT Read-write Catrol A net module writes ESC chip ET1100A net by adopting the district's data of uploading in dual port RAM 1 module of ping-pang storage, and EtherCAT Read-write Catrol B net module writes ESC chip ET1100B net by adopting the district's data of uploading in dual port RAM 3 module of ping-pang storage;
(10.2) main control chip receives and after processing and uploading district's data, by asynchronous parallel bus interface module, writes in dual port RAM 1 module and dual port RAM 3 module by needing the data uploading to EtherCAT network simultaneously;
(10.3), after EtherCAT Read-write Catrol module writes data, the EtherCAT look-at-me of ESC chip ET1100 is removed.
Preferably, described EtherCAT Read-write Catrol controls read/write data flow process by state machine, and state machine comprises initialization ESC chip ET1100, waits for startup command, waits for ET1100 look-at-me, reads the EtherCAT data of download area, has sent the pulse signal of read data, writes the EtherCAT data and removing ET1100 look-at-me 7 kinds of states that pass district.
Compared with the prior art, beneficial effect of the present invention is:
1, the present invention adopts the design of two redundancy EtherCAT network, can strengthen the fault-tolerant ability of EtherCAT network, improve the reliability of communication;
2, the present invention utilizes the features such as fast, the configurable pin of FPGA travelling speed is many, energy parallel processing, simultaneously to two panels ESC chip ET1100 read/write data, and by data stored in the dual port RAM in FPGA sheet, data are transmitted by high-speed asynchronous parallel bus interface and main control chip, therefore the stand-by period of main control chip bus can significantly be shortened, reduce the expense of main control chip in communication aspects, improve the real-time of master control system entirety;
3, the present invention starts the flow process of read/write EtherCAT network data according to the low level look-at-me that ESC chip ET1100 exports, just automatically can remove the look-at-me of ESC chip ET1100 after having operated, and wait for that next cycle low level look-at-me triggers again.Avoid main control chip because of lose a look-at-me negative edge after, again cannot respond the problem of ESC chip ET1100 look-at-me.
Accompanying drawing explanation
Fig. 1 is the two network data read-write system structural drawing of a kind of EtherCAT provided by the invention.
Fig. 2 is the operational scheme schematic diagram of EtherCAT Read-write Catrol module provided by the invention.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in further detail.
As shown in Figure 1, the invention provides the two network data read-write system of a kind of EtherCAT based on FPGA, FPGA selects the Spartan series of xilinx company, inner with programmable Block RAM.That main control chip is selected is the DSP of TI company C2000 series, supports 16 bit data bus; The ET1100 chip of the Shi Bei good fortune company of ESC chip selection.Be connected with the bus interface of main control chip, ESC chip ET1100 (A net) and ESC chip ET1100 (B net) respectively by FPGA, address bus and data bus are 16.
FPGA inner function module of the present invention is specific as follows:
Asynchronous parallel bus interface module; Adopt dual port RAM 1 module of ping-pang storage; Dual port RAM 2 module; EtherCAT Read-write Catrol (A net) module; Configuration information module; Adopt dual port RAM 3 module of ping-pang storage; Dual port RAM 4 module; EtherCAT Read-write Catrol (B net) module.Asynchronous parallel bus interface module is externally connected with the bus interface of main control chip, is internally connected with all dual port RAM modules, configuration information module and interruption pulse synthesis module.EtherCAT Read-write Catrol (A net) module is externally connected with the bus interface of ESC chip ET1100 (A net), internally with dual port RAM 2 module, adopt dual port RAM 1 module of ping-pang storage, configuration information module and interruption pulse synthesis module to be connected.EtherCAT Read-write Catrol (B net) module is externally connected with the bus interface of ESC chip ET1100 (B net), internally with dual port RAM 4 module, adopt dual port RAM 3 module of ping-pang storage, configuration information module and interruption pulse synthesis module to be connected.Below the principle of work of each module is described in detail:
1, asynchronous parallel bus interface module detects the read/write data signal that main control chip sends all the time, if read signal, then according to the address that main control chip exports, the download area data of appropriate address in dual port RAM 2 or dual port RAM 4 is passed to main control chip; If write signal, and the address that main control chip exports is the address of configuration information, just data is write configuration information module, if upload the address of district's data, then data is write the appropriate address in dual port RAM 1 and dual port RAM 3 module simultaneously; Asynchronous parallel bus interface module will upload district's data write dual port RAM 1_0 or dual port RAM 1_1 according to the ping-pang storage zone bit of dual port RAM 1 module, when ping-pang storage zone bit is 0, write dual port RAM 1_0, when ping-pang storage zone bit is 1, write dual port RAM 1_1; Asynchronous parallel bus interface module will upload district's data write dual port RAM 3_0 or dual port RAM 3_1 according to the ping-pang storage zone bit of dual port RAM 3 module, when ping-pang storage zone bit is 0, write dual port RAM 3_0, when ping-pang storage zone bit is 1, write dual port RAM 3_1;
2, dual port RAM 1 module of ping-pang storage is adopted to be made up of the Block RAM of FPGA inside, the total hop count of data can uploaded due to each ESC chip ET1100 is at most 7 sections, every section of maximum 256 words, therefore configure dual port RAM 1_0 and the two-part capacity of dual port RAM 1_1 is 4KB.Asynchronous parallel bus interface module can carry out read/write operation to dual port RAM 1 module, but EtherCAT Read-write Catrol (A net) module can only carry out read operation to dual port RAM 1 module.Dual port RAM 1 inside modules has a ping-pang storage zone bit, its function is: when ping-pang storage zone bit is 0, asynchronous parallel bus interface module can to dual port RAM 1_0 read/write data, and EtherCAT Read-write Catrol (A net) module can only to dual port RAM 1_1 read data; When ping-pang storage zone bit is 1, asynchronous parallel bus interface module can to dual port RAM 1_1 read/write data, and EtherCAT Read-write Catrol (A net) module can only to dual port RAM 1_0 read data; Ping-pang storage zone bit all writes last data at asynchronous parallel bus interface module at every turn, and EtherCAT Read-write Catrol (A net) module overturns after running through last data simultaneously;
3, dual port RAM 2 module is made up of the Block RAM of FPGA inside, and because the total hop count of the Downloadable data of each ESC chip ET1100 is at most 7 sections, every section of maximum 256 words, the capacity therefore configuring dual port RAM 2 module is 4KB.Asynchronous parallel bus interface module can only carry out read operation to dual port RAM 2 module, and EtherCAT Read-write Catrol (A net) module can only carry out write operation to dual port RAM 2 module;
4, EtherCAT Read-write Catrol (A net) module and EtherCAT Read-write Catrol (B net) module are all control read/write data flow process by state machine (as shown in Figure 2), state machine has 6 kinds of states, comprising: 1. initialization ESC chip ET1100; 2. startup command is waited for; 3. ET1100 look-at-me is waited for; 4. the EtherCAT data of download area are read; 5. the pulse signal of read data has been sent; 6. the EtherCAT data passing district are write; 7. ET1100 look-at-me is removed.1. jumping to state condition 2. by state is, has completed ESC chip ET1100 initialize flow; 2. jumping to state condition 3. by state is that main control chip is written with startup command word to configuration information module; By state, 3. state condition is 2. returned in redirect is the startup command word that main control chip has cancelled in configuration information module; 3. jumping to state condition 4. by state is the low level look-at-me detecting that ESC chip ET1100 exports; 4. jumping to state condition 5. by state is according to the data segment first address stored in configuration information module and data segment, length, reads all EtherCAT download areas data from ESC chip ET1100; 5. jumping to state condition 6. by state is sent to interruption pulse synthesis module the pulse signal completing read data; 6. jumping to state condition 7. by state is all EtherCAT have been uploaded district's data to write ESC chip ET1100; 7. jumping to state condition 3. by state is the 0x1000 address of having read an ESC chip ET1100, and the look-at-me that ESC chip ET1100 exports reverts to high level;
5, configuration information module is made up of the distributed RAM of FPGA inside, because each ESC chip ET1100 allows the total hop count of data segment of read/write to be at most 7 sections, every section of maximum 256 words, therefore configuration information module needs the configuration information of buffer memory 29 words altogether, comprise: 7 data segment first addresss of EtherCAT download area and 7 data segment, length, EtherCAT uploads 7 data segment first addresss and 7 data segment, length in district, the startup command word that 1 master control issues;
6, the read data being input as two EtherCAT Read-write Catrol modules of interruption pulse synthesis module completes pulse signal.When detecting that two modules all send pulse signal, interruption pulse synthesis module can export an interruption pulse immediately to main control chip, and notice main control chip reads up-to-date EtherCAT network data from dual port RAM 2 module and dual port RAM 4 module; When only detecting that a module sends pulse signal, interruption pulse synthesis module can start a timer, exports an interruption pulse again to main control chip after time delay certain hour.Here delay time can be set between the look-at-me of two redundancy EtherCAT network, surveys the largest interval time drawn;
7, dual port RAM 3 module of ping-pang storage is adopted to be made up of the Block RAM of FPGA inside, the total hop count of data can uploaded due to each ESC chip ET1100 is at most 7 sections, every section of maximum 256 words, therefore configure dual port RAM 3_0 and the two-part capacity of dual port RAM 3_1 is 4KB.Asynchronous parallel bus interface module can carry out read/write operation to dual port RAM 3 module, but EtherCAT Read-write Catrol (B net) module can only carry out read operation to dual port RAM 3 module.Dual port RAM 3 inside modules has a ping-pang storage zone bit, its function is: when ping-pang storage zone bit is 0, asynchronous parallel bus interface module can to dual port RAM 3_0 read/write data, and EtherCAT Read-write Catrol (B net) module can only to dual port RAM 3_1 read data; When ping-pang storage zone bit is 1, asynchronous parallel bus interface module can to dual port RAM 3_1 read/write data, and EtherCAT Read-write Catrol (B net) module can only to dual port RAM 3_0 read data; Ping-pang storage zone bit all writes last data at asynchronous parallel bus interface module at every turn, and EtherCAT Read-write Catrol (B net) module overturns after running through last data simultaneously;
8, dual port RAM 4 module is made up of the Block RAM of FPGA inside, and because the total hop count of the Downloadable data of each ESC chip ET1100 is at most 7 sections, every section of maximum 256 words, the capacity therefore configuring dual port RAM 4 module is 4KB.Asynchronous parallel bus interface module can only carry out read operation to dual port RAM 4 module, and EtherCAT Read-write Catrol (B net) module can only carry out write operation to dual port RAM 4 module.
The two network data reading/writing method of a kind of EtherCAT of the present invention comprises starting method, reads the method for EtherCAT data and writes the method for EtherCAT data.
Starting method comprises:
1, after FPGA powers on, two EtherCAT Read-write Catrol modules carry out initial configuration to two panels ESC chip ET1100 respectively, after completing, wait for the startup command word that main control chip issues;
2, main control chip is by asynchronous parallel bus interface module, by the data segment first address of download area and data segment, length and data segment first address and the data segment, length write configuration information module of uploading district;
3, main control chip is by startup command word write configuration information module;
4, after two EtherCAT Read-write Catrol modules receive the startup command word in configuration information module, equal startup optimization.
The method reading EtherCAT data comprises:
1, two EtherCAT Read-write Catrol modules wait for the low level look-at-me that two panels ESC chip ET1100 exports respectively;
2, after receiving low level look-at-me, two EtherCAT Read-write Catrol modules, according to the data segment first address of download area in configuration information module and data segment, length, read data respectively from two panels ESC chip ET1100;
3, EtherCAT Read-write Catrol (A net) module by read download area data stored in dual port RAM 2 module, EtherCAT Read-write Catrol (B net) module by read download area data stored in dual port RAM 4 module;
4, after running through all data, two EtherCAT Read-write Catrol modules all can export a pulse signal to interruption pulse synthesis module;
5, interruption pulse synthesis module is by after two pulse signal synthesis, exports an interruption pulse to main control chip;
6, after main control chip receives interruption pulse, by asynchronous parallel bus interface module, from dual port RAM 2 module and dual port RAM 4 module, read EtherCAT data, and select the cumulative data segment that word is continuous, School Affairs is correct to be used as valid data;
The method writing EtherCAT data comprises:
1, after two EtherCAT Read-write Catrol modules run through all download areas data, the flow process writing EtherCAT data is started immediately.EtherCAT Read-write Catrol (A net) module writes ESC chip ET1100 (A net) by adopting the district's data of uploading in dual port RAM 1 module of ping-pang storage, and EtherCAT Read-write Catrol (B net) module writes ESC chip ET1100 (B net) by adopting the district's data of uploading in dual port RAM 3 module of ping-pang storage;
2, main control chip receives and after processing and uploading district's data, by asynchronous parallel bus interface module, writes in dual port RAM 1 module and dual port RAM 3 module by needing the data uploading to EtherCAT network simultaneously;
3, after two EtherCAT Read-write Catrol modules write all data, respectively the EtherCAT look-at-me of two panels ESC chip ET1100 is removed.
Finally should be noted that: above embodiment is only in order to illustrate that technical scheme of the present invention is not intended to limit; those of ordinary skill in the field still can modify to the specific embodiment of the present invention with reference to above-described embodiment or equivalent replacement; these do not depart from any amendment of spirit and scope of the invention or equivalent replacement, are all applying within the claims of the present invention awaited the reply.
Claims (11)
1. the two network data read-write system of EtherCAT, it is characterized in that, described system comprises asynchronous parallel bus interface module, data buffer area, EtherCAT Read-write Catrol module, configuration information module and interruption pulse synthesis module;
Described data buffer area comprises A network data buffer area and B network data buffer area;
Described system is connected with main control chip and ESC chip respectively;
Described asynchronous parallel bus interface module, data buffer area are connected successively with EtherCAT Read-write Catrol module;
Described asynchronous parallel bus interface module, configuration information module are connected successively with EtherCAT Read-write Catrol module;
Described asynchronous parallel bus interface module, interruption pulse synthesis module are connected successively with EtherCAT Read-write Catrol module.
2. the two network data read-write system of a kind of EtherCAT as claimed in claim 1, is characterized in that, described A network data buffer area comprises dual port RAM 2 module and adopts dual port RAM 1 module of ping-pang storage; Described dual port RAM 1 module comprises dual port RAM 1_0 and dual port RAM 1_1 two parts.
3. the two network data read-write system of a kind of EtherCAT as claimed in claim 1, is characterized in that, described B network data buffer area comprises dual port RAM 4 module and adopts dual port RAM 3 module of ping-pang storage; Described dual port RAM 3 module comprises dual port RAM 3_0 and dual port RAM 3_1 two parts.
4. the two network data read-write system of a kind of EtherCAT as claimed in claim 1, it is characterized in that, described asynchronous parallel bus interface module is externally connected with the bus interface of main control chip, is internally connected with dual port RAM module, configuration information module and interruption pulse synthesis module.
5. the two network data read-write system of a kind of EtherCAT as claimed in claim 1, it is characterized in that, the bus interface that described EtherCAT Read-write Catrol A net module is externally netted with ESC chip ET1100A is connected, internally with dual port RAM 2 module, adopt dual port RAM 1 module of ping-pang storage, configuration information module and interruption pulse synthesis module to be connected.
6. the two network data read-write system of a kind of EtherCAT as claimed in claim 1, it is characterized in that, the bus interface that described EtherCAT Read-write Catrol B net module is externally netted with ESC chip ET1100B is connected, internally with dual port RAM 4 module, adopt dual port RAM 3 module of ping-pang storage, configuration information module and interruption pulse synthesis module to be connected.
7. the two network data reading/writing method of EtherCAT, it is characterized in that, described method comprises starting method, reads EtherCAT data method and writes EtherCAT data method.
8. the two network data reading/writing method of a kind of EtherCAT as claimed in claim 7, it is characterized in that, described starting method comprises
(8.1) after FPGA powers on, EtherCAT Read-write Catrol module carries out initial configuration to ESC chip ET1100, after completing, waits for the startup command word that main control chip issues;
(8.2) main control chip is by asynchronous parallel bus interface module, by the data segment first address of download area and data segment, length and data segment first address and the data segment, length write configuration information module of uploading district;
(8.3) main control chip is by startup command word write configuration information module;
(8.4) after EtherCAT Read-write Catrol module receives the startup command word in configuration information module, startup optimization.
9. the two network data reading/writing method of a kind of EtherCAT as claimed in claim 7, is characterized in that, described in read EtherCAT data method and comprise
(9.1) EtherCAT Read-write Catrol module waits for the low level look-at-me that ESC chip ET1100 exports;
(9.2), after receiving low level look-at-me, EtherCAT Read-write Catrol module, according to the data segment first address of download area in configuration information module and data segment, length, reads data from ESC chip ET1100;
(9.3) EtherCAT Read-write Catrol A net module by read download area data stored in dual port RAM 2 module, EtherCAT Read-write Catrol B net module by read download area data stored in dual port RAM 4 module;
(9.4), after running through data, EtherCAT Read-write Catrol module exports a pulse signal to interruption pulse synthesis module;
(9.5), after pulse signal synthesizes by interruption pulse synthesis module, an interruption pulse is exported to main control chip;
(9.6) after main control chip receives interruption pulse, by asynchronous parallel bus interface module, from dual port RAM 2 module and dual port RAM 4 module, read EtherCAT data, and select the cumulative data segment that word is continuous, School Affairs is correct to use as valid data.
10. the two network data reading/writing method of a kind of EtherCAT as claimed in claim 7, is characterized in that, described in write EtherCAT data method and comprise
(10.1), after EtherCAT Read-write Catrol module runs through download area data, the flow process writing EtherCAT data is started immediately; EtherCAT Read-write Catrol A net module writes ESC chip ET1100A net by adopting the district's data of uploading in dual port RAM 1 module of ping-pang storage, and EtherCAT Read-write Catrol B net module writes ESC chip ET1100B net by adopting the district's data of uploading in dual port RAM 3 module of ping-pang storage;
(10.2) main control chip receives and after processing and uploading district's data, by asynchronous parallel bus interface module, writes in dual port RAM 1 module and dual port RAM 3 module by needing the data uploading to EtherCAT network simultaneously;
(10.3), after EtherCAT Read-write Catrol module writes data, the EtherCAT look-at-me of ESC chip ET1100 is removed.
11. as described in claim 8 ~ 10 the two network data reading/writing method of a kind of EtherCAT, it is characterized in that, described EtherCAT Read-write Catrol controls read/write data flow process by state machine, and state machine comprises initialization ESC chip ET1100, waits for startup command, waits for ET1100 look-at-me, reads the EtherCAT data of download area, has sent the pulse signal of read data, writes the EtherCAT data and removing ET1100 look-at-me 7 kinds of states that pass district.
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| CN104391818B (en) | 2018-08-28 |
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