CN104378107B - Digital processing device improving phase lock frequency modulation circuit broadband modulation flatness - Google Patents
Digital processing device improving phase lock frequency modulation circuit broadband modulation flatness Download PDFInfo
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- CN104378107B CN104378107B CN201410627415.1A CN201410627415A CN104378107B CN 104378107 B CN104378107 B CN 104378107B CN 201410627415 A CN201410627415 A CN 201410627415A CN 104378107 B CN104378107 B CN 104378107B
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Abstract
The invention provides a digital processing device improving phase lock frequency modulation circuit broadband modulation flatness. An FPGA carries out cache filtering processing on original baseband signals, and outputs the baseband signals A to a high-speed A/D converter; A/D quantized data output by the high-speed A/D converter are received, one path of data is output to a low pass filter module, and the other path of data is delayed and then output to a high-speed D/A converter B; the low pass filter module carries out low pass filtering on the A/D quantized data and outputs the filtered A/D quantized data to a high-speed D/A converter A to be changed into baseband signals B, and the baseband signals B are converted by an analog low pass filter into baseband signals C to be output to a loop lower pass filter; the high-speed D/A converter B converts the A/D quantized data into baseband signals D which are output to a voltage-controlled oscillator. According to the digital processing device improving phase lock frequency modulation circuit broadband modulation flatness, the response stability of a phase lock frequency modulation circuit for a baseband signal low frequency component can be improved, and the phase lock frequency modulation circuit has the broadband modulation performance with the stable flatness feature.
Description
Technical field
The present invention relates to Digital Signal Processing, at the numeral of PLL―FM base band signal process
Reason device.
Background technology
Baseband processing circuitry is by operational amplifier and lumped parameter unit in known 2 injection phase-locking FM circuits
The analogue integrator circuit of the compositions such as device.The integration time constant of analogue integrator is determined by the resistance in circuit, electric capacity, electric
Resistance, capacitance change with environment temperature and use time, thus the integration time constant of analogue integrator also with environment temperature and
Use time, the referred to as temperature drift of analogue integrator integration time constant and time drift.During the integration of analogue integrator
Between constant temperature drift and time drift, will influence PLL―FM wide-band modulation flat characteristic.
The content of the invention
In order to overcome the deficiencies in the prior art, the present invention to provide a kind of improvement PLL―FM wide-band modulation flat characteristic
Digital processing unit.The digital processing unit can improve response stabilization of the PLL―FM to baseband signal low frequency component
Property, make PLL―FM that there is the wide-band modulation performance of flat characteristic stabilization.
The technical solution adopted for the present invention to solve the technical problems is：May be programmed and patrol including high-speed a/d converter, FPGA
Collect device, high-speed d/a converter A, high-speed d/a converter B and simulation low-pass filter.
Baseband signal processing module and low-pass filtering module are included in described FPGA PLDs；Described base
Band signal processing module receives raw baseband signal and raw baseband signal clock, raw baseband signal is carried out at caching filtering
Reason produces baseband signal A, and baseband signal A is exported to high-speed a/d converter；Baseband signal processing module receives high-speed a/d
The A/D quantized datas of converter output are simultaneously divided into two-way, and A/D quantized datas are directly output to low pass filter blocks all the way, separately
A/D quantized datas are exported to high speed D/A converter B after entering line delay all the way；Described baseband signal processing module is high-speed a/d
Converter, high-speed d/a converter A, high-speed d/a converter B and low pass filter blocks provide system clock；Described low pass filtered
Ripple module is exported to high speed D/A converter A after LPF is carried out to A/D quantized datas, and configures PLL―FM intermediate frequency
The internal register of rate chip combiner；Described high-speed d/a converter A is the data conversion Cheng Ji from low-pass filtering module
Band signal B, image frequency signal is filtered by simulation low-pass filter, is converted to baseband signal C outputs to PLL―FM
In loop low pass filter；Described high-speed d/a converter B turns the A/D quantized datas from baseband signal processing module
Change baseband signal D, output to the voltage tuning end of the voltage controlled oscillator in PLL―FM into.
In described low-pass filtering module, low pass filter 3dB cut-off frequecy of passband f meets f=2 π N/kvkd, wherein N is
The frequency dividing ratio of phaselocked loop, k in PLL―FMvFor the electricity of voltage controlled oscillator in PLL―FM adjusts sensitivity, kdIt is lock phase
The discriminator sensitivity of FM circuit frequency synthesizer chip.
Present invention additionally comprises reference voltage source, described reference voltage source output terminal connection high-speed d/a converter A and high speed
The Voltage Reference end of D/A converter B, there is provided identical reference voltage.
The beneficial effects of the invention are as follows：As a result of temperature drift and time drift is small but digital processing of high precision
Device, improves the influence that PLL―FM wide-band modulation flat characteristic changes with temperature and use time.The present invention overcomes
Prior art wide-band modulation flat characteristic is with temperature drift and the influence of time drift.
Brief description of the drawings
Fig. 1 is structural representation of the invention；
In figure, 1- high-speed a/d converters, 2-FPGA PLDs, 3- high-speed d/a converter A, 4- analog low-pass
Wave filter, 5- high-speed d/a converter B, 6- frequency references source, 7- synthesizer chips, 8- loop low pass filters, 9- is voltage-controlled
Oscillator, 10- digital processing units, 11- PLL―FMs, 12- WBFM signals, 13- baseband signals B, 14- base band letter
Number A, 15- high-speed a/d converter system clocks, 16-A/D quantized datas, data after 17- LPFs, the conversion of 18- high-speed d/as
Device A system clocks, 19- high-speed d/a converter B system clocks, the A/D quantized datas after 20- delay process, 21- original base bands
Signal clock, 22- raw baseband signals, 23- baseband signals C, 24- baseband signal D, 25- reference voltage source.
Specific embodiment
The present invention is further described with reference to the accompanying drawings and examples, and the present invention includes but are not limited to following implementations
Example.
The present invention uses digital processing unit and known PLL―FM.The digital processing unit includes high speed A/
D converters, FPGA PLDs, high-speed d/a converter A, high-speed d/a converter B, simulation low-pass filter, benchmark
Voltage source etc..
Described FPGA PLDs and high-speed a/d converter, high-speed d/a converter A, high-speed d/a converter
The connection of B, voltage controlled oscillator and synthesizer chip.The I/O port of FPGA programmable logic devices and high-speed d/a converter A, high speed
The digital input end of D/A converter B is that one-to-one connection, i.e. FPGA PLDs a I/O port connect a high speed
The digital input end of D/A converter；The I/O port of FPGA programmable logic devices is one-to-one with the digital output end of high-speed a/d converter
Connection.
The analog output of described high-speed d/a converter A is connected with simulation low-pass filter.Described high-speed d/a turns
The analog output of parallel operation B is connected with the voltage tuning end of voltage controlled oscillator.Described reference voltage source output terminal connection is at a high speed
The Voltage Reference end of D/A converter A and high-speed d/a converter B, for it provides identical reference voltage.
Two modules are included in FPGA PLDs：Baseband signal processing module, low-pass filtering module.
Described baseband signal processing module function, one is to receive raw baseband signal and raw baseband signal clock, right
Raw baseband signal baseband signal A is produced after caching filtering process and baseband signal A is exported to high-speed a/d converter
Analog input end；Two is the system clock for producing high-speed a/d converter, and receives the A/D quantizations of high-speed a/d converter output
Data；Three is to export to low pass filter blocks the A/D quantized datas of reception, and for low pass filter blocks system is provided when
Clock；Four is the digital input end of output to high speed D/A converter B after the A/D quantized datas of reception are entered into line delay etc. reason,
And for high-speed d/a converter B provides system clock.
Described low-pass filtering module function, one is to receive A/D quantized datas from baseband signal processing module and be
System clock；Two is the LPF that the types such as IIR or FIR are carried out to A/D quantized datas, filtered data output to high speed D/
The number input of A converters A；Three is the internal register for configuring PLL―FM frequency synthesizer chip.
In described low-pass filtering module, it is desirable to which IIR or FIR low pass filter 3dB cut-off frequecy of passband f meet f=2 π
N/kvkd, wherein N is the frequency dividing ratio of phaselocked loop in PLL―FM, kvFor the electricity of voltage controlled oscillator in PLL―FM is adjusted
Sensitivity, unit rad/V, kdDiscriminator sensitivity, unit V/rad for PLL―FM frequency synthesizer chip.
Described high-speed a/d converter selects the high-speed AD converter of more than 8, and its function is that quantization can from FPGA
The baseband signal A of programmed logic device, and A/D quantized datas are input into FPGA PLD base band signal process moulds
In block.
Described high-speed d/a converter A selects the high-speed A/D converter of more than 8, and its function is that handle can from FPGA
Low-pass filtering module filtered data is converted into baseband signal B in programmed logic device.
Described simulation low-pass filter output is connected to the input of loop low pass filter, simulation low-pass filter
Effect is to filter the image frequency signal in high-speed d/a converter A output baseband signals B, the output letter of simulation low-pass filter
Number be baseband signal C.
Described high-speed d/a converter B selects the high-speed A/D converter of more than 8, and its function is that handle can from FPGA
A/D quantized datas in programmed logic device in baseband signal processing module after delay process are converted into baseband signal D.
The PLL―FM is generally known phase-locked loop circuit, comprising frequency reference source, synthesizer chip,
FPGA PLDs, loop low pass filter, voltage controlled oscillator.Described FPGA PLDs are for matching somebody with somebody
Put the internal register of synthesizer chip.Described frequency reference source provides reference frequency for synthesizer chip.Institute
The voltage controlled oscillator output signal stated to synthesizer chip, with outside after being divided through synthesizer chip inside frequency divider
Internally phase discriminator enters line phase and compares reference frequency, exports direct-flow error voltage.Direct-flow error voltage passes through loop low pass
Ripple device, voltage controlled oscillator is input to after phase demodulation frequency and high-frequency noise in direct-flow error voltage are filtered through loop low pass filter
Voltage tuning end, complete phase-locked loop circuit closed loop phase lock control.
Described baseband signal C and baseband signal D is connected respectively to the input and VCO of loop low pass filter
The voltage tuning end of device, the output signal of voltage controlled oscillator is WBFM signal in PLL―FM.
Device embodiment：Reference picture 1, the inventive system comprises digital processing unit 10 and PLL―FM 11.Institute
Stating digital processing unit 10 includes high-speed a/d converter 1, FPGA PLDs 2, high-speed d/a converter A3, high speed D/
A converter B5, simulation low-pass filter 4, reference voltage source 25 etc..
PLL―FM 11 is generally known phase-locked loop circuit, comprising frequency reference source 6, synthesizer chip 7,
Loop low pass filter 8, voltage controlled oscillator 9 etc..Described synthesizer chip 7 connects that frequency reference source 6, FPGA is programmable to be patrolled
Collect device 2 and loop low pass filter 8.Described loop low pass filter 8 exports the voltage tuning end for connecing voltage controlled oscillator 9.
Described FPGA PLDs 2 are the internal registers for configuration frequency chip combiner 7.
Described FPGA PLDs 2 connect high-speed a/d converter 1, high-speed d/a converter A3 and high-speed d/a
Converter B5.Two modules are included in FPGA PLDs 2：Baseband signal processing module, low-pass filtering module.
The analog output of described high-speed d/a converter A3 is connected with simulation low-pass filter 4.Described high-speed d/a
The analog output of converter B5 is connected with the voltage tuning end of voltage controlled oscillator 9.The output end of described reference voltage source 25
Connection high-speed d/a converter A3 and high-speed d/a converter B5, for it provides identical reference voltage.
Described simulation low-pass filter 4 exports the input for connecing loop low pass filter 8.Described analogue low pass filtering
The cut-off frequecy of passband of device 4 need to be much larger than the frequency of raw baseband signal 22, and stopband cut-off frequency need to be to high-speed d/a converter A3
The first image frequency and its image frequency of high order have rejection ability.
The baseband signal processing module that described raw baseband signal 22 enters in FPGA PLDs 2.It is described
FPGA PLDs 2 in baseband signal processing module will receive raw baseband signal 22 cache filtering after, it is defeated
Go out baseband signal A14 to high-speed a/d converter 1.Described raw baseband signal clock 21 enters FPGA PLDs 2
In baseband signal processing module, high-speed a/d converter system clock 15, high speed D/ is produced by frequency multiplication of phase locked loop in FPGA
A converter A system clocks 18.Described high-speed a/d converter system clock 15 is exported to high-speed a/d converter 1, is high speed A/
D converters 1 provide sampling clock.Described baseband signal processing module receives the A/D amounts from the output of high-speed a/d converter 1
Change data 16, and A/D quantized datas 16 are delivered into the low-pass filtering module in FPGA PLDs 2.Described base band
Signal processing module will receive A/D quantized datas 16 and carry out the treatment such as caching filtering, time delay, the A/ after the delay process for obtaining
D quantized datas 20 are exported to the digital input end of high speed D/A converter B5；Described baseband signal processing module produces high speed D/
A converter B systems clock 19, the input end of clock of output to high speed D/A converter B5, for high-speed d/a converter B5 provides system
System clock.
Described high-speed d/a converter B5 outputs baseband signal D24 exports into PLL―FM 11 voltage controlled oscillator 9
Voltage tuning end, for direct frequency modulation of the phase locking, realize the direct frequency modulation of the high frequency components of baseband signal 13.
Low-pass filtering module in described FPGA PLDs 2, receives from baseband signal processing module
A/D quantized datas 16 and high-speed d/a converter A system clocks 18.During using high-speed d/a converter A system clocks 18 as system
Clock carries out the type LPF such as FIR or IIR to A/D quantized datas 16, and data 17 are exported at a high speed after the LPF of generation
The digital input end of D/A converter A3.Described high-speed d/a converter A system clocks 18, high-speed d/a converter B system clock
19 and high-speed a/d converter system clock 15 be same clock source, high-speed d/a converter A system clocks 18 export at a high speed
The input end of clock of D/A converter A3, for high-speed d/a converter A3 provides system clock.Described high-speed d/a converter A systems
The frequency of system clock 18 is significantly larger than the frequency of raw baseband signal clock 21.
Described baseband signal B13 into simulation low-pass filter 4 filter high-speed d/a converter A3 generation mirror image frequently
Rate.Described simulation low-pass filter 4 is output as baseband signal C23, the ring that baseband signal C23 enters in PLL―FM 11
The input of road low pass filter 8, completes the indirect frequency modulation of the low frequency components of baseband signal 13.The output of PLL―FM 11
The WBFM signal 12 that as flat characteristic is stablized.
Claims (3)
1. a kind of digital processing unit for improving PLL―FM wide-band modulation flatness, including high-speed a/d converter, FPGA
PLD, high-speed d/a converter A, high-speed d/a converter B and simulation low-pass filter, it is characterised in that：It is described
FPGA PLDs in include baseband signal processing module and low pass filter blocks；Described base band signal process
Module receives raw baseband signal and raw baseband signal clock, caching filtering process is carried out to raw baseband signal and produces base band
Signal A, and baseband signal A is exported to high-speed a/d converter；Baseband signal processing module receives high-speed a/d converter output
A/D quantized datas and be divided into two-way, A/D quantized datas are directly output to low pass filter blocks all the way, and another road A/D quantifies
Data are exported to high speed D/A converter B after entering line delay；Described baseband signal processing module is high-speed a/d converter, high speed
D/A converter A, high-speed d/a converter B and low pass filter blocks provide system clock；Described low pass filter blocks pair
A/D quantized datas are exported to high speed D/A converter A after carrying out LPF, and configure PLL―FM frequency synthesizer
The internal register of chip；Described high-speed d/a converter A is the data conversion from low pass filter blocks into baseband signal
B, image frequency signal is filtered by simulation low-pass filter, is converted to baseband signal C outputs to the ring in PLL―FM
Road low pass filter；A/D quantized datas from baseband signal processing module are converted into base by described high-speed d/a converter B
Band signal D, output to the voltage tuning end of the voltage controlled oscillator in PLL―FM.
2. it is according to claim 1 improve PLL―FM wide-band modulation flatness digital processing unit, its feature
It is：In described low pass filter blocks, low pass filter 3dB cut-off frequecy of passband f meets f=2 π N/kvkd, wherein N is
The frequency dividing ratio of phaselocked loop, k in PLL―FMvFor the electricity of voltage controlled oscillator in PLL―FM adjusts sensitivity, kdIt is lock phase
The discriminator sensitivity of FM circuit frequency synthesizer chip.
3. it is according to claim 1 improve PLL―FM wide-band modulation flatness digital processing unit, its feature
It is：Also include reference voltage source, described reference voltage source output terminal connection high-speed d/a converter A and high-speed d/a converter
The Voltage Reference end of B, there is provided identical reference voltage.
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| CN201410627415.1A CN104378107B (en) | 2014-11-10 | 2014-11-10 | Digital processing device improving phase lock frequency modulation circuit broadband modulation flatness |
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| CN104378107B true CN104378107B (en) | 2017-05-24 |
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| CN111384994B (en) * | 2018-12-28 | 2022-05-10 | 武汉万集信息技术有限公司 | Signal processing method and device |
| CN111308224B (en) * | 2020-02-24 | 2021-02-05 | 山东大学 | Signal flatness compensation method of radio astronomical receiver and radio astronomical receiver |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101610095A (en) * | 2009-05-12 | 2009-12-23 | 北京航空航天大学 | A kind of ultra-wideband radio frequency digital receiver device and its implementation based on FPGA |
| WO2011141540A1 (en) * | 2010-05-13 | 2011-11-17 | Bangor University | Synchronous clocking for optical orthogonal frequency division multiplexing transmission systems |
| CN102299879A (en) * | 2011-06-09 | 2011-12-28 | 西北工业大学 | Phase-lock frequency modulation transmitter |
| CN202721662U (en) * | 2012-05-09 | 2013-02-06 | 西北工业大学 | Phase lock frequency modulation circuit temperature drift compensation apparatus |
| CN103364765A (en) * | 2013-07-24 | 2013-10-23 | 中国人民解放军空军预警学院 | Digital radio frequency memory based on analogue demodulation/modulation |
-
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- 2014-11-10 CN CN201410627415.1A patent/CN104378107B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101610095A (en) * | 2009-05-12 | 2009-12-23 | 北京航空航天大学 | A kind of ultra-wideband radio frequency digital receiver device and its implementation based on FPGA |
| WO2011141540A1 (en) * | 2010-05-13 | 2011-11-17 | Bangor University | Synchronous clocking for optical orthogonal frequency division multiplexing transmission systems |
| CN102299879A (en) * | 2011-06-09 | 2011-12-28 | 西北工业大学 | Phase-lock frequency modulation transmitter |
| CN202721662U (en) * | 2012-05-09 | 2013-02-06 | 西北工业大学 | Phase lock frequency modulation circuit temperature drift compensation apparatus |
| CN103364765A (en) * | 2013-07-24 | 2013-10-23 | 中国人民解放军空军预警学院 | Digital radio frequency memory based on analogue demodulation/modulation |
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