CN104378107A - Digital processing device improving phase lock frequency modulation circuit broadband modulation flatness - Google Patents
Digital processing device improving phase lock frequency modulation circuit broadband modulation flatness Download PDFInfo
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- CN104378107A CN104378107A CN201410627415.1A CN201410627415A CN104378107A CN 104378107 A CN104378107 A CN 104378107A CN 201410627415 A CN201410627415 A CN 201410627415A CN 104378107 A CN104378107 A CN 104378107A
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Abstract
The invention provides a digital processing device improving phase lock frequency modulation circuit broadband modulation flatness. An FPGA carries out cache filtering processing on original baseband signals, and outputs the baseband signals A to a high-speed A/D converter; A/D quantized data output by the high-speed A/D converter are received, one path of data is output to a low pass filter module, and the other path of data is delayed and then output to a high-speed D/A converter B; the low pass filter module carries out low pass filtering on the A/D quantized data and outputs the filtered A/D quantized data to a high-speed D/A converter A to be changed into baseband signals B, and the baseband signals B are converted by an analog low pass filter into baseband signals C to be output to a loop lower pass filter; the high-speed D/A converter B converts the A/D quantized data into baseband signals D which are output to a voltage-controlled oscillator. According to the digital processing device improving phase lock frequency modulation circuit broadband modulation flatness, the response stability of a phase lock frequency modulation circuit for a baseband signal low frequency component can be improved, and the phase lock frequency modulation circuit has the broadband modulation performance with the stable flatness feature.
Description
Technical field
The present invention relates to Digital Signal Processing, especially about the digital processing unit of PLL―FM base band signal process.
Background technology
The analogue integrator circuit that baseband processing circuitry is made up of operational amplifier and lumped parameter components and parts etc. in known 2 injection phase-locking FM circuit.The integration time constant of analogue integrator is determined by the resistance in circuit, electric capacity, resistance, capacitance change with ambient temperature and service time, therefore the integration time constant of analogue integrator is also with ambient temperature and service time, be referred to as temperature drift and the time drift of analogue integrator integration time constant.The temperature drift of the integration time constant of analogue integrator and time drift, will affect the flat characteristic of the wide-band modulation of PLL―FM.
Summary of the invention
In order to overcome the deficiencies in the prior art, the invention provides a kind of digital processing unit improving PLL―FM wide-band modulation flat characteristic.This digital processing unit can improve the response stability of PLL―FM to baseband signal low frequency component, makes PLL―FM have the stable wide-band modulation performance of flat characteristic.
The technical solution adopted for the present invention to solve the technical problems is: comprise high-speed a/d converter, FPGA programmable logic device, high-speed d/a transducer A, high-speed d/a transducer B and simulation low-pass filter.
Baseband signal processing module and low-pass filtering module is comprised in described FPGA programmable logic device; Described baseband signal processing module receives raw baseband signal and raw baseband signal clock, carries out buffer memory filtering process and produces baseband signal A, and export baseband signal A to high-speed a/d converter to raw baseband signal; Baseband signal processing module receives the A/D quantized data of high-speed a/d converter output and is divided into two-way, and a road A/D quantized data directly exports low pass filter blocks to, exports high-speed d/a transducer B after another road A/D quantized data carries out time delay to; Described baseband signal processing module is high-speed a/d converter, high-speed d/a transducer A, high-speed d/a transducer B and low pass filter blocks provide system clock; Described low-pass filtering module exports high-speed d/a transducer A to after carrying out low-pass filtering to A/D quantized data, and configures the internal register of PLL―FM frequency synthesizer chip; Described high-speed d/a transducer A becomes baseband signal B the data transaction from low-pass filtering module, by simulation low-pass filter filtering image frequency signal, is converted to baseband signal C and outputs to loop low pass filter in PLL―FM; Described high-speed d/a transducer B converts baseband signal D to the A/D quantized data from baseband signal processing module, exports the voltage tuning end of the voltage controlled oscillator in PLL―FM to.
In described low-pass filtering module, low pass filter 3dB cut-off frequecy of passband f meets f=2 π N/k
vk
d, wherein N is the frequency dividing ratio of phase-locked loop in PLL―FM, k
vfor the electricity of voltage controlled oscillator in PLL―FM adjusts sensitivity, k
dfor the discriminator sensitivity of PLL―FM frequency synthesizer chip.
The present invention also comprises reference voltage source, and described reference voltage source output terminal connects the Voltage Reference end of high-speed d/a transducer A and high-speed d/a transducer B, provides identical reference voltage.
The invention has the beneficial effects as follows: owing to have employed temperature drift and the little but digital processing unit that precision is high of time drift, improve the impact of PLL―FM wide-band modulation flat characteristic with temperature and change service time.Instant invention overcomes the impact of prior art wide-band modulation flat characteristic with temperature drift and time drift.
Accompanying drawing explanation
Fig. 1 is structural representation of the present invention;
In figure, 1-high-speed a/d converter, 2-FPGA programmable logic device, 3-high-speed d/a transducer A, 4-simulation low-pass filter, 5-high-speed d/a transducer B, 6-frequency reference source, 7-synthesizer chip, 8-loop low pass filter, 9-voltage controlled oscillator, 10-digital processing unit, 11-PLL―FM, 12-wideband frequency modulation signal, 13-baseband signal B, 14-baseband signal A, 15-high-speed a/d converter system clock, 16-A/D quantized data, data after 17-low-pass filtering, 18-high-speed d/a transducer A system clock, 19-high-speed d/a transducer B system clock, A/D quantized data after 20-delay process, 21-raw baseband signal clock, 22-raw baseband signal, 23-baseband signal C, 24-baseband signal D, 25-reference voltage source.
Embodiment
Below in conjunction with drawings and Examples, the present invention is further described, the present invention includes but be not limited only to following embodiment.
The present invention adopts digital processing unit and known PLL―FM.Described digital processing unit comprises high-speed a/d converter, FPGA programmable logic device, high-speed d/a transducer A, high-speed d/a transducer B, simulation low-pass filter, reference voltage source etc.
Described FPGA programmable logic device is connected with high-speed a/d converter, high-speed d/a transducer A, high-speed d/a transducer B, voltage controlled oscillator and synthesizer chip.The I/O port of FPGA programmable logic device and the digital input end of high-speed d/a transducer A, high-speed d/a transducer B are for be connected one to one, and namely an I/O port of FPGA programmable logic device connects the digital input end of a high-speed d/a transducer; The I/O port of FPGA programmable logic device is connected one to one with the digital output end of high-speed a/d converter.
The analog output of described high-speed d/a transducer A is connected with simulation low-pass filter.The described analog output of high-speed d/a transducer B is connected with the voltage tuning end of voltage controlled oscillator.Described reference voltage source output terminal connects the Voltage Reference end of high-speed d/a transducer A and high-speed d/a transducer B, for it provides identical reference voltage.
Two modules are comprised: baseband signal processing module, low-pass filtering module in FPGA programmable logic device.
Described baseband signal processing module function, one is receive raw baseband signal and raw baseband signal clock, produces baseband signal A and baseband signal A is exported to the analog input end of high-speed a/d converter to raw baseband signal after carrying out buffer memory filtering process; Two is the system clocks producing high-speed a/d converter, and receives the A/D quantized data of high-speed a/d converter output; Three is export the A/D quantized data of reception to low pass filter blocks, and provides system clock for low pass filter blocks; Four is, after the A/D quantized data of reception being carried out the process such as time delay, export the digital input end of high-speed d/a transducer B to, and provides system clock for high-speed d/a transducer B.
Described low-pass filtering module function, one is receive from the A/D quantized data of baseband signal processing module and system clock; Two is the low-pass filtering of A/D quantized data being carried out to the types such as IIR or FIR, and filtered data export the number input of high-speed d/a transducer A to; Three is the internal registers configuring PLL―FM frequency synthesizer chip.
In described low-pass filtering module, require that IIR or FIR low pass filter 3dB cut-off frequecy of passband f meets f=2 π N/k
vk
d, wherein N is the frequency dividing ratio of phase-locked loop in PLL―FM, k
vfor the electricity of voltage controlled oscillator in PLL―FM adjusts sensitivity, unit rad/V, k
dfor discriminator sensitivity, the unit V/rad of PLL―FM frequency synthesizer chip.
Described high-speed a/d converter selects the high-speed AD converter of more than 8, and its function quantizes the baseband signal A from FPGA programmable logic device, and A/D quantized data is inputed in FPGA programmable logic device baseband signal processing module.
Described high-speed d/a transducer A selects the high-speed A/D converter of more than 8, and its function is converting baseband signal B to from low-pass filtering module filtered data in FPGA programmable logic device.
Described simulation low-pass filter exports the input being connected to loop low pass filter, the effect of simulation low-pass filter is the image frequency signal that filtering high-speed d/a transducer A exports in baseband signal B, and the output signal of simulation low-pass filter is baseband signal C.
Described high-speed d/a transducer B selects the high-speed A/D converter of more than 8, and its function converts baseband signal D to from the A/D quantized data after delay process in baseband signal processing module in FPGA programmable logic device.
Described PLL―FM is general known phase-locked loop circuit, comprises frequency reference source, synthesizer chip, FPGA programmable logic device, loop low pass filter, voltage controlled oscillator.Described FPGA programmable logic device is used to the internal register of configuration frequency chip combiner.Described frequency reference source provides reference frequency for synthesizer chip.Described voltage controlled oscillator output signal, to synthesizer chip, carries out phase compare with external reference frequency at inner phase discriminator, exports direct-flow error voltage after the inner frequency divider frequency division of synthesizer chip.Direct-flow error voltage, by loop low pass filter, is input to the voltage tuning end of voltage controlled oscillator after the phase demodulation frequency in loop low pass filter filtering direct-flow error voltage and high-frequency noise, and the closed loop phase lock completing phase-locked loop circuit controls.
Described baseband signal C and baseband signal D is connected respectively to the input of loop low pass filter and the voltage tuning end of voltage controlled oscillator, and in PLL―FM, the output signal of voltage controlled oscillator is wideband frequency modulation signal.
Device embodiment: with reference to Fig. 1, the inventive system comprises digital processing unit 10 and PLL―FM 11.Described digital processing unit 10 comprises high-speed a/d converter 1, FPGA programmable logic device 2, high-speed d/a transducer A3, high-speed d/a transducer B5, simulation low-pass filter 4, reference voltage source 25 etc.
PLL―FM 11 is general known phase-locked loop circuits, comprises frequency reference source 6, synthesizer chip 7, loop low pass filter 8, voltage controlled oscillator 9 etc.Described synthesizer chip 7 connects frequency reference source 6, FPGA programmable logic device 2 and loop low pass filter 8.Described loop low pass filter 8 exports the voltage tuning end connecing voltage controlled oscillator 9.Described FPGA programmable logic device 2 is used to the internal register of configuration frequency chip combiner 7.
Described FPGA programmable logic device 2 connects high-speed a/d converter 1, high-speed d/a transducer A3 and high-speed d/a transducer B5.Two modules are comprised: baseband signal processing module, low-pass filtering module in FPGA programmable logic device 2.
The analog output of described high-speed d/a transducer A3 is connected with simulation low-pass filter 4.The described analog output of high-speed d/a transducer B5 is connected with the voltage tuning end of voltage controlled oscillator 9.The output of described reference voltage source 25 connects high-speed d/a transducer A3 and high-speed d/a transducer B5, for it provides identical reference voltage.
Described simulation low-pass filter 4 exports the input connecing loop low pass filter 8.The cut-off frequecy of passband of described simulation low-pass filter 4 need much larger than the frequency of raw baseband signal 22, and stopband cut-off frequency need have rejection ability to the image frequency of first image frequency of high-speed d/a transducer A3 and high order thereof.
Described raw baseband signal 22 enters the baseband signal processing module in FPGA programmable logic device 2.After baseband signal processing module in described FPGA programmable logic device 2 will receive the filtering of raw baseband signal 22 buffer memory, export baseband signal A14 to high-speed a/d converter 1.Described raw baseband signal clock 21 enters the baseband signal processing module in FPGA programmable logic device 2, produces high-speed a/d converter system clock 15, high-speed d/a transducer A system clock 18 by the frequency multiplication of phase locked loop in FPGA.Described high-speed a/d converter system clock 15 exports high-speed a/d converter 1 to, for high-speed a/d converter 1 provides sampling clock.Described baseband signal processing module receives the A/D quantized data 16 exported from high-speed a/d converter 1, and A/D quantized data 16 is delivered to the low-pass filtering module in FPGA programmable logic device 2.Described baseband signal processing module will receive A/D quantized data 16 and carry out the process such as buffer memory filtering, time delay, and the A/D quantized data 20 after the delay process obtained exports the digital input end of high-speed d/a transducer B5 to; Described baseband signal processing module produces high-speed d/a transducer B system clock 19, exports the input end of clock of high-speed d/a transducer B5 to, for high-speed d/a transducer B5 provides system clock.
Described high-speed d/a transducer B5 exports the voltage tuning end that baseband signal D24 exports voltage controlled oscillator 9 in PLL―FM 11 to, for direct frequency modulation of the phase locking, realizes the direct frequency modulation of baseband signal 13 high frequency components.
Low-pass filtering module in described FPGA programmable logic device 2, receives the A/D quantized data 16 from baseband signal processing module and high-speed d/a transducer A system clock 18.Carry out the type low-pass filtering such as FIR or IIR as system clock to A/D quantized data 16 using high-speed d/a transducer A system clock 18, after the low-pass filtering of generation, data 17 export to the digital input end of high-speed d/a transducer A3.Described high-speed d/a transducer A system clock 18, high-speed d/a transducer B system clock 19 and high-speed a/d converter system clock 15 are same clock source, high-speed d/a transducer A system clock 18 exports the input end of clock of high-speed d/a transducer A3 to, for high-speed d/a transducer A3 provides system clock.The frequency of described high-speed d/a transducer A system clock 18 will much larger than the frequency of raw baseband signal clock 21.
Described baseband signal B13 enters the image frequency that simulation low-pass filter 4 filtering high-speed d/a transducer A3 produces.It is the input that baseband signal C23, baseband signal C23 enter the loop low pass filter 8 in PLL―FM 11 that described simulation low-pass filter 4 exports, and completes the indirect frequency modulation of baseband signal 13 low frequency components.The output of PLL―FM 11 is the stable wideband frequency modulation signal 12 of flat characteristic.
Claims (3)
1. one kind is improved the digital processing unit of PLL―FM wide-band modulation flatness, comprise high-speed a/d converter, FPGA programmable logic device, high-speed d/a transducer A, high-speed d/a transducer B and simulation low-pass filter, it is characterized in that: in described FPGA programmable logic device, comprise baseband signal processing module and low-pass filtering module; Described baseband signal processing module receives raw baseband signal and raw baseband signal clock, carries out buffer memory filtering process and produces baseband signal A, and export baseband signal A to high-speed a/d converter to raw baseband signal; Baseband signal processing module receives the A/D quantized data of high-speed a/d converter output and is divided into two-way, and a road A/D quantized data directly exports low pass filter blocks to, exports high-speed d/a transducer B after another road A/D quantized data carries out time delay to; Described baseband signal processing module is high-speed a/d converter, high-speed d/a transducer A, high-speed d/a transducer B and low pass filter blocks provide system clock; Described low-pass filtering module exports high-speed d/a transducer A to after carrying out low-pass filtering to A/D quantized data, and configures the internal register of PLL―FM frequency synthesizer chip; Described high-speed d/a transducer A becomes baseband signal B the data transaction from low-pass filtering module, by simulation low-pass filter filtering image frequency signal, is converted to baseband signal C and outputs to loop low pass filter in PLL―FM; Described high-speed d/a transducer B converts baseband signal D to the A/D quantized data from baseband signal processing module, exports the voltage tuning end of the voltage controlled oscillator in PLL―FM to.
2. the digital processing unit improving PLL―FM wide-band modulation flatness according to claim 1, is characterized in that: in described low-pass filtering module, and low pass filter 3dB cut-off frequecy of passband f meets f=2 π N/k
vk
d, wherein N is the frequency dividing ratio of phase-locked loop in PLL―FM, k
vfor the electricity of voltage controlled oscillator in PLL―FM adjusts sensitivity, k
dfor the discriminator sensitivity of PLL―FM frequency synthesizer chip.
3. the digital processing unit improving PLL―FM wide-band modulation flatness according to claim 1, it is characterized in that: also comprise reference voltage source, described reference voltage source output terminal connects the Voltage Reference end of high-speed d/a transducer A and high-speed d/a transducer B, provides identical reference voltage.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111308224A (en) * | 2020-02-24 | 2020-06-19 | 山东大学 | Signal flatness compensation method of radio astronomical receiver and radio astronomical receiver |
| CN111384994A (en) * | 2018-12-28 | 2020-07-07 | 武汉万集信息技术有限公司 | Signal processing method and device |
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| CN102299879A (en) * | 2011-06-09 | 2011-12-28 | 西北工业大学 | Phase-lock frequency modulation transmitter |
| CN202721662U (en) * | 2012-05-09 | 2013-02-06 | 西北工业大学 | Phase lock frequency modulation circuit temperature drift compensation apparatus |
| CN103364765A (en) * | 2013-07-24 | 2013-10-23 | 中国人民解放军空军预警学院 | Digital radio frequency memory based on analogue demodulation/modulation |
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Patent Citations (5)
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| CN101610095A (en) * | 2009-05-12 | 2009-12-23 | 北京航空航天大学 | A kind of ultra-wideband radio frequency digital receiver device and its implementation based on FPGA |
| WO2011141540A1 (en) * | 2010-05-13 | 2011-11-17 | Bangor University | Synchronous clocking for optical orthogonal frequency division multiplexing transmission systems |
| CN102299879A (en) * | 2011-06-09 | 2011-12-28 | 西北工业大学 | Phase-lock frequency modulation transmitter |
| CN202721662U (en) * | 2012-05-09 | 2013-02-06 | 西北工业大学 | Phase lock frequency modulation circuit temperature drift compensation apparatus |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111384994A (en) * | 2018-12-28 | 2020-07-07 | 武汉万集信息技术有限公司 | Signal processing method and device |
| CN111308224A (en) * | 2020-02-24 | 2020-06-19 | 山东大学 | Signal flatness compensation method of radio astronomical receiver and radio astronomical receiver |
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| CN104378107B (en) | 2017-05-24 |
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