CN104377545B - A kind of piezoelectric modulation vertical cavity semiconductor laser structure - Google Patents

A kind of piezoelectric modulation vertical cavity semiconductor laser structure Download PDF

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CN104377545B
CN104377545B CN201410759292.7A CN201410759292A CN104377545B CN 104377545 B CN104377545 B CN 104377545B CN 201410759292 A CN201410759292 A CN 201410759292A CN 104377545 B CN104377545 B CN 104377545B
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layer
transparency electrode
thickness
gaas
sio
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CN104377545A (en
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王智勇
吕朝蕙
李军
尧舜
邱运涛
贾冠男
高祥宇
雷宇鑫
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Beijing University of Technology
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Beijing University of Technology
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Abstract

The present invention provides a kind of piezoelectric modulation vertical cavity semiconductor laser structure, and it includes：Single-chip substrate (1), cushion (2), n-type DBR speculums (3), carrier lower limit layer (4), gain region (5), carrier upper limiting layer (6), photoelectricity limiting layer (7), p-type DBR speculums (8), Ohmic electrode contact layer (9), first transparency electrode (10), two the second layer gold (11), SiO2Anti-reflection film (12), two SiN insulating barriers (13), second transparency electrode (14), two the 3rd layer gold (15), the first layer gold (16).It utilizes SiO when powering up work2The piezoelectric property of anti-reflection film makes the chamber of vertical cavity semiconductor laser that different degrees of deformation occur, so as to realize the piezoelectric modulation to vertical cavity semiconductor laser power output.

Description

A kind of piezoelectric modulation vertical cavity semiconductor laser structure
Technical field
The present invention relates to semiconductor laser device technical field, more particularly to a kind of piezoelectric modulation vertical cavity semiconductor laser Device structure.
Background technology
At present, the modulation of vertical cavity semiconductor laser power output, which relies primarily on, changes the electric current applied and realizes, adjusts Mode processed is single.Generally, need to plate SiO in the output end face of vertical cavity semiconductor laser2Anti-reflection film, to improve differential quantum Efficiency and enhancing light transmission rate, and SiO2It is the material with piezoelectric property.Therefore anti-reflection film SiO can be utilized2Piezoelectricity it is special Property, the chamber of laser is changed into on-plane surface unsteady cavity from plane stability chamber, vertical cavity semiconductor laser is exported so as to realize The modulation of power.
Piezoelectric is a kind of dielectric with piezoelectricity physical characteristic, is typically formed as conversion element and is widely used in pressing On electric-type sensor.When applying alternating electric field on some polarization of dielectric directions, mechanical shape can occur for these dielectrics Become, after electric field removes, dielectric mechanically deform disappears therewith, and this phenomenon is referred to as inverse piezoelectric effect.Inverse piezoelectric effect is by electricity Mechanical energy can be converted to.
SiO2For regular hexahedron, there are three reference axis, z-axis is the symmetry axis of crystal, referred to as optical axis, is not had in this direction There is piezo-electric effect；X-axis is referred to as electric axis, and the piezo-electric effect on X-axis crystal face is most obvious；Y-axis is referred to as mechanical axis, in electric field force In the presence of it is most notable along the deformation of this direction of principal axis.
The content of the invention
To solve the above problems, the present invention provides a kind of piezoelectric modulation vertical cavity semiconductor laser structure, by making SiO2Anti-reflection film both sides are plated with the ingehious design of electrode, realize the modulation to vertical cavity semiconductor laser power output.
The piezoelectric modulation vertical cavity semiconductor laser structure of the present invention, it includes：
Single-chip substrate (1), cushion (2), n-type DBR speculums (3), carrier lower limit layer (4), gain region (5), Carrier upper limiting layer (6), photoelectricity limiting layer (7), p-type DBR speculums (8), Ohmic electrode contact layer (9), the first transparent electricity Pole (10), two the second layer gold (11), SiO2Anti-reflection film (12), two SiN insulating barriers (13), second transparency electrode (14), two Individual 3rd layer gold (15), the first layer gold (16)；
Wherein, single-chip substrate (1), cushion (2), n-type DBR speculums (3), carrier lower limit layer (4), gain region (5), carrier upper limiting layer (6), photoelectricity limiting layer (7), p-type DBR speculums (8) and Ohmic electrode contact layer (9) are wide；
And first layer gold (16) is deposited below the single-chip substrate (1)；Above the single-chip substrate (1) Sequentially generate cushion (2), n-type DBR speculums (3), carrier lower limit layer (4), gain region (5), carrier upper limiting layer (6), photoelectricity limiting layer (7), p-type DBR speculums (8) and Ohmic electrode contact layer (9)；
Further, the first transparency electrode (10) is deposited in the central area of the Ohmic electrode contact layer (9)；Institute Two the second layer gold (11) are stated to be deposited respectively on the Ohmic electrode contact layer (9) and being located at the first transparency electrode (10) Both sides；And the overall width of the first transparency electrode (10) and described two second layer gold (11) and single-chip substrate (1) width It is identical；
The SiO2Anti-reflection film (12) is born in the first transparency electrode (10), and the SiO2Anti-reflection film (12) and institute State that first transparency electrode (10) is wide, both sides are respectively with the first transparency electrode (10) both sides in same vertical plane；
Described two SiN insulating barriers (13) are born on described two second layer gold (11) and are located at the SiO respectively2It is anti-reflection Film (12) both sides；
The second transparency electrode (14) is deposited in the SiO2On anti-reflection film (12), and the second transparency electrode (14) With the SiO2Anti-reflection film (12) is wide, and both sides respectively with the SiO2Anti-reflection film (12) both sides are in same vertical plane；
Described two 3rd layer gold (15) are born on described two SiN insulating barriers and are located at the second transparency electrode respectively (14) both sides, described two 3rd layer gold (15) and described two SiN insulating barriers (13) are wide.
Further, the single-chip substrate (1) is n-GaAs (100) (Si that width is 250um:2x1018/cm2)；
The cushion (2) is the n-GaAs (Si that thickness is 0.5um:2x1018/cm2)；
The n-type DBR speculums (3) are by the Al of 20 couples of λ/4 cycles repetition0.9Ga0.1As(81.7nm)/GaAs (69.6nm)(Si:2x1018/cm2) composition；
The carrier lower limit layer (4) is the n-Al that thickness is 72.3nm0.2Ga0.8As(Si:1×1018/cm3)；
The gain region (5) includes 3 SQWs, and trap material is In0.2Ga0.8As thickness is 8nm, and barrier material is GaAs thickness is 10nm；
The carrier upper limiting layer (6) is the p-Al that thickness is 72.3nm0.2Ga0.8As(C:1×1018/cm3)；
The photoelectricity limiting layer (7) is the AlAs (C that thickness is 30nm:2×1018/cm3)；
The Al that the p-type DBR speculums (8) are repeated by the cycles of 29.5 couples of λ/40.9Ga0.1As(81.7nm)/GaAs (69.6nm)(C:2×1018/ cm3) form；
The Ohmic electrode contact layer (9) is the p-type GaAs (C that thickness is 139.2nm:4×1019/cm3) Ohmic electrode connects Contact layer.
The first transparency electrode (10) is the indium tin oxide transparency electrode that width is 50um, thickness is 0.3um；
The thick 0.3um of described two second layer gold (11), width 100um；
The SiO2Anti-reflection film (12) thickness is λ/4；
Described two SiN insulating barriers (13) width are 50um, thickness is λ/4；
Second transparency electrode (14) is the indium tin oxide transparency electrode that thickness is 0.3um；
Two the 3rd layer gold (15) thickness are 0.3um.
Further, second transparency electrode (14) light-emitting window is circular or square.
Further, the first transparency electrode (10) and the second transparency electrode (14) are ZnO transparency electrodes.
Beneficial effect：
The piezoelectric modulation vertical cavity semiconductor laser structure of the present invention, it, which is changed into, makes SiO2Anti-reflection film both sides are plated with Electrode, and the SiO of normal vertical cavity semiconductor laser2Anti-reflection film only has side to have electrode.Because exiting surface anti-reflection film SiO2Tool There is piezoelectric property, when in its upper and lower surface making alive, SiO2Anti-reflection film can deform upon, so that vertical cavity semiconductor swashs The chamber of light device is changed into on-plane surface unsteady cavity from plane stability chamber, changes the power output of vertical cavity semiconductor laser.With applying Alive difference, the deformation degree of anti-reflection film change, and the deformation degree of laser chamber changes therewith, realize pair The modulation of vertical cavity semiconductor laser power output.
Brief description of the drawings
Fig. 1 is the piezoelectric modulation vertical cavity semiconductor laser structure schematic diagram of the present invention.
Wherein reference is：
Single-chip substrate -1；
Cushion -2；
N-type DBR speculums -3；
Carrier lower limit layer -4；
Gain region -5；
Carrier upper limiting layer -6；
Photoelectricity limiting layer -7；
P-type DBR speculums -8；
Ohmic electrode contact layer -9；
First transparency electrode -10；
Second layer gold -11；
SiO2Anti-reflection film -12；
SiN insulating barriers -13；
Second transparency electrode -14；
3rd layer gold -15；
First layer gold -16.
Embodiment
The piezoelectric modulation vertical cavity semiconductor laser structure that the present invention uses is：Using MOCVD (Organometallic Chemistry gas Mutually deposit) epitaxial growth method.As shown in Figure 1：
In n-GaAs (100) (Si that width is 250um:2x1018/cm2) growth thickness is 0.5um on single-chip substrate 1 N-GaAs (Si:2x1018/cm2) cushion 2；
In n-GaAs (Si:2x1018/cm2) Al that the cycles of 20 couples of λ/4 repeat is grown on cushion 20.9Ga0.1As (81.7nm)/GaAs(69.6nm)(Si:2x1018/cm2), form n-type DBR speculums 3；
Growth thickness is 72.3nm n-Al on n-type speculum 30.2Ga0.8As(Si:1×1018/cm3) carrier lower limit Preparative layer 4；
Gain region 5 (trap material In of the growth with 3 SQWs on carrier lower limit layer 40.2Ga0.8As thickness For 8nm, barrier material is that GaAs thickness is 10nm)；
Growth thickness is 72.3nm p-Al on gain region 50.2Ga0.8As(C:1×1018/cm3) carrier upper limiting layer 6；
Growth thickness is 30nm AlAs (C on carrier upper limiting layer 6:2×1018/cm3) photoelectricity limiting layer 7；
The Al of 29.5 couples of λ/4 cycles repetition is grown on photoelectricity limiting layer 70.9Ga0.1As(81.7nm)/GaAs(69.6nm) (C:2×1018/ cm3), form p-type DBR speculums 8；
Growth thickness is 139.2nm highly-doped p-type GaAs (C on p-type DBR speculums 8:4×1019/cm3) Ohmic electrode Contact layer 9；
Ohmic electrode contact layer 9 central area evaporation width be 50um, the ITO (tin indium oxide) that thickness is 0.3um Transparency electrode 10；
The second thick layer gold 11 of 0.3um, the first layer gold 16, lining is deposited respectively below the both sides of transparency electrode 10 and substrate 1 Beneath the first layer gold of side 16 is wide with substrate, and the width of the second layer gold of transparency electrode both sides 11 is 100um；
Sputtering is wide with transparency electrode in first transparency electrode 10, and both sides are respectively with first transparency electrode both sides same Vertical plane, the SiO that thickness is λ/42Anti-reflection film 12；
In SiO2The both sides secondary epitaxy growth width of anti-reflection film 12 is 50um, the SiN insulating barriers 13 that thickness is λ/4；
In SiO2On anti-reflection film 12 be deposited it is wide with anti-reflection film, both sides respectively with anti-reflection film both sides same vertical plane, Thickness is 0.3um ITO (tin indium oxide) second transparency electrode 14；
In the both sides of second transparency electrode 14, the 3rd thick evaporation 0.3um layer gold 15, completes the vertical cavity semiconductor of piezoelectric modulation The growth of laser.
Wherein 29.5 couples of Al0.9Ga0.1As/GaAs(C:2×1018/cm3) cycle of λ/4 is repeatedly formed p-type DBR speculums, instead It is 980nm to penetrate spectrum centre wavelength, reflectivity 99.9%.Circular, side can be made in second transparency electrode (14) light-emitting window Shape etc. is variously-shaped；
Because exiting surface anti-reflection film SiO2With piezoelectric property, when in its upper and lower surface making alive, SiO2Anti-reflection film can be sent out Raw deformation, so as to change so that the chamber of vertical cavity semiconductor laser is changed into on-plane surface unsteady cavity from plane stability chamber, change is hung down The power output of straight cavity semiconductor laser.With alive difference is applied, the deformation degree of anti-reflection film changes, laser The deformation degree of chamber changes therewith, realizes the modulation to vertical cavity semiconductor laser power output.Therefore at work, In SiO2The electrode making alive of both sides, size is obtained by regulation voltage level, you can realizes and vertical cavity semiconductor laser is exported The modulation of power.
Certainly, the present invention can also have other various embodiments, ripe in the case of without departing substantially from spirit of the invention and its essence Know those skilled in the art when can be made according to the present invention it is various it is corresponding change and deformation, but these corresponding change and become Shape should all belong to the protection domain of appended claims of the invention.

Claims (5)

  1. A kind of 1. piezoelectric modulation vertical cavity semiconductor laser structure, it is characterised in that including：
    Single-chip substrate (1), cushion (2), n-type DBR speculums (3), carrier lower limit layer (4), gain region (5), current-carrying Sub- upper limiting layer (6), photoelectricity limiting layer (7), p-type DBR speculums (8), Ohmic electrode contact layer (9), first transparency electrode (10), two the second layer gold (11), SiO2Anti-reflection film (12), two SiN insulating barriers (13), second transparency electrode (14), two 3rd layer gold (15), the first layer gold (16)；
    Wherein, single-chip substrate (1), cushion (2), n-type DBR speculums (3), carrier lower limit layer (4), gain region (5), Carrier upper limiting layer (6), photoelectricity limiting layer (7), p-type DBR speculums (8) and Ohmic electrode contact layer (9) are wide；
    And first layer gold (16) is deposited below the single-chip substrate (1)；Above the single-chip substrate (1) successively Generate cushion (2), n-type DBR speculums (3), carrier lower limit layer (4), gain region (5), carrier upper limiting layer (6), Photoelectricity limiting layer (7), p-type DBR speculums (8) and Ohmic electrode contact layer (9)；
    Further, the first transparency electrode (10) is deposited in the central area of the Ohmic electrode contact layer (9)；Described two Individual second layer gold (11) is deposited on the Ohmic electrode contact layer (9) and being located at the first transparency electrode (10) two respectively Side；And the overall width of the first transparency electrode (10) and described two second layer gold (11) and single-chip substrate (1) width phase Together；
    The SiO2Anti-reflection film (12) secondary epitaxy is grown in the first transparency electrode (10), and the SiO2Anti-reflection film (12) wide with the first transparency electrode (10), both sides are respectively with the first transparency electrode (10) both sides same vertical flat Face；
    Described two SiN insulating barriers (13) are grown on described two second layer gold (11) and are located at the SiO respectively2Anti-reflection film (12) both sides；
    The second transparency electrode (14) is deposited in the SiO2On anti-reflection film (12), and the second transparency electrode (14) and institute State SiO2Anti-reflection film (12) is wide, and both sides respectively with the SiO2Anti-reflection film (12) both sides are in same vertical plane；
    Described two 3rd layer gold (15) are grown on described two SiN insulating barriers and are located at the second transparency electrode respectively (14) both sides, described two 3rd layer gold (15) and described two SiN insulating barriers (13) are wide.
  2. 2. piezoelectric modulation vertical cavity semiconductor laser structure as claimed in claim 1, it is characterised in that
    The single-chip substrate (1) is the n-GaAs that width is 250um, and n-GaAs crystal face is (100), and Si's mixes in n-GaAs Miscellaneous concentration is 2x1018/cm3；
    The cushion (2) is the n-GaAs that thickness is 0.5um, and Si doping concentration is 2x10 in n-GaAs18/cm3；
    The n-type DBR speculums (3) are by the Al of 20 couples of λ/4 cycles repetition0.9Ga0.1As/GaAs is formed, Al0.9Ga0.1As's Thickness is 81.7nm, and GaAs thickness is 69.6nm, and Si doping concentration is 2x10 in GaAs18/cm3；
    The carrier lower limit layer (4) is the n-Al that thickness is 72.3nm0.2Ga0.8As, n-Al0.2Ga0.8Si doping in As Concentration is 1x1018/cm3；
    The gain region (5) includes 3 SQWs, and trap material is In0.2Ga0.8As thickness is 8nm, and barrier material is GaAs thick Spend for 10nm；
    The carrier upper limiting layer (6) is the p-Al that thickness is 72.3nm0.2Ga0.8As, p-Al0.2Ga0.8C doping is dense in As Spend for 1 × 1018/cm3；
    The photoelectricity limiting layer (7) is the AlAs that thickness is 30nm, and C doping concentration is 2 × 10 in AlAs18/cm3；
    The Al that the p-type DBR speculums (8) are repeated by the cycles of 29.5 couples of λ/40.9Ga0.1As/GaAs is formed, Al0.9Ga0.1As's Thickness is 81.7nm, and GaAs thickness is 69.6nm, and C doping concentration is 2x10 in GaAs18/cm3；
    The Ohmic electrode contact layer (9) is the p-type GaAs that thickness is 139.2nm, and Ohmic electrode contact layer, C's mixes in GaAs Miscellaneous concentration is 4 × 1019/cm3。
  3. 3. piezoelectric modulation vertical cavity semiconductor laser structure as claimed in claim 2, it is characterised in that
    The first transparency electrode (10) is the indium tin oxide transparency electrode that width is 50um, thickness is 0.3um；
    The thick 0.3um of described two second layer gold (11), width 100um；
    The SiO2Anti-reflection film (12) thickness is λ/4；
    Described two SiN insulating barriers (13) width are 50um, thickness is λ/4；
    Second transparency electrode (14) is the indium tin oxide transparency electrode that thickness is 0.3um；
    Two the 3rd layer gold (15) thickness are 0.3um.
  4. 4. piezoelectric modulation vertical cavity semiconductor laser structure as claimed in claim 1, it is characterised in that
    Second transparency electrode (14) light-emitting window is circular or square.
  5. 5. piezoelectric modulation vertical cavity semiconductor laser structure as claimed in claim 1, it is characterised in that
    The first transparency electrode (10) and the second transparency electrode (14) are ZnO transparency electrodes.
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CN106953233A (en) * 2017-05-18 2017-07-14 北京工业大学 A kind of upside-down mounting vertical cavity semiconductor laser structure
CN108110615A (en) * 2017-11-29 2018-06-01 北京工业大学 A kind of small-bore vertical cavity semiconductor laser structure
CN113839304A (en) * 2021-07-30 2021-12-24 湖北光安伦芯片有限公司 Non-oxidation process micron column array high-power VCSEL structure and preparation method thereof

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