CN104299648A - Read only memory unit of differential structure - Google Patents
Read only memory unit of differential structure Download PDFInfo
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- CN104299648A CN104299648A CN201410495362.2A CN201410495362A CN104299648A CN 104299648 A CN104299648 A CN 104299648A CN 201410495362 A CN201410495362 A CN 201410495362A CN 104299648 A CN104299648 A CN 104299648A
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Abstract
The invention discloses a read only memory unit of a differential structure. Each unit comprises four bit line branches BL1, BL1B, BL2 and BL2B and a word line WL, wherein a differential pair is formed by the branch BL1 and the branch BL1B; a differential pair is formed by the branch BL2 and the branch BL2B; each differential pair shears two MOS field effect transistors. Due to the adoption of the technical scheme, the current range distinguished by a device during reading is expanded to a certain extent by the differential structure BOM unit; the two branches are compared and input into a differential amplifier during reading; the problem of mismatching caused by a reference circuit can be avoided; the reading stability is greatly improved; the read only memory unit of the differential structure has a wide market application prospect.
Description
Technical field
The present invention relates to a kind of semiconductor storage unit, be specifically related to a kind of read-only storage of differential architecture (ROM) unit of improvement.
Background technology
Along with developing rapidly of microelectric technique and computer technology, we are just marching toward an information society.Information society be unable to do without the storage of information.Since nearly half a century, people constantly explore storage new technology, define storer family various in style.Existing storer kind is a lot, from access facility aspect, they can be divided into read-only (Read Only Memory, ROM) storer and the large class of random (Random Access Memory, RAM) storer two.
ROM storer wherein in working order under, therefrom can only read data, and after power-off, data can not disappear, belong to semiconductor non-volatile storer (Non-Volatile Semiconductor Memory) category.
Traditional ROM storer is formed with one and multiple NMOS tube, and using a NMOS tube as elementary cell.As shown in Figure 1, its source ground (GND), drain electrode connects or is free of attachment to bit line (Bit Line, BL) traditional ROM storage unit, and grid is connected to wordline (Word Line, WL).Traditional data " 0 " are by receiving bit line to realize programming by the drain electrode of NMOS, traditional data " 1 " are not by receiving bit line to realize programming by the drain electrode of NMOS.
In general, such programming utilizes the front end layer of the nmos pass transistor forming ROM cell to realize, so as in ROM device integrated ROM cell more to high-density.Usually the programming of through hole (Contact) mask plate or the programming of active area (Diffusion) mask plate is utilized to realize.
Along with the development of integrated circuit technology in recent years, be limited to process rule, the area of ROM basic unit of storage cannot be accomplished to follow process scaled down, and unit storage unit area is larger.Along with the progress of technique, the read operation of ROM also faces the challenge, and during read operation, differentiable range of current is also more and more less, and the limitation of range of current seriously limits the impedance selection of reference circuit, is easy to bring impedance mismatch problem, causes read error.
In view of this, be necessary that the differential architecture ROM memory cell structure proposing a kind of improvement is to optimize these problems.
Summary of the invention
For overcoming deficiency of the prior art, the invention provides a kind of differential architecture read-only memory unit, on the basis of traditional ROM storage unit, two branch road contrast input difference amplifiers are adopted during reading, avoid the mismatch problem adopting reference circuit to bring, drastically increase the stability of reading.
For realizing above-mentioned technical purpose, reach above-mentioned technique effect, the present invention is achieved through the following technical solutions:
A kind of differential architecture read-only memory unit, it is characterized in that, each unit comprises four bit lines branch road BL1, BL1B, BL2 and BL2B, and a wordline WL, differential pair is formed between described branch road BL1 and branch road BL1B, form differential pair between described branch road BL2 and branch road BL2B, between each differential pair, share two MOS field effect transistors;
Described MOS field effect transistor comprises grid, source electrode and drain electrode, two
The grid of MOS field effect transistor connects wordline WL jointly, source ground;
The differential pair be made up of branch road BL1 and branch road BL1B, the drain electrode of one of them MOS field effect transistor connects branch road BL1, and the drain electrode of another MOS field effect transistor connects branch road BL1B;
The differential pair be made up of branch road BL2 and branch road BL2B, the drain electrode of one of them MOS field effect transistor connects branch road BL2, and the drain electrode of another MOS field effect transistor connects branch road BL2B.
Further, in the differential pair that described branch road BL1 and branch road BL1B is formed, the drain electrode of a MOS field effect transistor and bit line branch road are connection status, and the drain electrode of another MOS field effect transistor is not-connected status with bit line branch road.
Further, in the differential pair that described branch road BL2 and branch road BL2B is formed, the drain electrode of a MOS field effect transistor and bit line branch road are connection status, and the drain electrode of another MOS field effect transistor is not-connected status with bit line branch road.
Further, described MOS field effect transistor comprises grid, the the 1st and the 2nd doped semiconductor area below the gate medium of grid and gate medium, there is the grid of a conductive structure and MOS field effect transistor described 1st and the 2nd doped semiconductor area respectively as the source electrode of metal-oxide-semiconductor and the described MOS field effect transistor of drain electrode, one deck ultra-thin medium below conductive structure, the 1st doped semiconductor area below conductive structure, 1st and the 2nd doped semiconductor area of described MOS field effect transistor spatially separates and determines channel region therebetween, the wordline of the grid of described MOS field effect transistor device as a whole, the bit line of the drain electrode of described MOS field effect transistor device as a whole.
The invention has the beneficial effects as follows:
1, the present invention adopts differential architecture, and two branch roads input sense amplifier as differential pair, and the range of current distinguished thus during read operation can reach maximum.Meanwhile, because two branch roads store " 0 " and " 1 " respectively, thus under the prerequisite meeting read operation speed and accuracy, moderately can reduce the size of storage unit MOS element, ROM storage array area for cutting can well be optimized like this.
2, the present invention adopts symmetric difference framework, and the impedance matching of storage unit branch road is better, and stability is higher.For existing storage unit, usually adopt a reference circuit as with reference to branch road during reading, be input in sense amplifier together with bit line BL.The impedance of this branch road must when when storage unit deposits 0, BL holds equiva lent impedance and storage unit to deposit 1 in the middle of equiva lent impedance, the necessary careful design of reference arm here, not so be easy to cause mistake, and for the differential configuration that the present invention proposes, two bit lines branch roads are all identical structures, the resistance value also certainly equiva lent impedance and changing between equiva lent impedance when depositing 1 when depositing 0, thus do not worry resistance matching problem, the stability of storage unit also can be protected.
Accompanying drawing explanation
Accompanying drawing described herein is used to provide a further understanding of the present invention, and form a application's part, schematic description and description of the present invention, for explaining the present invention, does not form inappropriate limitation of the present invention.In the accompanying drawings:
Fig. 1 is traditional ROM memory cell structure schematic diagram;
Fig. 2 is ROM memory cell structure schematic diagram of the present invention.
Embodiment
Below with reference to the accompanying drawings and in conjunction with the embodiments, describe the present invention in detail.
With reference to shown in Fig. 2, a kind of differential architecture read-only memory unit, wherein, each unit comprises four bit lines branch road BL1, BL1B, BL2 and BL2B, and a wordline WL, form differential pair between described branch road BL1 and branch road BL1B, between described branch road BL2 and branch road BL2B, form differential pair, share two MOS field effect transistors between each differential pair, in the present embodiment, two MOS field effect transistors are respectively M1 pipe and M2 pipe;
M1 pipe and M2 pipe all comprise grid, source electrode and drain electrode, and M1 pipe is connected wordline WL jointly with the grid of M2 pipe, and source electrode is ground connection all.
In the differential pair that branch road BL1 and branch road BL1B is formed, wherein the drain electrode of M2 pipe is not connected with bit line branch road BL1, the drain electrode of M1 pipe is connected with bit line branch road BL1B, in the present embodiment, can realize allowing both (drain electrode and bit line) connect with metal level or through hole, also can realize not connecting, be similar to switch, select any, determine according to concrete technology.
In the differential pair that branch road BL2 and branch road BL2B is formed, wherein the drain electrode of M2 pipe is not connected with bit line branch road BL2, the drain electrode of M1 pipe is connected with bit line branch road BL2B, in the present embodiment, can realize allowing both (drain electrode and bit line) connect with metal level or through hole, also can realize not connecting, be similar to switch, select any, determine according to concrete technology.
Described MOS field effect transistor comprises grid, the the 1st and the 2nd doped semiconductor area below the gate medium of grid and gate medium, there is the grid of a conductive structure and MOS field effect transistor described 1st and the 2nd doped semiconductor area respectively as the source electrode of metal-oxide-semiconductor and the described MOS field effect transistor of drain electrode, one deck ultra-thin medium below conductive structure, the 1st doped semiconductor area below conductive structure, 1st and the 2nd doped semiconductor area of described MOS field effect transistor spatially separates and determines channel region therebetween, the wordline of the grid of described MOS field effect transistor device as a whole, the bit line of the drain electrode of described MOS field effect transistor device as a whole.
Principle of the present invention:
Continue shown in composition graphs 2, when bit line chooses BL1 and BL1B differential pair, two bit lines BL1 and BL1B charge to high level by pre-charge circuit, M1 pipe and M2 pipe are all standard MOS field effect transistors, open when M1 manages the wordline WL be connected with the grid of M2 pipe, the drain electrode of M2 pipe is not connected to BL1, discharge operation can not be carried out by pairs of bit line BL1, namely bit line BL1 keeps original level, M1 pipe is opened and is carried out discharge operation to BL1B, BL1B level reduces, at this moment certain voltage difference can be produced between BL1 and BL1B, we define this state is deposited data " 1 " in read only memory ROM, i.e. One_cell, at this moment by BL1 and BL1B input difference sensitive amplifier circuit, just can sense data fast and effectively.
In like manner, when bit line chooses BL2 and BL2B differential pair, two bit lines BL2 and BL2B charge to high level by pre-charge circuit, M1 pipe and M2 pipe are all standard MOS field effect transistors, open when M1 manages the wordline WL be connected with the grid of M2 pipe, the drain electrode of M2 pipe is not connected to BL2B, discharge operation can not be carried out by pairs of bit line BL2B, namely bit line BL2B keeps original level, M1 pipe is opened and is carried out discharge operation to BL2, BL2 level reduces, at this moment certain voltage difference can be produced between BL2 and BL2B, we define this state is deposited data " 0 " in read only memory ROM, i.e. Zero_cell, at this moment by BL2 and BL2B input difference sensitive amplifier circuit, just can sense data fast and effectively.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (4)
1. a differential architecture read-only memory unit, it is characterized in that, each unit comprises four bit lines branch road BL1, BL1B, BL2 and BL2B, and a wordline WL, differential pair is formed between described branch road BL1 and branch road BL1B, form differential pair between described branch road BL2 and branch road BL2B, between each differential pair, share two MOS field effect transistors;
Described MOS field effect transistor comprises grid, source electrode and drain electrode, two
The grid of MOS field effect transistor connects wordline WL jointly, source ground;
The differential pair be made up of branch road BL1 and branch road BL1B, the drain electrode of one of them MOS field effect transistor connects branch road BL1, and the drain electrode of another MOS field effect transistor connects branch road BL1B;
The differential pair be made up of branch road BL2 and branch road BL2B, the drain electrode of one of them MOS field effect transistor connects branch road BL2, and the drain electrode of another MOS field effect transistor connects branch road BL2B.
2. differential architecture read-only memory unit according to claim 1, it is characterized in that, in the differential pair that described branch road BL1 and branch road BL1B is formed, the drain electrode of a MOS field effect transistor and bit line branch road are connection status, and the drain electrode of another MOS field effect transistor is not-connected status with bit line branch road.
3. differential architecture read-only memory unit according to claim 1, it is characterized in that, in the differential pair that described branch road BL2 and branch road BL2B is formed, the drain electrode of a MOS field effect transistor and bit line branch road are connection status, and the drain electrode of another MOS field effect transistor is not-connected status with bit line branch road.
4. according to claim 1, differential architecture read-only memory unit described in 2 or 3, it is characterized in that, described MOS field effect transistor comprises grid, the the 1st and the 2nd doped semiconductor area below the gate medium of grid and gate medium, there is the grid of a conductive structure and MOS field effect transistor described 1st and the 2nd doped semiconductor area respectively as the source electrode of metal-oxide-semiconductor and the described MOS field effect transistor of drain electrode, one deck ultra-thin medium below conductive structure, the 1st doped semiconductor area below conductive structure, 1st and the 2nd doped semiconductor area of described MOS field effect transistor spatially separates and determines channel region therebetween, the wordline of the grid of described MOS field effect transistor device as a whole, the bit line of the drain electrode of described MOS field effect transistor device as a whole.
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| CN201410495362.2A CN104299648B (en) | 2014-09-25 | 2014-09-25 | A kind of differential architecture read-only memory unit |
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| CN201410495362.2A CN104299648B (en) | 2014-09-25 | 2014-09-25 | A kind of differential architecture read-only memory unit |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1726562A (en) * | 2002-12-19 | 2006-01-25 | 恩艾斯克株式会社 | CMIS semiconductor nonvolatile storage circuit |
| US20080008019A1 (en) * | 2006-07-06 | 2008-01-10 | Texas Instruments Incorporated | High Speed Read-Only Memory |
| CN204178726U (en) * | 2014-09-25 | 2015-02-25 | 苏州宽温电子科技有限公司 | A kind of differential architecture read-only memory unit |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1726562A (en) * | 2002-12-19 | 2006-01-25 | 恩艾斯克株式会社 | CMIS semiconductor nonvolatile storage circuit |
| US20080008019A1 (en) * | 2006-07-06 | 2008-01-10 | Texas Instruments Incorporated | High Speed Read-Only Memory |
| CN204178726U (en) * | 2014-09-25 | 2015-02-25 | 苏州宽温电子科技有限公司 | A kind of differential architecture read-only memory unit |
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