CN103745750A - Improved difference framework OTP (one time programmable) storage unit based on fuse characteristic - Google Patents
Improved difference framework OTP (one time programmable) storage unit based on fuse characteristic Download PDFInfo
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- CN103745750A CN103745750A CN201310723106.XA CN201310723106A CN103745750A CN 103745750 A CN103745750 A CN 103745750A CN 201310723106 A CN201310723106 A CN 201310723106A CN 103745750 A CN103745750 A CN 103745750A
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Abstract
The invention discloses an improved difference framework OTP (one time programmable) storage unit based on a fuse characteristic. The unit comprises two branches which are respectively composed of an OTP storage unit which is connected in series with a transistor fuse, wherein bit lines of the two branches are utilized as a group of differential pairs to be input into a sensitive amplifier, and the data is read after comparison. The improved difference framework OTP storage unit provided by the invention has the advantages that a difference framework is adopted, the distinguishable electric current before and after programming is effectively expanded; in addition, the symmetrical difference framework is adopted, and thus the impedance matching of the branches of the storage unit is good, and the stability is high.
Description
Technical field
The present invention relates to memory area, be specifically related to a kind of improved differential architecture OTP storage unit based on fuse characteristics.
Background technology
Disposable programmable memory (OTP) is the one in nonvolatile memory, it can be for circuit application provides versatile and flexible and cheap solution, thereby be widely used in the fields such as data backup memory, code storage, initial information storage, the storage of RFID beacon information.
There is at present various structures can realize OTP function, wherein topmost structure is nmos pass transistor structure, an OTP structure as shown in Figure 2, comprises a nmos pass transistor and a mos capacitance, and both are connected by a larger area multi-crystal silicon floating bar coupling.One end of multi-crystal silicon floating bar is as the grid of NMOS, and the N-type diffusion region on the other end and substrate in P trap forms mos capacitance.N-type diffusion region is connected with polysilicon as the word line of OTP, and the drain electrode of NMOS is as the bit line of OTP, and the source electrode of NMOS is as the source line of OTP.Its principle is while not programming, if apply and read voltage at wordline bits line segment, due to the coupling influence of mos capacitance, the grid voltage of NMOS can exceed threshold voltage, unlatching work, thus obtain a larger electric current; And if wordline bits line applies very large program voltage, there is stronger hot carrier injection in nmos pass transistor now, because floating gate polysilicon does not have direct metal connecting line, thereby the charge carrier of these injections can not disappear but is trapped in polysilicon, there is very large skew in the threshold voltage that has so just caused nmos pass transistor, if at this moment add and read voltage, coupled voltages is not enough to open NMOS, and NMOS turn-offs.
But above-mentioned OTP storage unit needs mos capacitance to carry out coupled voltages, and need to be by the recently design programming voltage that is coupled, therefore the needed mos capacitance area of this framework is larger.Meanwhile, need to increase primary ions inject in word line end, more than once extra lithography step, has increased cost.
After 2000, researchist has turned to the emphasis of research the OTP storage architecture of single grid type, because this structure can, completely compatible to memory process and standard CMOS logic process, greatly reduce cost.
Afterwards, researchist had worked out again a kind of OTP parts based on serial transistor.2006, in patent US6678190, eMemory company proposed a kind of series connection pmos type OTP parts, and Fig. 4 is exactly its configuration diagram.Its principle of work is by the injection to floating gate charge, changes the threshold voltage of storage tube and then change it to open off state.2008, the people such as Ying-Je Chen are at document " A Novel 2-Bit/Cell p-Channel Logic Programmable Cell With Pure 90-nm CMOS Technology " (IEEE ELECTRON DEVICE LETTERS, AUGUST 2008, VOL. 29, NO. 8, pp:938-940) in issued a kind of otp memory of serial transistor type of employing SAN (Self-Aligned Nitride) structure.In the middle of its two grid, adopt a self aligned nitride memory node of low pressure chemical vapor deposition generation, as stored charge, thereby programming is exactly to utilize the high energy electron of energy interband to inject this node to realize storage.
But, in any case, it is exactly that it has inevitably introduced extra transistor that OTP storage unit based on serial transistor type has a fatefulue weakness, number of transistors object increases and makes device area become large like this, manufacturing cost has obviously also increased a lot, and this can serious development and the use that restricts this class storer.
Researchist has also focused on the dielectric breakdown type otp memory design based on fuse (efuse) and anti-fuse (antifuse) research emphasis.Efuse fuse programming normally utilizes the special electrical specification of fuse, adopts the excess current of the fuse of flowing through to cause its fusing, thereby make fuse resistor value be varied to several kilohms even higher by tens ohm, realizes programming.Antifuse Programming Principle and efuse's is just in time contrary, and anti-fuse has very high resistance adding before program voltage, and it is in hundreds of megaohm, and while adding program voltage, by high electrical breakdown, it is even lower that resistance is reduced to kilo-ohm rank, so just can realize storage purpose.Just based on they such characteristics, they at otp memory design field in occupation of important position.In the U.S. Pat 6927997 of 2005, just proposed a kind of three pipe antifuse storeies that are widely used now, its framework as shown in Figure 3.In the U.S. Pat 7638855 of 2009, propose to have invented the overall architecture that has provided anti-fuse memory design in the another kind of Antifuse One-time-programmable Nonvolatile Memory. US7642138 patent Split Channel Antifuse Array Architecture of 2010.It is comparatively quick that entirety is looked back the development of visible storage unit based on fuse or anti-fuse and device.
In addition, the otp memory being formed by fuse or anti-fuse, it is based on dielectric breakdown characteristics, this fuse characteristics is easy to hold and adjust when research and development are manufactured.Meanwhile, along with the progress in associated materials field, the required special material of fuse and anti-fuse memory also makes progress to some extent, and its storage unit can be utilized high pressure gate tube.The required high voltage of programming also can utilize the design of related peripheral circuit and optimization to solve.
Otp memory part based on fuse characteristics can with logic process compatibility, the manufacturing process of fuse is simple, again because the transistor size of its use is less, thereby the area occupying is less, is widely used, production cost is also lower.But the programming efficiency of such device is lower, before and after this device programming, differentiable range of current is very little.For sensitive and sense data rapidly, conventionally all adopt now differential amplifier circuit to be used as reading circuit.The limitation of range of current has seriously limited the impedance of reference circuit and has selected, and is easy to bring impedance mismatch problem, causes read error.
In view of this, be necessary to propose a kind of improved OTP memory cell structure and optimize these problems.
Summary of the invention
The object of the invention is to overcome the above problem that prior art exists, a kind of improved differential architecture OTP storage unit based on fuse characteristics is provided, on the basis of traditional OTP storage unit based on fuse characteristics, while reading, adopt two branch road contrast input difference amplifiers, avoid the mismatch problem that adopts reference circuit to bring, greatly improved the stability reading.
For realizing above-mentioned technical purpose, reach above-mentioned technique effect, the present invention is achieved through the following technical solutions:
Based on an improved differential architecture OTP storage unit for fuse characteristics, comprise tandem compound, source line SL control circuit module, bit line BL control circuit module and the sensitive amplifier circuit module of PMOS transistor and fuse.
Further, source line SL control circuit module and bit line BL control circuit module comprise a corresponding coding and decoding circuit, and described sensitive amplifier circuit module comprises data read functions module.
Further, PMOS transistor is as gate transistor, and the PMOS grid word line of device as a whole, with the pmos source source electrode of device as a whole; Fuse is as storage medium, and one end of described fuse is connected with the drain electrode of described PMOS, and the other end that described fuse is not connected with transistor is the bit line of device as a whole.
Further, the coding and decoding circuit of described source line SL control circuit module, by address signal control, provides the task of power supply when it also bears programming simultaneously; Coding and decoding circuit in described bit line BL control circuit module provides voltage signal.
The invention has the beneficial effects as follows:
1) the present invention adopts differential architecture, has effectively expanded the electric current distinguished before and after programming.
2) the present invention adopts symmetric difference framework, and the impedance matching of storage unit branch road is better, and stability is higher.
For existing storage unit, while reading, conventionally adopt a reference circuit as with reference to branch road, be input in sense amplifier together with bit line BL.The impedance of this branch road must be deposited 0 o'clock BL end equiva lent impedance and storage unit between storage unit and be deposited in the middle of 1 o'clock equiva lent impedance, and the reference arm here must careful design, is not so easy to cause mistake.And the differential configuration proposing for the present invention, two BL branch roads are all identical structures, resistance value also certainly changes between equiva lent impedance depositing 0 o'clock equiva lent impedance and deposit for 1 o'clock.Thereby do not worry resistance matching problem, the stability of storage unit also can be protected.
3) differential architecture OTP storage unit of the present invention has been used differential pair as a storage unit, thereby required transistor and fuse increase, but only use two transistors, the increase of area is limited, and the cost of fuse is lower, do not need extra technological process.
Differential architecture OTP unit can expand the differentiable range of current in device programming front and back to a certain extent, while reading, adopt two branch road contrast input difference amplifiers simultaneously, can avoid the mismatch problem that adopts reference circuit to bring, greatly improve the stability reading.This framework has very important Research Significance and wide market outlook.
Accompanying drawing explanation
Fig. 1 is the improved differential architecture OTP structural representation that the present invention is based on fuse characteristics;
Fig. 2 tradition nmos pass transistor OTP structural representation;
Fig. 3 is 3 pipe anti-fuse structures OTP structural representations;
Fig. 4 is transistor fuse tandem type OTP structural representation.
Embodiment
Below with reference to the accompanying drawings and in conjunction with the embodiments, describe the present invention in detail.
Shown in Fig. 4, a kind of improved differential architecture OTP storage unit based on fuse characteristics, comprises tandem compound, source line SL control circuit module, bit line BL control circuit module and the sensitive amplifier circuit module of PMOS transistor and fuse.
Further, source line SL control circuit module and bit line BL control circuit module comprise a corresponding coding and decoding circuit, and described sensitive amplifier circuit module comprises data read functions module.
Further, PMOS transistor is as gate transistor, and the PMOS grid word line of device as a whole, with the pmos source source electrode of device as a whole; Fuse is as storage medium, and one end of described fuse is connected with the drain electrode of described PMOS, and the other end that described fuse is not connected with transistor is the bit line of device as a whole.
Further, the coding and decoding circuit of described source line SL control circuit module, by address signal control, provides the task of power supply when it also bears programming simultaneously; Coding and decoding circuit in described bit line BL control circuit module provides voltage signal.
Embodiment:
Take the OTP storage unit of P transistor npn npn series connection fuse as example, this framework is composed in series by a PMOS transistor and a fuse, PMOS transistor is as gate transistor, and described PMOS transistor gate is the word line of device as a whole, the described PMOS transistor source source electrode of device as a whole; Described fuse is as the carrier of storage information, and described fuse one end is connected with the transistorized drain electrode of described PMOS, the bit line that one end that described fuse is not connected with transistor is integral device.The scheme providing at this is: adopt difference symmetrical structure, and transistor fuse tandem type OTP unit composition of every route, the bit line of two branch roads is input in sense amplifier as one group of differential pair, then contrasts sense data.
During programming state, work as V
sgsignal is during to low level, and word line selection is logical, storage unit work.If at this moment SL applies programming high pressure VPP, BL1 connects 0, BL2 meets VPP, left side MP1 and the work of R1 branch road, because programming high pressure (turning-on voltage of removing MP1 pipe falls) is carried in fuse R1 above, according to the electrical specification of fuse, can know that now the resistance value of its fusing is very big, can think that this branch road turn-offs, and as writing 0; The right branch road MP2 and R2 branch road are also worked, but because BL2 has connect high voltage, at this moment the voltage difference that is carried in fuse R2 two ends is very low, according to fuse characteristics, can know that now the resistance value of R2 is very low, and think and now write 1, at this moment we define overall difference storage architecture and are written into 0.In like manner, if SL applies programming high pressure VPP, BL2 connects 0, BL1 meets VPP, R2 both end voltage is poor very high, and resistance is very high, thinks that it disconnects this moment, be written into 0, and the voltage difference at R1 two ends is very little, R1 resistance is very low, thinks path this moment, be written into 1, and we define overall difference storage architecture and are written into 1 in this case.
During reading state, V
sggive low level, select the storage unit reading.At this moment SL applies and reads voltage VR, and BL1 and BL2 set to 0 simultaneously.If be placed in the high impedance status of fusing during the programming of the R1 in the branch road of the left side, and R2 is placed in low impedance state, at this moment obviously left side branch current I1 is more much smaller than the right branch current I2, by sense amplifier, exports, and can read 0.In like manner, while how to programme, R1 is placed in low impedance state and R2 is placed in fusing high impedance status, and at this moment the right branch current I2 is more much smaller than left side branch current I1 obviously, by sense amplifier, exports, and we can read 1.
Principle of the present invention:
1) the present invention adopts differential architecture, has effectively expanded the electric current distinguished before and after programming.For example, can define bit line BL1 branch road and deposit 0, bit line BL2 branch road is deposited 1 o'clock, and 0 state is stored in global storage unit.If at this moment reading out data, the fuse R1 of bit line BL1 branch road is placed in high impedance status, and I1 value is very little; The fuse R2 of bit line BL2 branch road is placed in low impedance state, and at this moment I2 is larger, by difference sense amplifier read current effectively.Equally, definition bit line BL1 branch road deposits 1, and bit line BL2 branch road is deposited 0 o'clock global storage 1 state.At this moment be that bit line BL1 branch road has certain electric current, almost no current of bit line BL2 branch road.It is maximum that electric current differentiate range at this time can reach.
2) the present invention adopts symmetric difference framework, and the impedance matching of storage unit branch road is better, and stability is higher.For existing storage unit, while reading, conventionally adopt a reference circuit as with reference to branch road, be input in sense amplifier together with bit line BL.The impedance of this branch road must be deposited 0 o'clock BL end equiva lent impedance and storage unit between storage unit and be deposited in the middle of 1 o'clock equiva lent impedance, and the reference arm here must careful design, is not so easy to cause mistake.And the differential configuration proposing for the present invention, two BL branch roads are all identical structures, resistance value also certainly changes between equiva lent impedance depositing 0 o'clock equiva lent impedance and deposit for 1 o'clock.Thereby do not worry resistance matching problem, the stability of storage unit also can be protected.
3) pipe and the fuse number of the described improved differential architecture OTP unit based on fuse characteristics increase to some extent, but the PMOS pipe size in this OTP storage unit is not very large, fuse dimension is not very large yet, thereby the area change of storage unit is limited.
The OTP unit of described novel differential architecture can expand the differentiable range of current in device programming front and back to a certain extent, while reading, adopt two branch road contrast input difference amplifiers simultaneously, avoid the mismatch problem that adopts reference circuit to bring, greatly improved the stability reading.
Claims (4)
1. the improved differential architecture OTP storage unit based on fuse characteristics, is characterized in that: the tandem compound, source line SL control circuit module, bit line BL control circuit module and the sensitive amplifier circuit module that comprise PMOS transistor and fuse.
2. the improved differential architecture OTP storage unit based on fuse characteristics according to claim 1, it is characterized in that: source line SL control circuit module and bit line BL control circuit module comprise a corresponding coding and decoding circuit, and described sensitive amplifier circuit module comprises data read functions module.
3. the improved differential architecture OTP storage unit based on fuse characteristics according to claim 1, is characterized in that: PMOS transistor is as gate transistor, and the PMOS grid word line of device as a whole, with the pmos source source electrode of device as a whole; Fuse is as storage medium, and one end of described fuse is connected with the drain electrode of described PMOS, and the other end that described fuse is not connected with transistor is the bit line of device as a whole.
4. the improved differential architecture OTP storage unit based on fuse characteristics according to claim 2, is characterized in that: the coding and decoding circuit of described source line SL control circuit module, by address signal control, provides the task of power supply when it also bears programming simultaneously; Coding and decoding circuit in described bit line BL control circuit module provides voltage signal.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108305662A (en) * | 2018-03-27 | 2018-07-20 | 苏州大学 | Improved differential architecture OTP memory cell based on fuse characteristics and memory |
| CN108511022A (en) * | 2018-03-27 | 2018-09-07 | 苏州大学 | Improved differential architecture Nor flash storage units based on series crystal type and memory |
| CN108701486A (en) * | 2016-01-08 | 2018-10-23 | 美商新思科技有限公司 | It is generated using the PUF values of antifuse memory array |
| CN112992245A (en) * | 2020-12-25 | 2021-06-18 | 上海华力微电子有限公司 | efuse unit structure, double-row structure of efuse unit and application circuit of efuse unit structure |
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| CN1679110A (en) * | 2002-07-05 | 2005-10-05 | 伊皮杰有限公司 | Differential floating gate nonvolatile memories |
| US20070064465A1 (en) * | 2005-09-16 | 2007-03-22 | Kabushiki Kaisha Toshiba | ROM storing information by using pair of memory cells |
| CN101253573A (en) * | 2005-08-31 | 2008-08-27 | 国际商业机器公司 | Random access electrically programmable-E-FUSE ROM |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1679110A (en) * | 2002-07-05 | 2005-10-05 | 伊皮杰有限公司 | Differential floating gate nonvolatile memories |
| CN101253573A (en) * | 2005-08-31 | 2008-08-27 | 国际商业机器公司 | Random access electrically programmable-E-FUSE ROM |
| US20070064465A1 (en) * | 2005-09-16 | 2007-03-22 | Kabushiki Kaisha Toshiba | ROM storing information by using pair of memory cells |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108701486A (en) * | 2016-01-08 | 2018-10-23 | 美商新思科技有限公司 | It is generated using the PUF values of antifuse memory array |
| CN108701486B (en) * | 2016-01-08 | 2022-03-11 | 美商新思科技有限公司 | PUF value generation using antifuse memory arrays |
| CN108305662A (en) * | 2018-03-27 | 2018-07-20 | 苏州大学 | Improved differential architecture OTP memory cell based on fuse characteristics and memory |
| CN108511022A (en) * | 2018-03-27 | 2018-09-07 | 苏州大学 | Improved differential architecture Nor flash storage units based on series crystal type and memory |
| CN112992245A (en) * | 2020-12-25 | 2021-06-18 | 上海华力微电子有限公司 | efuse unit structure, double-row structure of efuse unit and application circuit of efuse unit structure |
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