CN112992245A - efuse unit structure, double-row structure of efuse unit and application circuit of efuse unit structure - Google Patents
efuse unit structure, double-row structure of efuse unit and application circuit of efuse unit structure Download PDFInfo
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- CN112992245A CN112992245A CN202011562191.2A CN202011562191A CN112992245A CN 112992245 A CN112992245 A CN 112992245A CN 202011562191 A CN202011562191 A CN 202011562191A CN 112992245 A CN112992245 A CN 112992245A
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- fuse
- efuse
- nmos tube
- unit structure
- programming
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/18—Auxiliary circuits, e.g. for writing into memory
Abstract
The invention provides an efuse unit structure, a double-row structure of the efuse unit and an application circuit of the efuse unit structure, wherein the efuse unit structure comprises a programming fuse and a reference fuse; a first NMOS transistor and a second NMOS transistor; one end of the reference fuse is an SAref port of the efuse unit structure, and the other end of the reference fuse is connected with the drain electrode of the second NMOS tube; one end of the programming fuse is a bit line port of the efuse unit structure, and the other end of the programming fuse is connected with the drain electrode of the first NMOS tube; the grid electrodes of the first NMOS tube and the second NMOS tube are connected to form a word line port of an efuse unit structure; the source electrodes of the first NMOS tube and the second NMOS tube are connected to form a ground port of the efuse unit structure. The efuse unit structure of the invention adopts non-fusing programming operation on the fuse wire, reduces the requirement on the required programming current, can work under lower programming voltage and greatly reduces the power consumption of the system. Meanwhile, the small difference between the programming fuse and the reference fuse can be reliably compared, and a non-fusing mechanism is adopted, so that the required programming current is smaller, and the integral area of the efuse is reduced.
Description
Technical Field
The invention relates to the field of integrated circuit design, in particular to an efuse unit structure, a double-row structure of efuse units and an application circuit of the efuse unit structure.
Background
The efuses belong to one-time programmable memories (OTP), and realize a programming function by blowing fuses based on an electro-migration (EM) principle. The efuse internal read module converts the resistance value of the fuse into a corresponding logic value, and the working principle is that the fuse resistance before and after fusing is compared with the reference resistance through a comparison circuit to generate different levels. In order to ensure the reliability of the comparison result, the conventional efuse design desirably blows the fuse during the programming operation to obtain a larger resistance value. Therefore, the conventional efuse unit includes a control tube with a larger W/L size so as to pass a larger blowing current, which directly results in a larger efuse area and larger overall power consumption.
The conventional efuse cell realizes a programming operation by blowing a fuse based on the electromigration principle. The conventional efuse needs to adopt a higher programming voltage because the fusing current required by programming is larger; while in a read operation, the system uses a lower voltage to reduce power consumption. Therefore, the conventional efuse adopts a dual power supply (VDD, VDDQ) structure, as shown in fig. 1, fig. 1 is a circuit schematic diagram of the conventional efuse structure, and the programming current of the system is from VDDQ, through P1, link and N1 to ground during the programming operation, so as to realize the programming of the efuse. During a read operation of the system, a read current flows from VDD, SA, through the link and N1 to ground, and a current value related to the resistance of the efuse fuse (link) is converted into a logic output DO at SA (Sensor Amplifier).
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide an efuse cell structure, a dual-column structure of efuse cells, and an application circuit of efuse cell structure, which are used to solve the problems of large efuse area and large overall power consumption in the prior art.
To achieve the above and other related objects, the present invention provides an efuse cell structure, which at least includes:
a fuse pair consisting of a program fuse and a reference fuse; a first NMOS transistor and a second NMOS transistor; wherein one end of the reference fuse is an SAref port of the efuse cell structure; the other end of the reference fuse is connected with the drain electrode of the second NMOS tube; one end of the programming fuse is a bit line port of the efuse unit structure; the other end of the programming fuse is connected with the drain electrode of the first NMOS tube; the grids of the first NMOS tube and the second NMOS tube are mutually connected to form a word line port of the efuse unit structure; and the source electrodes of the first NMOS tube and the second NMOS tube are mutually connected to form a grounding port of the efuse unit structure.
The invention also provides a double-row structure of the efuse unit, which at least comprises the following components:
n efuse unit structures; the efuse unit structure includes: a fuse pair consisting of a program fuse and a reference fuse; a first NMOS transistor and a second NMOS transistor; wherein one end of the reference fuse is an SAref port of the efuse cell structure; the other end of the reference fuse is connected with the drain electrode of the second NMOS tube; one end of the programming fuse is a bit line port of the efuse unit structure; the other end of the programming fuse is connected with the drain electrode of the first NMOS tube; the grids of the first NMOS tube and the second NMOS tube are mutually connected to form a word line port of the efuse unit structure; the source electrodes of the first NMOS tube and the second NMOS tube are mutually connected to form a grounding port of the efuse unit structure;
a sense amplifier module SA; the sense amplifier module SA includes: a first differential input BL, a second differential input Ref and a logic output;
the N efuse unit structures are sequentially arranged into first to Nth efuse unit structures; the bit line ports of the first to nth effect cell structures are connected to each other and connected to a first differential input end BL of the sense amplifier module SA; the SAref ports of the first to nth effect cell structures are connected to each other and to a second differential input terminal Ref of the sense amplifier module SA.
The invention also provides an application circuit of the efuse unit structure, which at least comprises the following components:
an efuse cell structure; the efuse unit structure includes: a fuse pair consisting of a program fuse and a reference fuse; a first NMOS transistor and a second NMOS transistor; wherein one end of the reference fuse is an SAref port of the efuse cell structure; the other end of the reference fuse is connected with the drain electrode of the second NMOS tube; one end of the programming fuse is a bit line port of the efuse unit structure; the other end of the programming fuse is connected with the drain electrode of the first NMOS tube; the grids of the first NMOS tube and the second NMOS tube are mutually connected to form a word line port of the efuse unit structure; the source electrodes of the first NMOS tube and the second NMOS tube are mutually connected to form a grounding port of the efuse unit structure;
a sense amplifier module SA; the sense amplifier module SA includes: a first differential input end BL, a second differential input end Ref, a logic output end and a power supply end VDD;
PMOS programming control tube;
a bit line port of the efuse unit structure is connected with a first differential input end BL of the sense amplifier module SA and a drain of the PMOS programming control tube; the SAref port of the efuse unit structure is connected to the second differential input terminal Ref of the sense amplifier module SA.
Preferably, the source of the PMOS programming control tube is connected with a voltage VDD 1.
Preferably, the gate of the PMOS programming control tube is connected to the control signal Prog.
As described above, the efuse cell structure of the present invention has the following beneficial effects: the efuse unit structure of the invention reduces the requirement on the required programming current because of adopting the non-fusing programming operation on the fuse wire, thereby being capable of working under a lower programming voltage and greatly reducing the system power consumption. Meanwhile, the efuse unit structure adopts a fuse pair mode, so that the small difference between a programming fuse and a reference fuse can be reliably compared, and the programming current required by a non-fusing mechanism is smaller, so that the fuse and the control tube of the efuse unit can be smaller, and the integral area of the efuse is reduced.
Drawings
FIG. 1 is a circuit diagram showing a conventional efuse structure;
FIG. 2 is a circuit diagram illustrating an efuse cell structure according to the present invention;
FIG. 3 is a schematic circuit diagram illustrating a two-column structure of an efuse cell according to the present invention;
FIG. 4 is a schematic diagram of an applied circuit structure of the efuse cell structure of the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 4. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
The invention provides an efuse unit structure, which at least comprises:
a fuse pair consisting of a program fuse and a reference fuse; a first NMOS transistor and a second NMOS transistor; wherein one end of the reference fuse is an SAref port of the efuse cell structure; the other end of the reference fuse is connected with the drain electrode of the second NMOS tube; one end of the programming fuse is a bit line port of the efuse unit structure; the other end of the programming fuse is connected with the drain electrode of the first NMOS tube; the grids of the first NMOS tube and the second NMOS tube are mutually connected to form a word line port of the efuse unit structure; and the source electrodes of the first NMOS tube and the second NMOS tube are mutually connected to form a grounding port of the efuse unit structure.
As shown in FIG. 2, FIG. 2 is a circuit diagram illustrating an efuse cell structure according to the present invention; the efuse cell structure of the embodiment is a fuse pair consisting of a programming fuse (Link1) and a reference fuse (Link 2); a first NMOS transistor N1, a second NMOS transistor N2; wherein one end of the reference fuse Link2 is an SAref port (reference resistor output end) of the efuse cell structure; the other end of the reference fuse Link2 is connected with the drain of the second NMOS transistor N2; one end of the programming fuse Link1 is a bit line port BL of the efuse cell structure; the other end of the programming fuse Link1 is connected with the drain of the first NMOS transistor N1; the grids of the first NMOS tube and the second NMOS tube are mutually connected to form a word line port WL of the efuse unit structure; and the source electrodes of the first NMOS tube and the second NMOS tube are connected with each other to form a ground port GND of the efuse unit structure.
The efuse cell structure of the present invention adopts a new programming mechanism, i.e., a programming operation in a non-blowing mode is performed on a fuse. This mechanism requires that the electromigration process of the fuse be controlled so that the resistance of the fuse changes rather than causing the fuse to blow. Since the electromigration occurs at different current and time stages, the resistance value of the fuse changes in a larger range, the efuse unit structure of the invention takes a fuse without electromigration as a comparison reference, and the difference of the resistance values between the programmed fuse and the reference fuse is directly compared through a differential structure in the sense amplifier module SA, so as to obtain a correct logic output value.
The invention also provides a double-row structure of the efuse unit, which at least comprises the following components:
n efuse unit structures; the efuse unit structure includes: a fuse pair consisting of a program fuse and a reference fuse; a first NMOS transistor and a second NMOS transistor; wherein one end of the reference fuse is an SAref port of the efuse cell structure; the other end of the reference fuse is connected with the drain electrode of the second NMOS tube; one end of the programming fuse is a bit line port of the efuse unit structure; the other end of the programming fuse is connected with the drain electrode of the first NMOS tube; the grids of the first NMOS tube and the second NMOS tube are mutually connected to form a word line port of the efuse unit structure; the source electrodes of the first NMOS tube and the second NMOS tube are mutually connected to form a grounding port of the efuse unit structure;
a sense amplifier module SA; the sense amplifier module SA includes: a first differential input BL, a second differential input Ref and a logic output;
the N efuse unit structures are sequentially arranged into first to Nth efuse unit structures; the bit line ports of the first to nth effect cell structures are connected to each other and connected to a first differential input end BL of the sense amplifier module SA; the SAref ports of the first to nth effect cell structures are connected to each other and to a second differential input terminal Ref of the sense amplifier module SA.
As shown in FIG. 3, FIG. 3 is a schematic circuit diagram of a dual-column structure of an efuse cell according to the present invention, where the dual-column structure of the efuse cell includes: n efuse unit structures; wherein each efuse unit structure comprises: a fuse pair consisting of a program fuse and a reference fuse; a first NMOS transistor and a second NMOS transistor; wherein one end of the reference fuse is an SAref port of the efuse cell structure; the other end of the reference fuse is connected with the drain electrode of the second NMOS tube; one end of the programming fuse is a bit line port of the efuse unit structure; the other end of the programming fuse is connected with the drain electrode of the first NMOS tube; the grids of the first NMOS tube and the second NMOS tube are mutually connected to form a word line port of the efuse unit structure; the source electrodes of the first NMOS tube and the second NMOS tube are mutually connected to form a grounding port of the efuse unit structure;
a sense amplifier module SA; the sense amplifier module SA includes: a first differential input BL, a second differential input Ref and a logic output DO;
the N efuse unit structures are sequentially arranged into first to Nth efuse unit structures; the bit line ports BL of the first to nth effect cell structures are connected to each other and connected to a first differential input terminal BL of the sense amplifier module SA; the SAref ports of the first to nth effect cell structures are connected to each other and to a second differential input terminal Ref of the sense amplifier module SA.
The word line ports corresponding to the first to Nth efuse cell structures are a first word line port WL1 to an Nth word line port WLn;
the invention adopts a non-fusing mechanism to carry out programming operation, although the resistance change of the fuse wire which generates electromigration is smaller, the fuse wire pair of the programming fuse wire and the reference fuse wire is arranged in the efuse unit, and the slight change of the resistance value of the fuse wire is converted into logic change through SA by utilizing the deviation of the resistance values of the programming fuse wire and the reference fuse wire. As shown in fig. 3, the reference array and the memory array formed by the fuse pairs in the cells on the same column have the same physical characteristics and variation states because they are constructed in the same and co-located in the same region, and thus can mutually cancel the influence of the process variation.
As shown in fig. 4, fig. 4 is a schematic diagram of an application circuit structure of an efuse cell structure of the present invention, and the application circuit structure at least includes:
an efuse cell structure; the efuse unit structure includes: a fuse pair consisting of a program fuse and a reference fuse; a first NMOS transistor and a second NMOS transistor; wherein one end of the reference fuse is an SAref port of the efuse cell structure; the other end of the reference fuse is connected with the drain electrode of the second NMOS tube; one end of the programming fuse is a bit line port of the efuse unit structure; the other end of the programming fuse is connected with the drain electrode of the first NMOS tube; the grids of the first NMOS tube and the second NMOS tube are mutually connected to form a word line port of the efuse unit structure; the source electrodes of the first NMOS tube and the second NMOS tube are mutually connected to form a grounding port of the efuse unit structure;
the application circuit of the efuse cell structure further comprises: a sense amplifier module SA; the sense amplifier module SA includes: a first differential input end BL, a second differential input end Ref, a logic output end and a power supply end VDD;
the application circuit of the efuse cell structure further comprises: PMOS program control pipe P1;
a bit line port BL of the efuse cell structure is connected to a first differential input end BL of the sense amplifier module SA and a drain of the PMOS programming control transistor P1; the SAref port of the efuse unit structure is connected to the second differential input terminal Ref of the sense amplifier module SA.
Further, the source of the PMOS programming control transistor of the present embodiment is connected to the voltage VDD 1. Still further, the gate of the PMOS programming control transistor of this embodiment is connected to the control signal Prog. The efuse structure of the present invention shown in fig. 4 switches SAref of the reference fuse in the fuse pair of the efuse cell into SA, so as to ensure that an accurate comparison reference is provided for the programmed fuse resistance on BL during the read operation.
The efuse of the invention reduces the requirement on the required programming current because of adopting the non-fusing programming operation on the fuse wire, thereby being capable of working under a lower programming voltage and greatly reducing the power consumption of a system. Meanwhile, the efuse unit adopts a fuse pair mode, so that the small difference between the programming fuse and the reference fuse can be reliably compared, and the programming current required by adopting a non-fusing mechanism is smaller, so that the fuse and the control tube of the efuse unit can be smaller, and the whole area of the efuse is reduced.
The basic application structure of the efuse unit of the invention is shown in fig. 4. It can be seen that the WL signal on the WL port of the efuse unit controls the gate terminals of the N1 and N2 tubes, as with the conventional efuse in FIG. 1. The BL terminal of the efuse unit is respectively connected to the SA module and the drain terminal of the PMOS programming control transistor P1. In a programming operation, the Prog signal controls the programming current from VDD1, P1 transistor, programming fuse and N1 to ground. The reference current of the SA block is connected to ground through the reference fuse and the N2 transistor, which provides an accurate comparison reference for the programmed fuse resistance on BL during read operation and outputs the comparison result from DO of the SA block. In contrast, the conventional efuse does not rely on an external reference fuse for making a comparison resistor, but utilizes a reference resistor inside the SA module.
In summary, the efuse cell structure, the double-column structure of the efuse cell, and the application circuit of the efuse cell structure of the present invention reduce the requirement for the required programming current by applying the non-fusing programming operation to the fuse, and therefore, can operate at a lower programming voltage, so that the power consumption of the system is greatly reduced. Meanwhile, the efuse unit structure adopts a fuse pair mode, so that the small difference between a programming fuse and a reference fuse can be reliably compared, and the programming current required by a non-fusing mechanism is smaller, so that the fuse and the control tube of the efuse unit can be smaller, and the integral area of the efuse is reduced. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (5)
1. An efuse cell structure, comprising at least:
a fuse pair consisting of a program fuse and a reference fuse; a first NMOS transistor and a second NMOS transistor; wherein one end of the reference fuse is an SAref port of the efuse cell structure; the other end of the reference fuse is connected with the drain electrode of the second NMOS tube; one end of the programming fuse is a bit line port of the efuse unit structure; the other end of the programming fuse is connected with the drain electrode of the first NMOS tube; the grids of the first NMOS tube and the second NMOS tube are mutually connected to form a word line port of the efuse unit structure; and the source electrodes of the first NMOS tube and the second NMOS tube are mutually connected to form a grounding port of the efuse unit structure.
2. A double-column structure of an efuse unit is characterized by at least comprising:
n efuse unit structures; the efuse unit structure includes: a fuse pair consisting of a program fuse and a reference fuse; a first NMOS transistor and a second NMOS transistor; wherein one end of the reference fuse is an SAref port of the efuse cell structure; the other end of the reference fuse is connected with the drain electrode of the second NMOS tube; one end of the programming fuse is a bit line port of the efuse unit structure; the other end of the programming fuse is connected with the drain electrode of the first NMOS tube; the grids of the first NMOS tube and the second NMOS tube are mutually connected to form a word line port of the efuse unit structure; the source electrodes of the first NMOS tube and the second NMOS tube are mutually connected to form a grounding port of the efuse unit structure;
a sense amplifier module SA; the sense amplifier module SA includes: a first differential input BL, a second differential input Ref and a logic output;
the N efuse unit structures are sequentially arranged into first to Nth efuse unit structures; the bit line ports of the first to nth effect cell structures are connected to each other and connected to a first differential input end BL of the sense amplifier module SA; the SAref ports of the first to nth effect cell structures are connected to each other and to a second differential input terminal Ref of the sense amplifier module SA.
3. An application circuit of an efuse cell structure, comprising at least:
an efuse cell structure; the efuse unit structure includes: a fuse pair consisting of a program fuse and a reference fuse; a first NMOS transistor and a second NMOS transistor; wherein one end of the reference fuse is an SAref port of the efuse cell structure; the other end of the reference fuse is connected with the drain electrode of the second NMOS tube; one end of the programming fuse is a bit line port of the efuse unit structure; the other end of the programming fuse is connected with the drain electrode of the first NMOS tube; the grids of the first NMOS tube and the second NMOS tube are mutually connected to form a word line port of the efuse unit structure; the source electrodes of the first NMOS tube and the second NMOS tube are mutually connected to form a grounding port of the efuse unit structure;
a sense amplifier module SA; the sense amplifier module SA includes: a first differential input end BL, a second differential input end Ref, a logic output end and a power supply end VDD;
PMOS programming control tube;
a bit line port of the efuse unit structure is connected with a first differential input end BL of the sense amplifier module SA and a drain of the PMOS programming control tube; the SAref port of the efuse unit structure is connected to the second differential input terminal Ref of the sense amplifier module SA.
4. The application circuit of the efuse cell structure according to claim 3, wherein: the source of the PMOS programming control tube is connected with a voltage VDD 1.
5. The efuse cell structure of claim 4, wherein: and the grid electrode of the PMOS programming control tube is connected with a control signal Prog.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011562191.2A CN112992245A (en) | 2020-12-25 | 2020-12-25 | efuse unit structure, double-row structure of efuse unit and application circuit of efuse unit structure |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011562191.2A CN112992245A (en) | 2020-12-25 | 2020-12-25 | efuse unit structure, double-row structure of efuse unit and application circuit of efuse unit structure |
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| CN112992245A true CN112992245A (en) | 2021-06-18 |
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| CN202011562191.2A Pending CN112992245A (en) | 2020-12-25 | 2020-12-25 | efuse unit structure, double-row structure of efuse unit and application circuit of efuse unit structure |
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| CN (1) | CN112992245A (en) |
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- 2020-12-25 CN CN202011562191.2A patent/CN112992245A/en active Pending
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