CN110400595B - Anti-cause circuit with correction function - Google Patents
Anti-cause circuit with correction function Download PDFInfo
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- CN110400595B CN110400595B CN201910670124.3A CN201910670124A CN110400595B CN 110400595 B CN110400595 B CN 110400595B CN 201910670124 A CN201910670124 A CN 201910670124A CN 110400595 B CN110400595 B CN 110400595B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/18—Auxiliary circuits, e.g. for writing into memory
Abstract
The invention provides an anti-use with a correction function, which comprises the following components: an anti-efuse programming tube, an efuse link structure, a control tube M1 and a control tube M2; the source electrode of the anti-effect programming tube and the drain electrode of the control tube M1 are connected with one end of the effect link structure; the drain electrode of the control tube M2 is connected with the other end of the efuse link structure; the grid of the control tube M1 is connected with a WL1 control signal; the grid of the control tube M2 is connected with a WL2 control signal; the gate of the anti-effect programming tube is the VH end of the anti-effect, and the sources of the control tube M1 and the control tube M2 are the VL ends of the anti-effect respectively. The invention improves the applicability and flexibility of the anti-use, so that the anti-use has correction capability, namely, the previous programming result can be modified again, and the logic state after the first programming is changed. And programming the programmed logic data again, thereby not only expanding the use flexibility, but also continuously keeping the original data reliability and safety characteristics of the anti user.
Description
Technical Field
The present invention relates to an antifuse structure, and more particularly, to an antifuse circuit having a trimming function.
Background
Common One Time Programmable (OTP) structures include Anti-eFuse (antifuse) and eFuse (fuse) two broad categories. The Anti-effect is programmed by breaking down an Oxide-Nitride-Oxide (ONO) insulating layer between a polysilicon layer and an N + diffusion layer, so that a resistance value between the two layers is changed, resulting in a change of an equivalent logic value. The efuse (fuse) is a method for programming a chip by blowing a fuse according to an Electron Mobility (EM) characteristic, resulting in a change in resistance values at both ends of the fuse. The two kinds of OTP adopt a standard CMOS process, the unit area is small, the total cost is reduced, the safety is good, particularly, the internal interconnection structures of the two kinds of OTP have natural radiation-proof capability and are relatively not influenced by electromagnetic radiation, which has particular attraction to the applications of aerospace, military, nuclear industry and the like, but the defects of the OTP schemes are also obvious: the memory can be programmed only once, so that the field use condition of a user and the production test capability of a product are greatly limited, and the redundancy is poor.
Therefore, in order to solve the above problem, a new anti-fuse circuit (antifuse) having a correction function needs to be provided.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an anti-use circuit with a correction function, which is used to solve the problem that the anti-use circuit in the prior art can be programmed only once, so that the redundancy of the product is poor.
To achieve the above and other related objects, the present invention provides an anti-cause circuit with a correction function, including at least: an anti-efuse programming tube, an efuse link structure, a control tube M1 and a control tube M2; the source electrode of the anti-efuse programming tube and the drain electrode of the control tube M1 are connected with one end of the efuse link structure; the drain electrode of the control tube M2 is connected with the other end of the efuse link structure; the grid electrode of the control tube M1 is connected with a WL1 control signal; the grid electrode of the control tube M2 is connected with a WL2 control signal; the gate of the anti-effect programming tube is a VH (high level) end of the anti-effect circuit, and the sources of the control tube M1 and the control tube M2 are VL (low level) ends of the anti-effect circuit respectively.
Preferably, the control tube M1 and the control tube M2 are NMOS tubes.
Preferably, the anti-use circuit implements the first and second programming operations and the read operation.
Preferably, in the first and second programming operations, the VH terminal of the anti-cause circuit is connected to a control tube M0.
Preferably, in the first and second programming operations, the control transistor M0 is a PMOS transistor.
Preferably, in the first and second programming operations, the VH terminal of the anti-use circuit is connected to the drain of the control tube M0, the source of the control tube M0 is connected to VDDQ, and the gate of the control tube M0 is controlled by BL; and two VL ends of the anti-cause circuit are grounded.
Preferably, in the first programming operation, the control tube M1 is opened, and the control tube M2 is closed; in the second programming operation, the control tube M1 is closed and the control tube M2 is opened.
Preferably, in the read operation, a VH end of the anti circuit is connected to a Sense Amplifier module.
Preferably, in the read operation, two VL terminals of the anti-use circuit are grounded.
Preferably, the state of the read operation includes: before and after the first programming operation, and after the second programming operation.
Preferably, in the read operation before the first programming operation and after the first programming operation, the control pipe M1 is opened and the control pipe M2 is closed; in the read operation after the second programming operation, the control pipe M1 is closed and the control pipe M2 is opened.
As described above, the anti-cause circuit with correction function according to the present invention has the following advantageous effects: the invention improves the applicability and flexibility of the anti-use circuit, so that the anti-use circuit has correction capability, namely, the previous programming result can be modified again, and the logic state after the first programming is changed. The programmed logic data is programmed again, so that the use flexibility is improved, and the original characteristics of data reliability and safety of the anti-use circuit are continuously maintained.
Drawings
FIG. 1 is a schematic diagram of an anti-use circuit according to the present invention;
FIG. 2 is a schematic diagram of the anti-use circuit of the present invention connected to the control transistor M0 during the first and second programming operations;
FIG. 3a is a schematic diagram of an anti-use circuit according to the present invention before a program operation;
FIG. 3b is a schematic diagram illustrating the state of the anti-use circuit in the first programming operation according to the present invention;
FIG. 3c is a diagram illustrating the state of the anti-use circuit in the second programming operation according to the present invention;
FIG. 4a is a diagram illustrating the state of the anti-use circuit before programming;
FIG. 4b is a schematic diagram illustrating the state of the anti-use circuit after the first programming operation according to the present invention;
FIG. 4c is a schematic diagram illustrating the state of the anti-use circuit after the second programming operation.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 4 c. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
The invention provides an anti-fuse circuit (anti-fuse) with a correction function, which is used for improving the applicability of the anti-fuse circuit. The anti-use circuit has the one-time correction programming capability, and the previous programming result can be programmed and repaired again.
As shown in fig. 1, fig. 1 is a schematic diagram of an anti-use circuit structure according to the present invention. The anti-use circuit at least comprises: an anti-efuse programming tube, an efuse link structure, a control tube M1 and a control tube M2; the source electrode of the anti-efuse programming tube and the drain electrode of the control tube M1 are connected with one end of the efuse link structure; the drain electrode of the control tube M2 is connected with the other end of the efuse link structure; the grid electrode of the control tube M1 is connected with a WL1 control signal; the grid electrode of the control tube M2 is connected with a WL2 control signal; the gate of the anti-effect programming tube is a VH end of the anti-effect circuit, and the source electrodes of the control tube M1 and the control tube M2 are VL ends of the anti-effect circuit respectively. The anti-cause circuit is an anti-cause circuit structure of 4-terminal devices (WL1, WL2, VH and VL).
In fig. 1, a gate of an anti-effect programming tube forms a VH end of an anti-effect circuit, a source of the anti-effect programming tube is connected to an effect link structure (metal link) and a drain (drain end) of a control tube M1, the other end of the metal link is connected to a drain (drain end) of a control tube M2, and source ends of the control tube M1 and the control tube M2 form a VL end of the anti-effect circuit of the present invention; the gate terminal of the control transistor M1 forms the WL1 terminal of the anti-use circuit of the present invention. The gate terminal of the control pipe M2 forms the WL2 terminal of the anti-use circuit of the present invention.
Further, the control tube M1 and the control tube M2 are NMOS tubes in the present invention. And the anti-use circuit respectively realizes the first and second programming operations and the read operation. That is, the anti-use circuit performs the first and second programming operations and the read operation, respectively. Further, as shown in fig. 2, fig. 2 is a schematic diagram illustrating the structure of the anti-use circuit of the present invention connected to the control pipe M0 in the first and second programming operations. In the first and second programming operations, the VH terminal of the anti-use circuit is connected to a control tube M0. In the first and second programming operations of the present invention, the control transistor M0 is a PMOS transistor. That is, during the first programming operation and the second programming operation, the control transistor M0 connected to the VH terminal of the anti-cause circuit of the present invention is a PMOS transistor. Referring to fig. 2, in the first and second programming operations, the VH terminal of the anti-use circuit is connected to the drain of the control transistor M0, the source of the control transistor M0 is connected to VDDQ (output buffer supply voltage), and the gate of the control transistor M0 is controlled by BL; and two VL ends of the anti-cause circuit are grounded.
Namely, VH of the anti-use circuit of the present invention is connected to drain of the PMOS transistor M0, source of the PMOS transistor M0 is connected to VDDQ, and BL controls gate of the PMOS transistor M0, so as to provide a programming voltage for the anti-use circuit unit of the present invention. The ends WL1 and WL2 respectively control NMOS tubes M1 and M2, two-time gating of an anti-use circuit inside the module is achieved, and a VL end of the anti-use circuit is connected with GND.
Referring to fig. 3a to 3c, the anti-use circuit of the present invention implements a programming process, a programming setting, and a state change before and after the programming. Fig. 3a is a schematic diagram illustrating an anti-use circuit according to the present invention before a program operation; FIG. 3b is a schematic diagram illustrating the state of the anti-use circuit in the first programming operation according to the present invention; FIG. 3c is a diagram illustrating the state of the anti-use circuit in the second programming operation according to the present invention. The dashed lines indicate the absence of vias.
As shown in FIG. 3a, before programming, the cells in the anti-use circuit are in an initial state (pre). The efuse link structure exhibits a low resistance in the pre state, while the anti-efuse programming tube exhibits a high resistance between gate and source in the pre state. Because the anti-cause circuit and the anti-cause circuit are connected in series, the whole anti-cause circuit presents high resistance in a state before programming, and the logic state of the anti-cause circuit is defined as 1. The efuse in FIG. 3a represents the efuse link structure in the present invention.
As shown in FIG. 3b, the efuse in FIG. 3b represents the efuse link structure in the present invention. First time programming (normal programming) operation: if the fusion voltage between the gate and the source of the anti-fuse circuit programming tube is Va, the fusing current Im (the corresponding programming voltage is Vm) of the anti-fuse link structure, when the anti-fuse circuit is normally programmed, the WL1 is high, the control tube M1 is switched on, the WL2 is low, and the control tube M2 is switched off; when the working voltage is set to be Va and the programming time Ta, the gate and the source of the anti-effect are fused; at this time, no current passes through the efuse link structure, and the state of the efuse link structure is maintained unchanged, so that after normal programming, the state of the anti-cause circuit unit presents low resistance, and therefore, the whole anti-cause circuit is programmed to be in a logic state of '0'.
As shown in FIG. 3c, the efuse in FIG. 3c represents the efuse link structure in the present invention. Second program (modified program) operation: when the logic value of the anti-use circuit unit after programming needs to be corrected, namely, the logic value needs to be corrected from '0' to '1', the anti-use circuit can be subjected to reprogramming operation, the programming current value is set to Im, the programming time Tm is set, the WL1 is set to be at a low level, the control tube M1 is disconnected, the WL2 is set to be at a high level, and the control tube M2 is connected; therefore, the programming current flows through link, and electromigration occurs, which causes the link to blow, so that the entire anti-cause circuit presents high resistance, i.e. is reprogrammed to logic state "1".
Thus, in the first programming operation, the control tube M1 is open, and the control tube M2 is closed; in the second programming operation, the control tube M1 is closed and the control tube M2 is opened. When programming for the first time, WL1 is turned on, WL2 is turned off, the voltage 1 enables the anti-efuse programming tube to be changed, and the efuse link structure is not affected; when programming for the second time, WL1 is disconnected, WL2 is connected, the structure of the efuse link is changed by current 2, and the anti-efuse programming tube is not influenced.
As shown in fig. 4a to 4c, the read operation setting and the read state change after programming of the anti-use circuit of the present invention, wherein fig. 4a is a schematic diagram illustrating the state of the read operation before programming of the anti-use circuit of the present invention; FIG. 4b is a schematic diagram illustrating the state of the anti-use circuit after the first programming operation according to the present invention; FIG. 4c is a schematic diagram illustrating the state of the anti-use circuit after the second programming operation. Wherein the dashed lines indicate that no vias are present.
Further, in the read operation, the VH terminal of the anti-use circuit is connected to a Sense Amplifier module (Sense Amplifier module) (SA module in fig. 4a to 4 c). Furthermore, in the read operation, two VL ends of the anti-use circuit are grounded. The states of the read operation of the present invention include: before and after the first programming operation, and after the second programming operation.
When the anti-use circuit is read, the VH end of the anti-use circuit is connected with a Sense Amplifier (SA) module, and is converted into a logic value to be output through the SA according to the equivalent resistance value between the VH and the GND. If the anti-use circuit only carries out the first programming (normal programming), the equivalent resistance value is read under the control of WL1, and WL2 is set to 0; if the anti-use circuit is programmed for the second time (redundancy programming), the equivalent resistance value is read under the control of WL2, and WL1 is set to 0.
Therefore, as shown in fig. 4a, when reading before programming, WL1 is on, WL2 is off, and SA converts and outputs information of large resistance value of anti-efuse programming tube, the logic initial value is 1, and efuse in fig. 4a represents efuse link structure in the present invention.
As shown in fig. 4b, after the first programming, reading, keeping the switch setting unchanged, SA converting to output the low resistance value information of the anti-effect programming tube, and the logic output value is 0; the efuse in FIG. 4b represents the efuse link structure in the present invention.
As shown in FIG. 4c, after the second programming, the read is performed, WL1 is turned off, WL2 is turned on, the SA outputs the series resistance value (blown, large resistance value) of the anti-efuse programming tube and the efuse link structure, and the logic output value is 1. The efuse in FIG. 4c represents the efuse link structure in the present invention.
Thus, i.e., in the read operation before the first programming operation and after the first programming operation, the control pipe M1 is opened and the control pipe M2 is closed; in the read operation after the second programming operation, the control pipe M1 is closed and the control pipe M2 is opened.
Compared with the traditional anti-cause circuit structure, the anti-cause circuit structure provided by the invention has the advantage that the one-time reprogramming capability is increased, namely, a user can correct the programming result for 1 time on the basis of normally operating the anti-cause programming tube. Before programming, the anti-use circuit is in state "1". After the first programming, the value of the anti circuit is "0". The anti-use circuit value can be corrected back to "1" again by a second programming.
At present, in order to correct the OTP result, the OTP is generally implemented by setting a redundant bit. Namely, a redundant bit area is added outside the normal bit, and the address information and the actual value of the error bit are recorded by programming the redundant bit. If the user reads out the wrong bit address, the system ignores the wrong value and automatically reads out the corresponding redundant value. The invention does not adopt a redundancy mode to correct errors generated in the OTP programming process, but directly utilizes a secondary programming method to correct the errors, thereby simplifying the circuit and layout design, and having smaller IP using area, higher flexibility and higher reliability.
In summary, the present invention improves the applicability and flexibility of the anti-use circuit, so that the anti-use circuit has a correction capability, that is, the previous programming result can be modified again, and the logic state after the first programming is changed. The programmed logic data is programmed again, so that the use flexibility is improved, and the original characteristics of data reliability and safety of the anti-use circuit are continuously maintained. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (11)
1. An anti-use circuit having a correction function, comprising at least:
an anti-efuse programming tube, an efuse link structure, a control tube M1 and a control tube M2;
the source electrode of the anti-efuse programming tube and the drain electrode of the control tube M1 are connected with one end of the efuse link structure; the drain electrode of the control tube M2 is connected with the other end of the efuse link structure; the grid electrode of the control tube M1 is connected with a WL1 control signal; the grid electrode of the control tube M2 is connected with a WL2 control signal;
the gate of the anti-effect programming tube is a VH end of the anti-effect circuit, and the source electrodes of the control tube M1 and the control tube M2 are VL ends of the anti-effect circuit respectively.
2. The anti-use circuit with correction function according to claim 1, characterized in that: the control tube M1 and the control tube M2 are NMOS tubes.
3. The anti-use circuit with correction function according to claim 2, wherein: the anti-use circuit respectively realizes the first programming operation, the second programming operation and the reading operation.
4. The anti-use circuit with correction function according to claim 3, wherein: in the first and second programming operations, the VH terminal of the anti-use circuit is connected to a control tube M0.
5. The anti-use circuit with correction function according to claim 4, wherein: in the first and second programming operations, the control transistor M0 is a PMOS transistor.
6. The anti-use circuit with correction function according to claim 5, characterized in that: in the first and second programming operations, the VH terminal of the anti-cause circuit is connected to the drain of the control tube M0, the source of the control tube M0 is connected to VDDQ, and the gate of the control tube M0 is controlled by BL; and two VL ends of the anti-cause circuit are grounded.
7. The anti-use circuit with correction function according to claim 6, characterized in that: in the first programming operation, the control tube M1 is opened, and the control tube M2 is closed; in the second programming operation, the control tube M1 is closed and the control tube M2 is opened.
8. The anti-use circuit with correction function according to claim 3, wherein: in the read operation, the VH end of the anti-use circuit is connected with a Sense Amplifier module.
9. The anti-use circuit with correction function according to claim 8, characterized in that: in the read operation, two VL ends of the anti-cause circuit are grounded.
10. The anti-use circuit with correction function according to claim 9, characterized in that: the states of the read operation include: before and after the first programming operation, and after the second programming operation.
11. The anti-use circuit with correction function according to claim 10, wherein: in the read operation before the first programming operation and after the first programming operation, the control pipe M1 is opened, and the control pipe M2 is closed; in the read operation after the second programming operation, the control pipe M1 is closed and the control pipe M2 is opened.
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| CN201910670124.3A CN110400595B (en) | 2019-07-24 | 2019-07-24 | Anti-cause circuit with correction function |
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| KR100648288B1 (en) * | 2005-07-22 | 2006-11-23 | 삼성전자주식회사 | Redundancy selector circuit for use in non-volatile memory device |
| US20080170457A1 (en) * | 2007-01-12 | 2008-07-17 | International Business Machines Corporation | Method for sensing a signal in an integrated circuit complementary fuse arrangement |
| US7715219B2 (en) * | 2008-06-30 | 2010-05-11 | Allegro Microsystems, Inc. | Non-volatile programmable memory cell and memory array |
| US8625377B2 (en) * | 2012-02-08 | 2014-01-07 | Robert N. Rountree | Low voltage efuse programming circuit and method |
| GB2541961B (en) * | 2015-09-01 | 2019-05-15 | Lattice Semiconductor Corp | Multi-time programmable non-volatile memory cell |
| CN109712663A (en) * | 2018-12-29 | 2019-05-03 | 上海华力集成电路制造有限公司 | Fuse programming unit, fuse circuit and its programming process |
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