CN103366821A - Improved differential framework OTP (One Time Programmable) storage unit based on series transistor - Google Patents
Improved differential framework OTP (One Time Programmable) storage unit based on series transistor Download PDFInfo
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Abstract
The invention discloses an improved differential framework OTP (One Time Programmable) storage unit based on a series transistor. The improved differential framework OTP storage unit comprises at least two branches consisting of an OTP storage unit with two serially-connected transistors, wherein bit lines of the two branches are used as one group of differential pair to be input into a sense amplifier, and then data is read out through comparison. According to the improved differential framework OTP storage unit, by adopting a differential framework, the distinguishable current before and after programming is effectively increased; in addition, by adopting a symmetric differential structure, impedances of the branches of the storage unit are well matched, and the stability is good.
Description
Technical field
The present invention relates to memory area, be specifically related to a kind of improved differential architecture OTP storage unit based on the serial transistor type.
Background technology
Disposable programmable memory (OTP) is a kind of in the nonvolatile memory, it can be for circuit application provides versatile and flexible and cheap solution, thereby is widely used in data backup memory, code storage, the initial information storage, the fields such as RFID beacon information storage.
Have at present various structures can realize the OTP function, main structure is the nmos pass transistor structure, and an OTP structure as shown in Figure 1 comprises a nmos pass transistor and a mos capacitance, and both link to each other by a larger area multi-crystal silicon floating bar coupling.One end of multi-crystal silicon floating bar is as the grid of NMOS, and the N-type diffusion region on the other end and the substrate in the P trap consists of mos capacitance.The N-type diffusion region links to each other with polysilicon as the word line of OTP, and the drain electrode of NMOS is as the bit line of OTP, and the source electrode of NMOS is as the source line of OTP.Its principle is when not programming, and reads voltage if apply at the wordline bits line segment, because the coupling influence of mos capacitance, the grid voltage of NMOS can surpass threshold voltage, unlatching work, thus obtain a larger electric current; And if the wordline bits line applies very large program voltage, this moment, stronger hot carrier injection occured in nmos pass transistor, because floating gate polysilicon does not have direct metal connecting line, thereby the charge carrier of these injections can not disappear but is trapped in polysilicon, very large skew occurs in the threshold voltage that has so just caused nmos pass transistor, read voltage if at this moment add, coupled voltages is not enough to open NMOS, and NMOS turn-offs.
But above-mentioned OTP storage unit needs mos capacitance to come coupled voltages, and need to be by the recently design programming voltage that is coupled, and therefore the needed mos capacitance area of this framework is larger.Simultaneously, need to increase primary ions in word line end and inject, namely more than once extra lithography step has increased cost.
After 2000, people have turned to the emphasis of research the OTP storage architecture of single grid type, because this structure can be fully compatible memory process and standard CMOS logic process, provide cost savings widely.
The researchist designs the dielectric breakdown type otp memory that research emphasis has focused on based on fuse (efuse) and anti-fuse (antifuse).Thereby efuse programming is normally adopted and is flowed through that the fuse excess current causes its fusing so that its resistance value is varied to several kilohms even highlyer realize programming by tens ohm.The Antifuse programming is just in time opposite with efuse, and anti-fuse has very high resistance before programming, and about the hundreds of megaohm, by high electrical breakdown, resistance is reduced to kilo-ohm rank even lower, realizes storage purpose with this during programming.Formal based on their such characteristic, they at the otp memory design field in occupation of important position.Just proposed a kind of three pipe antifuse storeies that are widely used now in the US Patent No. 6927997 in 2005, its framework as shown in Figure 2.
But, no matter be the otp memory that fuse or anti-fuse consist of, all be based on dielectric breakdown characteristics, can bring certain stability problem inevitably.Simultaneously, some fuses and anti-fuse memory need special material to consist of fuse and anti-fuse, and its storage unit needs the high pressure gate tube, and memory cell area is also larger.The required high voltage of programming has also proposed challenge for the design of peripheral circuit and optimization.
2006, in patent US6678190, eMemory company formally proposed a kind of series connection pmos type OTP parts.Fig. 3 is exactly its configuration diagram.Its principle of work is by the injection to floating gate charge, changes the threshold voltage of storage tube and then change it to open off state.2008, Chingis company proposed a kind of similar PMOS tandem type OTP storage organization in patent US7078761B2.The easy otp memory of the logic NOT unit of a kind of transistor series type that National also proposes, it is comprised of a PMOS pipe and a NMOS pipe, and the PMOS pipe is in the N trap and the unsettled floating boom that is used as of its grid.2008, the people such as Ying-Je Chen are at document " A Novel2-Bit/Cell p-Channel Logic Programmable Cell With Pure90-nm CMOS Technology " (IEEE ELECTRON DEVICE LETTERS, AUGUST2008, VOL.29, NO.8, pp:938-940) in issued the otp memory of the serial transistor type of a kind of employing SAN (Self-Aligned Nitride) structure.Adopt self aligned nitride memory node of low pressure chemical vapor deposition generation in the middle of its two grid, as stored charge, thereby programming is exactly to utilize the high energy electron of energy interband to inject this node to realize storage.
Serial transistor type OTP parts can be fully compatible with logic process, is widely used.But the programming efficiency of such device is lower, and namely differentiable range of current is very little before and after this device programming.For sensitive and sense data rapidly, usually all adopt now differential amplifier circuit to come the most reading circuit.The limitation of range of current has seriously limited the impedance of reference circuit and has selected, and is easy to bring the impedance mismatch problem, causes read error.
In view of this, be necessary to propose a kind of improved OTP memory cell structure and optimize these problems.
Summary of the invention
For deficiency of the prior art, the invention provides a kind of improved differential architecture OTP storage unit based on the serial transistor type, on the basis of traditional serial transistor type OTP storage unit, adopt two branch road contrast input difference amplifiers when reading, avoid the mismatch problem that adopts reference circuit to bring, greatly improved the stability that reads.
Take two pipe P type OTP storage unit as example, this framework is comprised of two PMOS transistor series, and first PMOS transistor is as gate transistor, and a described PMOS grid is the word line of integral device the most, and described the first pmos source is the source electrode of device as a whole; Second PMOS transistor is as memory transistor, and described the 2nd PMOS grid is floating empty, and the drain electrode of described the 2nd PMOS is the bit line of device as a whole, and the drain electrode of the source electrode of described the 2nd PMOS and a described PMOS shares a p type diffusion region.In this scheme that provides namely be: adopt the difference symmetrical structure, one two pipe of every route tandem type OTP unit forms, and the bit line of two branch roads is input in the sense amplifier as one group of differential pair, then contrasts sense data.
Compared with prior art, a kind of improved differential architecture OTP storage unit based on the serial transistor type of the present invention has following some advantage:
1) the present invention adopts differential architecture, has effectively enlarged the electric current distinguished before and after the programming.
2) the present invention adopts the symmetric difference framework, and the impedance matching of storage unit branch road is better, and stability is higher.For existing storage unit, usually adopt a reference circuit as the reference branch road when reading, and bit line BL is input in the sense amplifier together.The impedance of this branch road must be deposited 0 o'clock BL end equiva lent impedance and storage unit between storage unit and be deposited in the middle of 1 o'clock equiva lent impedance, and the reference arm here must careful design, not so is easy to cause mistake.And the differential configuration that proposes for the present invention, two BL branch roads all are identical structures, resistance value also changed between the equiva lent impedance depositing 0 o'clock equiva lent impedance and deposit certainly in 1 o'clock.Thereby do not worry resistance matching problem, the stability of storage unit also can be protected.
3) number of tubes of differential architecture OTP of the present invention unit increases to some extent, but the pipe of the PMOS in tandem type OTP unit size is not very large, thereby the area change of storage unit is limited.
Differential architecture OTP unit can enlarge the differentiable range of current in device programming front and back to a certain extent, adopt two branch road contrast input difference amplifiers when reading simultaneously, can avoid the mismatch problem that adopts reference circuit to bring, greatly improve the stability that reads.This framework has very important Research Significance and wide market outlook.
Description of drawings
Fig. 1 is traditional nmos pass transistor OTP structural representation.
Fig. 2 is 3 pipe anti-fuse structures OTP structural representations.
Fig. 3 is 2 pipe cascaded structure OTP structural representations.
Fig. 4 is the differential architecture OTP structural representation based on the serial transistor type of the present invention.
Embodiment
In conjunction with shown in Figure 4, a kind of improved differential architecture OTP storage unit based on the serial transistor type of the present invention, storage unit circuit mainly comprises four transistors, wherein transistor MP1 and transistor MP2 consist of a serial transistor type OTP unit, in like manner transistor MP3 and transistor MP4 also consist of a same serial transistor type OTP unit, and their whole symmetrical structures that adopts have formed difference type OTP storage unit.Wherein MP1 and MP3 are as gate transistor, and the signal Vsg that applies by grid controls.MP2 and MP4 grid are floating empty, as memory transistor.Uppermost source line SL control circuit module, this module comprises a coding and decoding circuit, by address signal control, provides the task of power supply when bearing simultaneously programming.Nethermost is bit line BL control circuit module and sensitive amplifier circuit module, and this module comprises the another one coding and decoding circuit, and voltage signal is provided, and sensitive amplifier circuit is also born the important task of reading out data simultaneously.
During programming state, when Vsg signal during to low level, the word line selection is logical, storage unit work.If at this moment SL applies programming high pressure VPP (about 8V), BL1 meets 0, BL2 and meets VPP, left side MP1 and the work of MP2 branch road, electronics is optionally injected the grid FG1 of MP2, when the floating boom voltage of MP2 is low to moderate a certain voltage, it stays open state, is written into 1; The right branch road MP3 and MP4 branch road are also worked, but because BL2 has connect high voltage, and electronics is not injected into the grid FG2 of MP4, its grid voltage does not change, and still keeps off state, is written into 0.At this moment we define whole difference storage architecture and are written into 1.In like manner, if SL applies programming high pressure VPP, BL2 meets 0, BL1 and meets VPP, and then the floating boom voltage of MP2 is constant, is written into 0, and the threshold voltage variation of MP4, and make its grid voltage be low to moderate a certain voltage, and allow it open, write 1.We define whole difference storage architecture and are written into 0 in this case.
During reading state, Vsg selects the storage unit that reads to low level.At this moment SL applies and reads voltage VR, and BL1 and BL2 set to 0 simultaneously.If the MP2 floating boom is not recharged by electronic injection MP4 in the storage unit, then because V
FG1-V
BL1＜Vth, V
FG2-V
BL2=0＞Vth, MP2 open MP4 and turn-off, and branch current I1 by sense amplifier, can read 1 than large many of I2.In like manner, if the MP4 floating boom is not recharged by electronic injection MP2 in the storage unit, then because V
FG2-V
BL2＜Vth, V
FG1-V
BL1=0＞Vth, MP4 open MP2 and turn-off, and branch current I2 is than large many of I1, and by sense amplifier, we can read 0.
To sum up, 1) the present invention adopts differential architecture, has effectively enlarged the electric current distinguished before and after the programming.For example, can define bit line BL1 and deposit 0, bit line BL2 deposited 1 o'clock, and 0 state is stored in the global storage unit.If reading out data at this moment, bit line BL1 floating-gate pipe threshold voltage unchanged, pipe turn-offs, and electric current is very little; Bit line BL2 floating-gate pipe has electronic injection, threshold voltage variation, and pipe is opened, certain electric current of flowing through, the difference sense amplifier is read current effectively.Equally, definition bit line BL1 deposits 1, and bit line BL2 deposits 0 o'clock global storage 1 state.At this moment be that bit line BL1 has certain electric current, bit line BL2 is no current almost.It is maximum that electric current differentiate range at this time can reach.
2) the present invention adopts the symmetric difference framework, and the impedance matching of storage unit branch road is better, and stability is higher.For existing storage unit, usually adopt a reference circuit as the reference branch road when reading, and bit line BL is input in the sense amplifier together.The impedance of this branch road must be deposited 0 o'clock BL end equiva lent impedance and storage unit between storage unit and be deposited in the middle of 1 o'clock equiva lent impedance, and the reference arm here must careful design, not so is easy to cause mistake.And the differential configuration that proposes for the present invention, two BL branch roads all are identical structures, resistance value also changed between the equiva lent impedance depositing 0 o'clock equiva lent impedance and deposit certainly in 1 o'clock.Thereby do not worry resistance matching problem, the stability of storage unit also can be protected.
3) number of tubes of described novel differential architecture OTP unit increases to some extent, but the pipe of the PMOS in tandem type OTP unit size is not very large, thereby the area change of storage unit is limited.
The OTP unit of described novel differential architecture can enlarge the differentiable range of current in device programming front and back to a certain extent, adopt two branch road contrast input difference amplifiers when reading simultaneously, avoid the mismatch problem that adopts reference circuit to bring, greatly improved the stability that reads.
The above; it only is better case study on implementation of the present invention; be not that the present invention is imposed any restrictions; every similar mode of any simple modification, change, employing that essence is done above embodiment according to the present invention substitutes and the variation of equivalent structure, all still belongs in the protection domain of technical solution of the present invention.
Claims (6)
1. improved differential architecture OTP storage unit based on the serial transistor type, it is characterized in that, comprise at least two branch roads that formed by the OTP storage unit of one two pipe tandem type, adopt the difference symmetrical structure, article two, the bit line of branch road is input in the sense amplifier as one group of differential pair, then contrasts sense data.
2. the improved differential architecture OTP storage unit based on the serial transistor type according to claim 1, it is characterized in that, the OTP storage unit of described two pipe tandem types comprises a PMOS transistor and the 2nd PMOS transistor of series connection, with a PMOS transistor as gate transistor, the one PMOS grid is the word line of device as a whole, and the first pmos source is the source electrode of device as a whole; As memory transistor, described the 2nd PMOS grid is floating empty with the 2nd PMOS transistor, and the drain electrode of described the 2nd PMOS is the bit line of device as a whole, and the drain electrode of the source electrode of described the 2nd PMOS and a described PMOS shares a p type diffusion region.
3. the improved differential architecture OTP storage unit based on the serial transistor type according to claim 2 is characterized in that, every pipe serial transistor type OTP unit comprises a gate transistor and a memory transistor.
4. the improved differential architecture OTP storage unit based on the serial transistor type according to claim 3, it is characterized in that, every pipe serial transistor type OTP unit also comprises active line SL control circuit module, bit line BL control circuit module and sensitive amplifier circuit module.
5. the improved differential architecture OTP storage unit based on the serial transistor type according to claim 4 is characterized in that, includes the coding and decoding circuit of a correspondence in described source line SL control circuit module and the bit line BL control circuit module.
6. the improved differential architecture OTP storage unit based on the serial transistor type according to claim 5, it is characterized in that, coding and decoding circuit in the line SL control circuit module of described source by address signal control, provides the task of power supply when bearing simultaneously programming; Coding and decoding circuit in the described bit line BL control circuit module provides voltage signal, also comprises data read functions module in the described sensitive amplifier circuit module.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103680631A (en) * | 2013-12-25 | 2014-03-26 | 苏州宽温电子科技有限公司 | Improved differential framework XPM memory unit |
| CN104269187A (en) * | 2014-09-19 | 2015-01-07 | 苏州锋驰微电子有限公司 | OTP (One Time Programmable) or MTP (Multiple Time Programmable) memory module with dual-cell structure and capable of checking blank |
| CN104269188A (en) * | 2014-09-19 | 2015-01-07 | 苏州锋驰微电子有限公司 | OTP (One Time Programmable) or MTP (Multiple Time Programmable) memory module with dual-cell structure |
| CN108305662A (en) * | 2018-03-27 | 2018-07-20 | 苏州大学 | Improved differential architecture OTP memory cell based on fuse characteristics and memory |
| CN108511022A (en) * | 2018-03-27 | 2018-09-07 | 苏州大学 | Improved differential architecture Nor flash storage units based on series crystal type and memory |
| CN108520767A (en) * | 2018-03-27 | 2018-09-11 | 苏州大学 | Improved differential architecture OTP memory cell based on series crystal type and memory |
| CN111415694A (en) * | 2019-01-04 | 2020-07-14 | 三星电子株式会社 | One-time programmable memory unit, memory thereof and memory system |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103680631A (en) * | 2013-12-25 | 2014-03-26 | 苏州宽温电子科技有限公司 | Improved differential framework XPM memory unit |
| CN104269187A (en) * | 2014-09-19 | 2015-01-07 | 苏州锋驰微电子有限公司 | OTP (One Time Programmable) or MTP (Multiple Time Programmable) memory module with dual-cell structure and capable of checking blank |
| CN104269188A (en) * | 2014-09-19 | 2015-01-07 | 苏州锋驰微电子有限公司 | OTP (One Time Programmable) or MTP (Multiple Time Programmable) memory module with dual-cell structure |
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| CN108305662A (en) * | 2018-03-27 | 2018-07-20 | 苏州大学 | Improved differential architecture OTP memory cell based on fuse characteristics and memory |
| CN108511022A (en) * | 2018-03-27 | 2018-09-07 | 苏州大学 | Improved differential architecture Nor flash storage units based on series crystal type and memory |
| CN108520767A (en) * | 2018-03-27 | 2018-09-11 | 苏州大学 | Improved differential architecture OTP memory cell based on series crystal type and memory |
| CN111415694A (en) * | 2019-01-04 | 2020-07-14 | 三星电子株式会社 | One-time programmable memory unit, memory thereof and memory system |
| CN111415694B (en) * | 2019-01-04 | 2024-06-07 | 三星电子株式会社 | One-time programmable memory unit, memory and memory system thereof |
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Application publication date: 20131023 |