JP2009129487A - Nonvolatile semiconductor storage element and nonvolatile semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a rewritable nonvolatile semiconductor storage element of which the voltage stress is not applied to a storage transistor in the standby state while allowing the read-out margin to be large. <P>SOLUTION: A semiconductor storage device includes: the TRUE side storage transistor and BAR side storage transistor; selection transistors connected between drains of both storage transistors and corresponding bit lines; a word line connected to gates of two selection transistors; a flip-flop composed by cross connecting two CMOS inverters; and two gate transistors connected between the drains of respective storage transistors and corresponding input/output section of the flip-flop. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an electrically erasable and writable nonvolatile semiconductor memory element and a nonvolatile semiconductor memory device including the same.

  Necessity of redundancy (redundancy) due to increase in capacity of built-in SRAM, necessity of individual tuning after mounting a board such as an LCD driver, personal identification information (ID code, decryption key, and IC card With the expansion of various applications such as numbers, the need for low-cost fuses is increasing.

  Conventionally, fuse memories that can be formed by a standard CMOS process include those having a polysilicon or wiring metal layer that is blown by a laser or current, and those having an insulating gate film that is broken by a voltage. However, a fuse memory having such a fusing part or a dielectric breakdown part can be programmed only once, and therefore is not suitable for applications requiring rewriting as described above.

  On the other hand, if it is a floating gate type nonvolatile element, it is possible to create a fuse that can be electrically erased and written by a CMOS process. However, in order to form a floating gate, a standard similar to a conventional flash memory is used. Since it is necessary to introduce an additional process into the CMOS process, it is not suitable from the viewpoint of cost. Further, in the standard CMOS process, since the insulating film becomes thinner with higher integration, there is a problem that the data retention characteristic is deteriorated when the floating gate is formed using this standard CMOS process.

  Thus, for example, Patent Document 1, Patent Document 2, and Patent Document 3 show a nonvolatile memory device that can be manufactured by a standard CMOS process and a nonvolatile memory device that does not have a special floating gate.

US Pat. No. 6,518,614 JP 2004-56095 A JP-A-2005-353106

  FIG. 1 shows a memory cell configuration of a nonvolatile memory device manufactured by a standard CMOS process disclosed in Patent Document 3 as a conventional example. This memory cell includes N-type MOS transistors MCN1 and MCN2 which are nonvolatile data storage units and static latch type flip-flop units (MN3, MN4,...) Having differential inputs to the output nodes nodeT and nodeB of the nonvolatile data storage unit. MP1, MP2). The flip-flop unit can perform normal SRAM operation reading and writing operations, but can reload data in the nonvolatile data storage unit and store data in the flip-flop unit.

  FIG. 2 shows a data setting method in the conventional example. This data setting method is a method of determining data by the threshold voltage difference between MCN1 and MCN2. In the initial state before data writing, the N-type MOS transistors MCN1 and MCN2 are both at the threshold voltage Vth0, and in this state, the output data of the flip-flop is indefinite. Therefore, in order to determine the data, first, writing of data “0” is realized by raising the threshold voltage on the MCN1 side to Vth1 (Vth1> Vth0). In this configuration, since erasing (lowering Vth) cannot be performed, the subsequent writing of data “1” sets the threshold voltage on the MCN2 side to Vth2 (Vth2> Vth1) from the state of data “0”. Realized by raising

  FIG. 3 shows a method for changing the threshold voltage of the N-type MOS transistor in the nonvolatile data storage section in the above-described conventional example. As an example, data “0”, that is, a case where the threshold voltage on the MCN1 side is increased is shown. Basically, the characteristic degradation due to hot carriers of the N-type MOS transistor is actively utilized, and the source potential of MCN1, which is to increase the threshold voltage, is 0V, the gate potential (MLW) is 2.5V, the drain The potential (nodeT) is set to 5 V, and the threshold voltage is raised by hot carrier injection near the drain end. At this time, the drain potential of 5V is such that the bit line BLT potential is set to 5V, the word line WL of the flip-flop section is set to a sufficiently high voltage (7V), and the BLT potential of 5V is completely supplied to the nodeT. By supplying. The drain potential of MCN2, which does not want to increase the threshold voltage, is controlled so that hot carrier injection does not occur by setting the BLB potential to 0V. When data “1” is written, the threshold voltage on the MCN2 side is increased. Therefore, by simply setting BLT = 0V and BLB = 5V, other conditions are the same as when data “0” is written. .

  FIG. 4 shows a data transfer method from the nonvolatile data storage unit to the flip-flop unit in the above-described conventional example. This figure shows a data transfer method in the case of data “0”, that is, the threshold voltage Vth1 of MCN1 is higher than the threshold voltage Vth0 of MCN2. In the flip-flop unit, nodeT and nodeB are equalized to the same potential by lowering the equalization control signal ZEQ from Vcc to 0 V at time t0 under the condition that the word line WL = 0V and the restore control signal RESTORE = 0V. At time t1, the equalizing operation is terminated, and MLW, which is the gate potential of MCN1 and MCN2, is gradually increased from time t2, so that the MCN2 side having the lower threshold voltage is turned on first, and the potential of nodeB is lowered. Go. After a while, the MCN1 side also turns on, but finally the latch is determined when nodeB on the MCN2 side having a low threshold voltage is 0V and nodeT on the MCN1 side is Vcc. At time t3, MLW boosting is completed. At time t4, RESTORE is raised from 0V to Vcc to activate the latch of the flip-flop unit, and the data is held stably. Finally, at time t5, MLW is lowered to 0V. End.

Although the operation of the memory cell in the conventional example has been described above, the conventional configuration has the following problems.
[1] The threshold voltage difference margin is small. The threshold voltage difference margin corresponds to Vth1−Vth0 for data “0” and Vth2−Vth1 for data “1”. The threshold voltage change amount in the hot carrier injection phenomenon has an upper limit value Vth_max. If the read margin of data “0” and data “1” is evenly distributed, The margin is (Vth_max−Vth0) / 2. When it is assumed that rewriting is performed N times, it is necessary to divide the Vth control into 2N with Vth_max as the maximum value, and the margins of data “0” and data “1” are (Vth_max−Vth0) / 2N Thus, the margin is further reduced.

  [2] It is necessary to apply a high voltage (7 V and 5 V) to the word line WL and the bit lines BLT and BLB that need to be controlled for each memory cell as an operating voltage when writing data to the nonvolatile data storage unit There is. This means that it is necessary to use a high breakdown voltage transistor as a driver for driving the word line and the bit line and a column selection transistor for selecting the bit line. When operating at Vcc = 1.8 V as in the normal read operation, the high voltage transistor optimized for high voltage is not high speed, which causes an access delay. Increasing the transistor size in order to increase the current driving capability has the problem of increasing the chip area.

  The purpose of increasing the read margin in the nonvolatile memory is to improve data retention characteristics. Therefore, it is also important to prevent voltage stress from being applied to the storage transistor in the data retention state.

  An object of the present invention is to provide a rewritable nonvolatile semiconductor memory element and a nonvolatile semiconductor memory device in which a read margin can be increased and voltage memory is not applied to a memory transistor in a standby state.

  According to the first aspect of the present invention, there are provided a TRUE-side storage transistor and a BAR-side storage transistor, which are MOS transistors capable of controlling a threshold voltage by electron injection near the gate, and a source line connected to the sources of the two storage transistors. And a TRUE-side select transistor that is a MOS transistor connected between the drain of the TRUE-side storage transistor and the TRUE-side bit line, and a drain connected to the BAR-side storage transistor and the BAR-side bit line. A BAR side selection transistor, which is a MOS transistor, and a word line connected to the gates of the two selection transistors are provided.

  The invention according to claim 2 provides a TRUE-side storage transistor and a BAR-side storage transistor, which are MOS transistors capable of controlling a threshold voltage by electron injection near the gate, and a source line connected to the sources of the two storage transistors And a TRUE-side select transistor that is a MOS transistor connected between the drain of the TRUE-side storage transistor and the TRUE-side bit line, and a drain connected to the BAR-side storage transistor and the BAR-side bit line. BAR side selection transistor that is a MOS transistor, a word line connected to the gates of the two selection transistors, a flip-flop configured by cross-connecting two CMOS inverters, and a load transistor of each of the two inverters And two connected in parallel A recharging transistor; a TRUE side gate transistor connected between a drain of the TRUE side storage transistor and a TRUE side input / output unit of the flip-flop; a drain of the BAR side storage transistor; and a BAR side input of the flip-flop And a BAR-side gate transistor connected between the output portion and the output portion.

  According to a third aspect of the present invention, there are provided a TRUE-side storage transistor and a BAR-side storage transistor, which are MOS transistors capable of controlling a threshold voltage by electron injection near the gate, and a source line connected to the sources of the two storage transistors. And a TRUE-side select transistor that is a MOS transistor connected between the drain of the TRUE-side storage transistor and the TRUE-side bit line, and a drain connected to the BAR-side storage transistor and the BAR-side bit line. A BAR-side selection transistor which is a MOS transistor, a word line connected to the gates of the two selection transistors, a flip-flop configured by cross-connecting two CMOS inverters, a current mirror circuit connected to a power supply, , TRUE memory transistor A TRUE side gate transistor connected between a drain and the current mirror circuit; a BAR side gate transistor connected between the drain of the BAR side storage transistor and the current mirror circuit; and a TRUE side gate transistor. Between the TRUE side analog switch connected between the current mirror side terminal and the TRUE side input / output part of the flip-flop, and between the current mirror side terminal of the BAR side gate transistor and the BAR side input / output part of the flip-flop And a BAR-side analog switch connected to.

  According to a fourth aspect of the present invention, there are provided a TRUE-side storage transistor and a BAR-side storage transistor, which are MOS transistors capable of controlling a threshold voltage by electron injection near the gate, and a source line connected to the sources of the two storage transistors. And a TRUE-side select transistor that is a MOS transistor connected between the drain of the TRUE-side storage transistor and the TRUE-side bit line, and a drain connected to the BAR-side storage transistor and the BAR-side bit line. It is connected to a power supply through a switching transistor, a BAR side selection transistor which is a MOS transistor, a word line connected to the gates of the two selection transistors, a flip-flop configured by cross-connecting two CMOS inverters, and a switching transistor. Current mirror circuit A TRUE-side gate transistor connected between the drain of the TRUE-side storage transistor of the nonvolatile semiconductor memory element and the current-side mirror circuit and the TRUE-side input / output unit of the flip-flop; and the BAR side of the nonvolatile semiconductor memory element And a BAR side gate transistor connected between the drain of the storage transistor and the current mirror circuit and the BAR side input / output unit of the flip-flop.

  According to a fifth aspect of the present invention, in the second to fourth aspects of the present invention, the TRUE output inverter connected to the TRUE side input / output unit of the flip-flop and the BAR output inverter connected to the BAR side input / output unit are provided. , Further provided.

  According to a sixth aspect of the present invention, in the first to fifth aspects of the present invention, the gate voltage of the TRUE side storage transistor and the gate voltage of the BAR side storage transistor are controlled independently.

  A seventh aspect of the invention is characterized in that, in the first to fifth aspects of the invention, the gate voltage of the TRUE storage transistor and the gate voltage of the BAR storage transistor are controlled in common.

  According to an eighth aspect of the present invention, there is provided a nonvolatile semiconductor memory device having a memory array in which the nonvolatile semiconductor memory elements according to any one of the first to seventh aspects are arranged in a matrix of a plurality of rows and a plurality of columns. Features.

The typical configuration of the invention is summarized as follows.
The storage transistor is configured by a standard CMOS process, and the nonvolatile memory has a configuration including a pair of series circuits of a selection transistor and a storage transistor. Information on the memory transistor is stored in a flip-flop portion provided separately from the memory transistor.

  The memory transistor has a gate electrode through a gate insulating film above the channel between the source and drain, has an insulating film side spacer on the side of the gate electrode, and the drain side junction has a low impurity concentration. The LDD structure has a region, and the source side junction portion has a structure in which a low concentration region of the LDD structure portion is not formed (non-LDD structure).

  Then, a driving circuit for driving the nonvolatile memory applies a positive voltage to the gate electrode and the source with respect to the drain of the storage transistor, injects channel hot electrons into the insulating film side spacer, and writes information. A circuit for erasing information by applying a positive voltage to the source with respect to the drain and injecting avalanche hot holes into the insulating film side spacer.

Typical effects of the invention disclosed in the present application are as follows.
[1] The characteristics of a nonvolatile element obtained by making an offset structure on only one side of a transistor formed by a normal CMOS process are poor in stability and reproducibility and are likely to cause malfunction. Since the current difference between the pair of storage transistors is determined, the operational stability is greatly improved.

  [2] Since the gate voltage of the storage transistor can be supplied from the driver circuit, data determination can be performed in a region where the potential Vgs between the gate and source of the storage transistor is large, that is, a region where the amount of current is large, and the sense margin is improved.

  [3] The memory transistor and the flip-flop can be electrically separated, and even when this memory cell is used as output data for fuse use, no electric field stress is applied to the memory transistor. Will improve.

  First, the memory transistor used in the embodiment of the present invention will be described. FIG. 5 is a diagram showing a cross-sectional structure of a memory transistor used in the following embodiments. This figure shows the potential arrangement at the time of writing.

In FIG. 5, a P-type well 104 having a depth of 0.8 μm and an average boron concentration of 2 × 10 ¹⁷ cm ⁻³ is formed in the surface region of a P-type silicon substrate 101 having a resistivity of 10 Ωcm. In this P-type well 104, two storage transistors MCN1 and MCN2 separated by a plurality of trenches (element isolation) 102 having a depth of 250 nm are formed. In this figure, only one storage transistor (MCN1) is shown.

The storage transistor is an N-channel transistor, and has a drain 109 and a source 115 formed adjacent to the trench 102 on both sides in the surface region of the P-type well 104 and a drain extension formed in the peripheral region of the drain 109. 107. The drain 109 and the source 115 are each formed with an average arsenic concentration of 1 × 10 ²⁰ cm ⁻³ , and the drain extension 107 is formed with an average arsenic concentration of 5 × 10 ¹⁸ cm ⁻³ .

On the substrate of the channel region, which is the region between the drain 109 and the source 115 on the surface of the P-type well 104, a gate oxide film 105 with a thickness of 5 nm and a phosphorus concentration of 2 × 10 ²⁰ cm ⁻ with a thickness of 200 nm. ^A gate electrode 106 made of ³ polysilicon film is formed. Further, side spacers 108 and 108S made of an insulating film having a thickness of 50 nm are formed on both sides of the gate oxide film 105 and the gate electrode 106. Since no extension region is formed around the source 115, the side spacer 108S on the source side is exposed to the channel region of the substrate.

In the region of the P-type well 104, the region separated from the memory transistor by the trench 102 has an average boron concentration of 1 × 10 ²⁰ cm ⁻³ that is an electrode for grounding the P-type well 104. A P-type diffusion layer 111 is formed.

  In this memory transistor, the threshold voltage can be increased by injecting carriers into the side spacer 108S on the source side. Further, as will be described with reference to FIG. 10, the threshold voltage can be returned to the initial state by extracting the carriers injected into the side spacer 108S. As a result, the storage transistor stores data in a nonvolatile manner.

  This storage transistor can be structurally manufactured by a standard CMOS process, and the standard initial threshold voltage is 0.8 V. However, since it is a transistor having a special structure, the variation in threshold value is large. Therefore, it is difficult to ensure reliability by using this memory transistor alone as a memory element. For this reason, in the memory cell unit of this embodiment, the reliability is improved by using the storage transistors in pairs (MCN1, MCN2) and comparing their threshold values.

Embodiment 1
A memory cell unit (nonvolatile semiconductor memory element) and a memory device (nonvolatile semiconductor memory device) including the memory cell unit according to the first embodiment of the present invention will be described with reference to FIGS. In the following description, a signal line and a signal / voltage appearing on the signal line are referred to by the same symbol.

  FIG. 6 is a circuit diagram of a memory cell unit constituting one cell of the memory device. In this memory cell unit, writing and reading are performed via one word line WL and two bit lines BLT (BitLine-True) and BLB (BitLine-Bar).

  The memory transistors MCN1 and MCN2 which are N-type MOS transistors are transistors in which the side spacer portion on the source side is formed as a charge storage region. The memory transistors MCN1 and MCN2 are written (programmed) when negative charges are injected into the side spacer portions by channel hot electrons and the threshold value rises. The memory transistors MCN1 and MCN2 share the threshold voltage with the source line SL. A gate control line MGT is connected to the gate of the storage transistor MCN1, and another gate control line MGB is connected to the gate of the storage transistor MCN2. The drain portion (nodeT) of MCN1 is connected to the bit line BLT via a transfer gate MN1 that is an N-type MOS transistor. The drain part (nodeB) of MCN2 is connected to the bit line BLB via a transfer gate MN2 which is an N-type MOS transistor. A word line WL is connected to the gates of these transfer gates MN1 and MN2.

  FIG. 7 is a diagram showing a configuration of a memory device in which a plurality of memory cell units shown in FIG. 6 are connected in a row (row: X) and column (column: Y) array. In this memory device, a word line WL is provided for each row and is controlled independently by a word line driver. The bit lines BLT and BLB are provided for each column, and are controlled independently by the column selection circuit. Other signal lines (SL, MGT, MGB) are provided in common to all memory cell units (blocks) and controlled in common.

  Since the memory device of this embodiment has a configuration in which the memory cell unit itself does not have a flip-flop, the flip-flop is provided outside the memory array, that is, outside the sense amplifier circuit, and the memory cell read by the sense amplifier The information is transferred to the flip-flop and can be read from the outside.

  FIG. 8 is a diagram showing conditions for applying a write voltage to the memory cell unit. This figure shows the condition when data “0” is written, that is, when the threshold voltage of the memory transistor MCN1 is increased. When “0” is written, the word line WL is set to Vcc, the True side bit line BLT is set to 0 V, and the Bar side bit line BLB is set to Vcc under the condition that the source voltage SL and the gate voltages MGT and MGB are set to 6 V. As a result, when the True-side transfer gate MN1 is turned on, the node T becomes 1 V, for example, and a current of, for example, 300 μA flows through the storage transistor MCN1. This current causes channel hot electrons to be generated on the source SL side of the storage transistor MCN1, and electrons are injected into the side spacer portion on the SL side, whereby the threshold voltage of the storage transistor MCN1 rises (programs).

  Since the transfer gate MN2 is turned off, the storage transistor MCN2 that is not the target of writing has its node B raised to about 5V (6V-Vthn: Vthn = MCN2 threshold voltage) by charging from the source line SL side. Since there is no current path, channel hot electron injection does not occur and the threshold voltage remains unchanged.

  In addition, the voltage application condition for writing data “1”, that is, the voltage application condition for increasing the threshold voltage of the memory transistor MCN2, exchanges the voltage on the True side bit line BLT and the voltage on the Bar side bit line BLB. Then, BLT = Vcc and BLB = 0V are set. Other conditions are the same as when data “0” is written.

  In this embodiment, 6V is applied to both the gate MGT and the drain SL of the memory transistor MCN1, but this voltage is not limited to 6V, and may be a voltage different from the gate MGT and the drain SL.

  FIG. 9 is a diagram showing conditions for applying an erase voltage to the memory cell unit. The erase operation is performed for all memory cells (blocks) at once. Under the condition that the source line SL is set to 9V and the gate voltages MGT and MGB of the storage transistors MCN1 and MCN2 are set to 0V, the word line WL is set to Vcc and the bit lines BLT and BLB are set to 0V. When the transfer gates MN1 and MN2 are turned on with this voltage arrangement, nodeT and nodeB become 0V, and in the storage transistors MCN1 and MCN2, an avalanche hot hole HH is injected from the source (source line SL) side to the source side spacer. . The negative charges (electrons) trapped in the write operation of FIG. 8 are neutralized by the positive charges, thereby lowering the threshold voltages of the memory transistors MCN1 and MCN2 to the state before writing.

  FIG. 10 is a diagram showing conditions for applying a read voltage to the memory cell unit. The voltage application condition shown in this figure is based on the premise that the memory cell unit to be read is not indefinite, that is, the threshold voltages of the storage transistors MCN1 and MCN2 of the nonvolatile data storage unit are not Vth0. First, the source voltage SL of the storage transistors MCN1 and MCN2 is set to 0V, and the gate voltages MGT and MGB are set to Vcc. Under this condition, of the storage transistors MCN1 and MCN2, the storage transistor that is not programmed (low threshold voltage) is turned on, and the storage transistor that is programmed (high threshold voltage) remains off. . In this state, when the word line WL is set to Vcc and the transfer gates MN1 and MN2 are turned on, a current flows only on the side where the storage transistor is turned on, so this current difference appears as a voltage change of the bit lines BLT and BLB. This potential difference is read by a differential sense amplifier and transferred to a flip-flop provided outside the memory array, whereby data reading is completed. After the data is transferred to the flip-flop, the electric field stress on the storage transistor can be reduced by setting the gate voltages MGT and MGB of the storage transistors MCN1 and MCN2 to 0V.

  FIG. 11 is a diagram for explaining threshold voltages set in the memory transistors MCN1 and MCN2 by the write operation, that is, a diagram for explaining a data setting method for a nonvolatile memory cell. Here, when the threshold voltage of the storage transistor MCN1 is low (on) and the threshold voltage of the storage transistor MCN2 is high (off), the data is “1” and the threshold of the storage transistor MCN1 When the voltage is high (off) and the threshold voltage of the storage transistor MCN2 is low (on), the data is “0”.

  FIG. 6A shows a case before data setting, that is, when the threshold voltages of the storage transistors MCN1 and MCN2 are both in the initial state Vth0. Even in this state, the state of the nonvolatile memory cell is determined to be data "1" by the procedure shown in FIG.

  FIG. 5B shows the threshold voltage when data “0” is set in the nonvolatile memory cell. Writing of data “0” is realized by raising the threshold voltage of the storage transistor MCN1 from the initial state in FIG. 5A to Vth2 (Vth2> Vth0).

  FIG. 3C shows the threshold voltage when data “1” is set in the nonvolatile memory cell. Writing of data “1” is realized by raising the threshold voltage of the memory transistor MCN2 from the initial state in FIG. 5A to Vth2 (Vth2> Vth0).

  When the erase operation described with reference to FIG. 9 is performed, the state shown in FIG. 9A is restored even if the threshold voltage is controlled as shown in FIGS.

  Thus, since this memory cell can be lowered again to the initial state Vth0 even if the threshold voltages of the storage transistors MCN1 and MCN2 are increased, both the storage transistors MCN1 and MCN2 are in the initial state Vth0. Even in this case, the data can be forcibly determined to be “1”. Therefore, even if the data is used for a plurality of times of rewriting, the True side (storage transistor MCN1) and the Bar side (storage transistor MCN2) are used. The read margin, which is the difference between the threshold voltages, can be made sufficiently large.

  The above-described control method is based on the premise that the memory cell unit to be read is not indefinite, that is, the threshold voltages of the storage transistors MCN1 and MCN2 of the nonvolatile data storage unit are not Vth0. However, it may be necessary to read data from a memory cell unit whose data is not determined to be undefined in actual applications.

  FIG. 12 shows a case where a non-volatile data storage unit in which data is already written while recognizing the indefinite data as data “1” even when there are mixed data indefinite memory cell units. It is a figure which shows the voltage application conditions which determine data as usual. First, the source voltage SL of the storage transistors MCN1 and MCN2 is set to 0V, the gate voltage MGT of the storage transistor MCN1 is set to Vcc, and the gate voltage MGB of the storage transistor MCN2 is set to Vcc−ΔV (for example, ΔV = 0.2V). By setting the gate potential of the memory transistor MCN1 higher than the gate potential of the memory transistor MCN2 by ΔV, the memory transistor MCN1 is more easily turned on than the memory transistor MCN2, and the threshold voltages of the memory transistors MCN1 and MCN2 are both Vth0. When the data is indefinite, the data can be forcibly recognized as “1”. On the other hand, if data has already been written, the data is determined based on the difference between the threshold voltages of the storage transistors MCN1 and MCN2. The operation is the same as that described in FIG.

  Here, when the threshold voltages of the memory transistors MCN1 and MCN2 are both Vth0, this indicates that the memory transistors MCN1 and MCN2 are not rewritten, and the memory transistor deteriorates due to the rewrite. It is thought that there is not. For this reason, the magnitude of ΔV may be determined in consideration only of the initial threshold voltage variation of the transistor, and for example, about 0.2 V is considered sufficient. Here, the case where the data to be read is forcibly fixed to “1” when the data is indefinite has been described. However, the data may be fixed to “0” by inverting the potential difference of MGT-MGB. Is possible.

  FIG. 13 is a diagram for explaining a margin for determining data when the voltage application procedure shown in FIG. 12 is performed. In the initial state where the threshold voltages of MCN1 and MCN2 are both Vth0, as described above, the apparent threshold voltage on the MCN2 side is set to ΔV by making the MGB voltage lower by ΔV than the MGT voltage. The data is forcibly recognized as data “1”. In a memory cell in which data “0” has already been written, the margin decreases by ΔV. However, if Vth2−Vth0 = 1V and ΔV = 0.2V, the margin becomes 0.8V. . In the memory cell in which data “1” has already been written, the margin is increased by ΔV. If Vth2−Vth0 = 1V and ΔV = 0.2V, the margin is 1.2V. It becomes.

  FIG. 14 is a diagram illustrating a method for detecting the threshold voltage of the memory transistor MCN1. This figure shows the voltage application conditions when the threshold voltage is detected. By detecting the threshold voltage of the memory transistor using this method, the threshold voltage variation in the initial state, the amount of change in threshold voltage during write / erase operations, and the threshold voltage after rewriting are maintained at a high temperature It is possible to evaluate characteristics and the like.

  0 V is supplied to the source voltage SL and 1 V is supplied to the drain (nodeT) of the memory transistor MCN1. The drain is supplied with 1V from the bit line BLT via the transfer gate MN1. Under this condition, a MAP voltage (variable) is applied to the gate of the storage transistor. By making the MAP voltage variable, it is possible to determine the threshold voltage of the memory transistor MCN1 (the gate voltage necessary to flow a certain current).

  When the threshold voltage on the storage transistor MCN1 side is being measured, the gate voltage MGB of the storage transistor MCN2 is set to 0 V and turned off. Since the voltage between the source and drain of the storage transistor MCN2 is 0V, no current flows even if the transistor is turned on, but the storage transistor MCN2 is turned off so that the source voltage SL is not raised by some leakage current. It is. Even if the gate voltage MGB of the storage transistor MCN2 is the same MAP voltage as the gate voltage MGT of the storage transistor MCN1, there is no problem in operation.

  FIG. 14 shows voltage application conditions when measuring the threshold voltage of the storage transistor MCN1, but when measuring the threshold voltage of the storage transistor MCN2, the control of the bit lines BLT and BLB and the gate voltage are shown. The control of MGT and MGB may be reversed.

<< Embodiment 2 >>
FIG. 15 is a diagram showing another embodiment (Embodiment 2) of the memory cell unit. The difference from the first embodiment shown in FIG. 6 is that the gate voltages MG of the storage transistors MCN1 and MCN2 are made common. In this configuration, since the gate voltages MGT and MGB of the storage transistors MCN1 and MCN2 cannot be controlled separately as shown in FIG. 12, data in which the threshold voltages of the storage transistors MCN1 and MCN2 are both Vth0. Data cannot be determined to be “1” or “0” when indefinite, but it is useful when such data indefinite memory cells are not mixed because the structure is simplified.

  A memory device is configured by connecting the memory cells shown in FIG. 15 in an array as shown in FIG. The writing, erasing, and reading operations of this memory cell are the same as the operations shown in FIGS. 8, 9, and 10 of the first embodiment. Further, when the threshold voltage is detected, the gate voltages of the storage transistors MCN1 and MCN2 cannot be controlled separately as shown in FIG. 14, and therefore the gate voltage of the storage transistor on the non-measurement side is also controlled by the MAP voltage. Since the potential difference between the source and drain of the storage transistor on the non-target side is 0 V and no leakage current flows, there is no problem in operation.

  In the configuration of this embodiment, since the gate voltage control of the storage transistors MCN1 and MCN2 is shared as described above, the number of gate control drivers for the storage transistors can be reduced to about ½ compared to the first embodiment. It has the merit that.

<< Embodiment 3 >>
FIG. 16 is a diagram showing another embodiment (third embodiment) of the memory cell unit. The difference from the first embodiment shown in FIG. 6 is that a flip-flop and an inverter that inverts each flip-flop output are arranged in each memory cell of the memory array, assuming that the fuse output is used. It is a point. The connection form of the memory transistors MCN1, MCN2 and transfer gates MN1, MN2 is the same as that of the first embodiment shown in FIG.

  The flip-flop section is formed of PMOS transistors MP1 and MP2 having an N well potential and a source potential of Vcc, and NMOS transistors MN5 and MN6 having a P well potential of GND and a source potential of NCS. The PMOS transistor MP1 and the NMOS transistor MN5 constitute a TRUE side inverter, and the PMOS transistor MP2 and the NMOS transistor MN6 constitute a BAR side inverter.

  The TRUE side input / output unit LATT of the flip-flop is connected to the nodeT via the NMOS transistor MN3. The BAR side input / output unit LATB of the flip-flop is connected to the nodeB via the NMOS transistor MN4. The gate potentials of the NMOS transistors MN3 and MN4 are controlled by a control signal RESP.

  Further, the TRUE side input / output unit LATT of the flip-flop is connected to Vcc via the PMOS transistor MP3. The BAR side input / output unit LATB of the flip-flop is connected to Vcc via the PMOS transistor MP4. The gate potentials of the PMOS transistors MP3 and MP4 are controlled by a control signal PREN.

  The TRUE output LATT of the flip-flop becomes an input of an inverter formed by the PMOS transistor MP5 and the NMOS transistor MN7, and is output as an inverted output OUT. On the other hand, the BAR side output LATB of the flip-flop becomes an input of an inverter formed by the PMOS transistor MP6 and the NMOS transistor MN8, and is output as an inverted output IOUT. When using for fuses, either OUT or IOUT will be used, but to balance the parasitic capacitances of LATT and LATB when transferring data to the flip-flops, both to ensure operational stability It is arranged.

  FIG. 17 is a diagram showing a configuration of a memory device in which a plurality of memory cell units shown in FIG. 16 are connected in a row (row: X) and column (column: Y) array. In this memory device, a word line WL is provided for each row and is controlled independently by a word line driver. The bit lines BLT and BLB are provided for each column, and are controlled independently by the column selection circuit. Other signal lines (SL, MGT, MGB, PREN, NCS, RESP) are provided in common to all the memory cell units (blocks) and controlled in common.

  FIG. 18 is a diagram showing conditions for applying a write voltage to the memory cell unit. This figure shows the condition when data “0” is written, that is, when the threshold voltage of the memory transistor MCN1 is increased. The operation for the nonvolatile data storage unit is the same as that of the first embodiment. The flip-flop unit is electrically disconnected from the nonvolatile data storage unit by turning off the gate potential RESP of the NMOS transistors MN3 and MN4 with 0V.

  At the time of writing “0”, the word line WL is set to Vcc, the True side bit line BLT is set to 0 V, and the Bar side BLB is set to Vcc under the condition that the source voltage SL and the gate voltages MGT and MGB are set to 6 V. As a result, when the True-side transfer gate MN1 is turned on, the node T becomes 1 V, for example, and a current of, for example, 300 μA flows through the storage transistor MCN1. This current causes channel hot electrons to be generated on the source SL side of the storage transistor MCN1, and electrons are injected into the side spacer portion on the SL side, whereby the threshold voltage of the storage transistor MCN1 rises (programs).

  Since the transfer gate MN2 is turned off, the storage transistor MCN2 that is not the target of writing has its node B raised to about 5V (6V-Vthn: Vthn = MCN2 threshold voltage) by charging from the source line SL side. Since there is no current path, channel hot electron injection does not occur and the threshold voltage remains unchanged.

  In addition, the voltage application condition for writing data “1”, that is, the voltage application condition for increasing the threshold voltage of the memory transistor MCN2, exchanges the voltage on the True side bit line BLT and the voltage on the Bar side bit line BLB. Then, BLT = Vcc and BLB = 0V are set. Other conditions are the same as when data “0” is written.

  In this embodiment, 6V is applied to both the gate MGT and the drain SL of the memory transistor MCN1, but this voltage is not limited to 6V, and may be a voltage different from the gate MGT and the drain SL.

  FIG. 19 is a diagram showing conditions for applying an erase voltage to the memory cell unit. The operation for the nonvolatile data storage unit is substantially the same as that shown in FIG. 9 of the first embodiment. The flip-flop section is electrically disconnected from the storage transistor section by turning off the gate voltages RESP of the NMOS transistors MN3 and MN4 by setting them to 0V.

  The erase operation is performed for all memory cells (blocks) at once. Under the condition that the source line SL is set to 9V and the gate voltages MGT and MGB of the storage transistors MCN1 and MCN2 are set to 0V, the word line WL is set to Vcc and the bit lines BLT and BLB are set to 0V. When the transfer gates MN1 and MN2 are turned on with this voltage arrangement, the nodes T and nodeB become 0 V, and without the storage transistors MCN1 and MCN2, the avalanche hot hole HH is injected from the source (source line SL) side to the source side spacer. . This positive charge neutralizes the negative charges (electrons) trapped in the write operation of FIG. 18, thereby lowering the threshold voltages of the memory transistors MCN1 and MCN2 to the state before writing.

  FIG. 20 shows operating voltage conditions when transferring data in the nonvolatile data storage unit to the flip-flop unit in the memory cell unit. The voltage application condition shown in this figure is based on the premise that the memory cell unit to be read is not indefinite, that is, the threshold voltages of the storage transistors MCN1 and MCN2 of the nonvolatile data storage unit are not Vth0. Data transfer to the flip-flop unit is performed in the following procedure under the condition that the source voltage SL of the memory transistors MCN1 and MCN2 is 0V. At time t0, the gate voltages MGT and MGB of the storage transistors MCN1 and MCN2 are boosted from 0V to Vcc, and the NMOS side source voltage NCS of the flip-flop unit is boosted from 0V to Vcc-Vth to prepare for the sensing operation. By setting the PREN signal to 0 V at time t1, the precharging PMOS transistors MP3 and MP4 are turned on, and LATT and LATB are precharged to Vcc. Subsequently, by setting the RESP signal to Vcc at time t2, the NMOS transistors MN3 and MN4 are turned on, and the nodeT and nodeB which are the drain side potentials of the memory transistors MCN1 and MCN2 are charged to Vcc−Vth. By returning the PREN signal to Vcc at time t3, the precharge operation is completed, and a potential difference corresponding to the current difference between the storage transistors MCN1 and MCN2 appears in LATT and LATB. The state of the flip-flop unit is determined by returning the NCS potential to 0V at time t4 after waiting for a certain sensing time, and the RESP signal and the gate voltages MGT and MGB of the storage transistors MCN1 and MCN2 are returned to 0V at time t5. The operation is complete. After the operation is completed, the gate voltages MGT and MGB of the memory transistors MCN1 and MCN2 are 0 V, and it is possible to reduce the electric field stress on the memory transistors.

  The above-described control method is based on the premise that the memory cell unit to be read is not indefinite, that is, the threshold voltages of the storage transistors MCN1 and MCN2 of the nonvolatile data storage unit are not Vth0. However, it may be necessary to read data from a memory cell unit whose data is not determined to be undefined in actual applications.

  FIG. 21 shows that even when a memory cell unit with indefinite data is mixed, the indefinite data is recognized as data “1”, and the non-volatile data storage unit to which data has already been written is written data. It is a figure which shows the voltage application conditions which determine data as usual. 20 is different from the voltage application condition shown in FIG. 20 in that the gate voltage MGT of the memory transistor MCN1 is Vcc, the gate voltage MGB of the memory transistor MCN2 is Vcc−ΔV (for example, ΔV = 0.2 V), and the gate voltage of MCN1 is MCN2. That is, it is set higher than the gate voltage by ΔV. As a result, the memory transistor MCN1 is more likely to be turned on than the memory transistor MCN2, and the data set in the flip-flop unit can be obtained even when the data is indefinite such that the threshold voltages of the memory transistors MCN1 and MCN2 are both Vth0. It can be forcibly set to “1”. On the other hand, if data has already been written, the data is determined based on the difference between the threshold voltages of the storage transistors MCN1 and MCN2. The operation is the same as that shown in FIG.

  Here, when the threshold voltages of the memory transistors MCN1 and MCN2 are both Vth0, it indicates that the memory transistors MCN1 and MCN2 have not been rewritten, and there is no transistor deterioration due to rewriting. it is conceivable that. For this reason, the magnitude of ΔV may be determined in consideration only of the initial threshold voltage variation of the transistor, and for example, about 0.2 V is considered sufficient.

  Although the case where the data set in the flip-flop unit is forcibly set to “1” when the data is indefinite has been described here, the setting data is set to “0” by inverting the potential difference of MGT-MGB. It is also possible.

  FIG. 22 is a diagram illustrating a method for detecting the threshold voltage of the memory transistor MCN1. The voltage application conditions for the nonvolatile data storage unit are the same as the voltage application conditions shown in FIG. 14 of the first embodiment. The flip-flop unit is electrically disconnected from the nonvolatile data storage unit by turning off the NMOS transistors MN3 and MN4 with the gate voltage RESP being 0V.

  By detecting the threshold voltage of the memory transistor using this method, the threshold voltage variation in the initial state, the amount of change in threshold voltage during write / erase operations, and the threshold voltage after rewriting are maintained at a high temperature It is possible to evaluate characteristics and the like.

  0 V is supplied to the source voltage SL and 1 V is supplied to the drain (nodeT) of the memory transistor MCN1. The drain is supplied with 1V from the bit line BLT via the transfer gate MN1. Under this condition, a MAP voltage (variable) is applied to the gate of the storage transistor. By making the MAP voltage variable, it is possible to determine the threshold voltage of the memory transistor MCN1 (the gate voltage necessary to flow a certain current).

  When the threshold voltage on the storage transistor MCN1 side is being measured, the gate voltage MGB of the storage transistor MCN2 is set to 0 V and turned off. Since the voltage between the source and drain of the storage transistor MCN2 is 0V, no current flows even if the transistor is turned on, but the storage transistor MCN2 is turned off so that the source voltage SL is not raised by some leakage current. It is. Even if the gate voltage MGB of the storage transistor MCN2 is the same MAP voltage as the gate voltage MGT of the storage transistor MCN1, there is no problem in operation.

  FIG. 22 shows voltage application conditions when measuring the threshold voltage of the storage transistor MCN1, but when measuring the threshold voltage of the storage transistor MCN2, the control of the bit lines BLT and BLB and the gate voltage are shown. The control of MGT and MGB may be reversed.

<< Embodiment 4 >>
FIG. 23 is a diagram showing another embodiment (embodiment 4) of the memory cell unit. A difference from the third embodiment shown in FIG. 16 is that the gate voltages MG of the memory transistors MCN1 and MCN2 are made common. In this configuration, as shown in FIG. 21, since the gate voltages MGT and MGB of the storage transistors MCN1 and MCN2 cannot be controlled separately, data in which the threshold voltages of the storage transistors MCN1 and MCN2 are both Vth0. Data cannot be determined to be “1” or “0” when indefinite, but it is useful when such data indefinite memory cells are not mixed because the structure is simplified.

  The memory cells shown in FIG. 23 are connected in an array as shown in FIG. 17 to form a memory device. The writing, erasing and reading operations of this memory cell are the same as the operations shown in FIGS. 18, 19 and 20 of the third embodiment. Further, when the threshold voltage is detected, the gate voltages of the storage transistors MCN1 and MCN2 cannot be controlled separately as shown in FIG. 22, so the gate voltage of the storage transistor on the non-measurement side is also controlled to the MAP voltage. Since the potential difference between the source and drain of the storage transistor on the non-target side is 0 V and no leakage current flows, there is no problem in operation.

  In the configuration of this embodiment, since the gate voltage control of the storage transistors MCN1 and MCN2 is shared as described above, the number of gate control drivers for the storage transistors can be reduced to about ½ compared to the first embodiment. It has the merit that.

<< Embodiment 5 >>
FIG. 24 is a diagram showing another embodiment (fifth embodiment) of the memory cell unit of the memory device. As in the third embodiment shown in FIG. 16, assuming that the fuse output is used, a flip-flop and an inverter for inverting and outputting each flip-flop output are provided in each memory cell unit. The connection form of the memory transistors MCN1, MCN2 and transfer gates MN1, MN2 is the same as that of the first embodiment shown in FIG.

  The flip-flop section is formed by PMOS transistors MP1 and MP2 having an N well potential of Vcc and a source potential of PCS, and NMOS transistors MN5 and MN6 having a P well potential of GND and a source potential of NCS. The PMOS transistor MP1 and the NMOS transistor MN5 constitute a TRUE side inverter, and the PMOS transistor MP2 and the NMOS transistor MN6 constitute a BAR side inverter.

  The TRUE side input / output unit LATT of the flip-flop is connected to SENSE via the PMOS transistor MP7 and the NMOS transistor MN9. The BAR side input / output unit LATB of the flip-flop is connected to SENSEB through the PMOS transistor MP8 and the NMOS transistor MN10. The gate potentials of the PMOS transistors MP7 and MP8 are controlled by LATP, and the gate potentials of the NMOS transistors MN9 and MN10 are controlled by LATN. SENSSET and SENSEB are the drain potentials of the PMOS transistors MP3 and MP4 that are current-mirror connected, SENSE is connected to nodeT via the NMOS transistor MN3, and SENSEB is connected to nodeB via the NMOS transistor MN4. The gate potential of the NMOS transistors MN3MN4 is controlled by RESP.

  The TRUE output LATT of the flip-flop becomes an input of an inverter formed by the PMOS transistor MP5 and the NMOS transistor MN7, and is output as an inverted output OUT. On the other hand, the BAR side output LATB of the flip-flop becomes an input of an inverter formed by the PMOS transistor MP6 and the NMOS transistor MN8, and is output as an inverted output IOUT. When using for fuses, either OUT or IOUT will be used, but to balance the parasitic capacitances of LATT and LATB when transferring data to the flip-flops, both to ensure operational stability It is arranged.

  The operation of the memory cell unit of this embodiment is different from the operation of the memory cell unit of the third embodiment only in the data transfer method from the nonvolatile data storage unit to the flip-flop unit. Since RESP is set to 0V and the flip-flop is electrically disconnected, the operation is exactly the same. At the time of data transfer to the flip-flop unit, a voltage difference corresponding to the current difference between the memory elements MCN1 and MCN2 is stably output to SENSE and SENSEB, and the voltage is transferred to the flip-flop unit.

  A memory device is configured by connecting a plurality of memory cells shown in FIG. 24 in an array as shown in FIG.

  FIG. 25 is a diagram showing operating voltage conditions when data in the nonvolatile data storage unit is transferred to the flip-flop unit. The voltage application condition shown in this figure is based on the premise that the memory cell unit to be read is not indefinite, that is, the threshold voltages of the storage transistors MCN1 and MCN2 of the nonvolatile data storage unit are not Vth0. Data transfer to the flip-flop unit is performed in the following procedure under the condition that the source voltage SL of the memory transistors MCN1 and MCN2 is 0V. At time t0, the gate voltages MGT and MGB of the memory element transistors MCN1 and MCN2 are boosted from 0V to Vcc, the PMOS side source voltage PCS of the flip-flop is lowered from Vcc to 1 / 2Vcc, and the NMOS side source voltage NCS is decreased from 0V. The voltage is boosted to 1/2 Vcc to prepare for the sensing operation. By turning the NMOS transistors MN3 and MN4 on at time t1 by setting the RESP signal to Vcc, the memory side MCN1 and MCN2 drain side potentials SENSE and SENSEB flow through the current mirror-connected PMOS transistors MP3 and MP4. The potential is in accordance with the difference in current between the transistors MCN1 and MCN2. SENSEB is determined only by the current value on the storage transistor MCN2 side, and SENSE is determined by the current difference between the storage transistors MCN1 and MCN2. For example, when the current on the storage transistor MCN1 side is larger than the current on the storage transistor MCN2 side, SENSE <SENSEB, and vice versa. By changing LATP from Vcc to 0 V and LATN from 0 V to Vcc at time t2 when the potential difference between SENSE and SENSEB is ensured, the potentials SENSE and SENSEB are transferred to LATT and LATB which are inputs to the flip-flop unit. At time t3, LATP and LATN are returned to Vcc and 0 V, respectively, NCS is set to 0 V at time t4, and PCS is set to Vcc at time t5, so that data in the flip-flop unit is determined.

  After the potential difference between SENSET and SENSEB is transferred to the flip-flop, it is not necessary to pass a current to the storage elements MCN1 and MCN2, so that the RESP and the gate potentials MGT and MGB of the storage transistors are returned to 0 V at time t4. It becomes possible to alleviate electric field stress on the memory transistor.

  In the third embodiment, LATT and LATN, which are inputs to the flip-flop unit, sense a transient state in the process in which both of them are pulled down by the currents of the storage elements MCN1 and MCN2, while the flip-flop unit senses this embodiment. Then, there is a merit that the sense margin can be improved by generating a sufficient potential difference in SENSET and SENSEB in the current mirror section and transferring the stable potential to LATT and LATB.

  The above-described control method is based on the premise that the memory cell unit to be read is not indefinite, that is, the threshold voltages of the storage transistors MCN1 and MCN2 of the nonvolatile data storage unit are not Vth0. However, it may be necessary to read data from a memory cell unit whose data is not determined to be undefined in actual applications.

  In FIG. 26, even in the case where memory cell units with undefined data are mixed, the non-volatile data storage unit that has already written data while recognizing the undefined data as data “1”. It is a figure which shows the voltage application conditions which determine data as usual. This voltage application condition differs from the voltage application condition shown in FIG. 25 in that the gate voltage MGT of the memory transistor MCN1 is Vcc and the gate voltage MGB of MCN2 is Vcc−ΔV (eg, ΔV = 0.2V). The gate voltage is set higher by ΔV than the gate voltage of MCN2. As a result, MCN1 becomes easier to turn on than MCN2, and the data set in the flip-flop section is forcibly changed even when data is uncertain such that the threshold voltages of the storage transistors MCN1 and MCN2 are both Vth0. 1 ". On the other hand, if data has already been written, the data is determined based on the difference between the threshold voltages of the storage transistors MCN1 and MCN2.

  Here, when the threshold voltages of the memory transistors MCN1 and MCN2 are both Vth0, it indicates that the memory transistors MCN1 and MCN2 have not been rewritten, and there is no transistor deterioration due to rewriting. it is conceivable that. For this reason, the magnitude of ΔV may be determined in consideration only of the initial threshold voltage variation of the transistor, and for example, about 0.2 V is considered sufficient.

  Although the case where the data set in the flip-flop unit is forcibly set to “1” when the data is indefinite has been described here, the setting data is set to “0” by inverting the potential difference of MGT-MGB. It is also possible.

Embodiment 6
FIG. 27 is a diagram showing another embodiment (embodiment 6) of the memory cell unit of the memory device. A difference from the fifth embodiment shown in FIG. 24 is that the gate voltages MG of the storage transistors MCN1 and MCN2 are made common. In this configuration, since the gate voltages MGT and MGB of the storage transistors MCN1 and MCN2 cannot be controlled separately as shown in FIG. 26, data in which the threshold voltages of the storage transistors MCN1 and MCN2 are both Vth0. Data cannot be determined to be “1” or “0” when indefinite, but it is useful when such data indefinite memory cells are not mixed because the structure is simplified. A memory device is configured by connecting a plurality of memory cells shown in FIG. 27 in an array as shown in FIG.

<< Embodiment 7 >>
FIG. 28 is a diagram showing another embodiment (Embodiment 7) of the memory cell unit of the memory device. As in the third embodiment shown in FIG. 16, assuming that the fuse output is used, a flip-flop and an inverter for inverting and outputting each flip-flop output are provided in each memory cell unit. The connection form of the memory transistors MCN1, MCN2 and transfer gates MN1, MN2 is the same as that of the first embodiment shown in FIG.

  The flip-flop section is formed by PMOS transistors MP1 and MP2 having an N well potential of Vcc and a source potential of PCS, and NMOS transistors MN5 and MN6 having a P well potential of GND and a source potential of NCS. The PMOS transistor MP1 and the NMOS transistor MN5 constitute a TRUE side inverter, and the PMOS transistor MP2 and the NMOS transistor MN6 constitute a BAR side inverter.

  The TRUE-side input / output unit LATT and the BAR-side input / output unit LATB of the flip-flop become the drain potentials of the PMOS transistors MP3 and MP4 that are current mirror-connected. The TRUE side input / output unit LATT is connected to the node T via the NMOS transistor MN3, and the BAR side input / output unit LATB is connected to the node B via the NMOS transistor MN4. The gate potentials of the NMOS transistors MN3 and MN4 are controlled by RESP. On the source side of the PMOS transistors MP3 and MP4, PMOS transistors MP7 and MP8 whose gate potentials are controlled by SENSEN are connected in series with the power supply.

  The TRUE output LATT of the flip-flop becomes an input of an inverter formed by the PMOS transistor MP5 and the NMOS transistor MN7, and is output as an inverted output OUT. On the other hand, the BAR side output LATB of the flip-flop becomes an input of an inverter formed by the PMOS transistor MP6 and the NMOS transistor MN8, and is output as an inverted output IOUT. When using for fuses, either OUT or IOUT will be used, but to balance the parasitic capacitances of LATT and LATB when transferring data to the flip-flops, both to ensure operational stability It is arranged.

  The operation of the memory cell unit of this embodiment is different from the operation of the memory cell unit of the third embodiment only in the operation at the time of data transfer to the flip-flop unit, and the write operation and the erase operation are performed by setting RESP to 0V. Since the flip-flop section is electrically separated, the operation is exactly the same. Further, the operation at the time of data transfer of the memory cell unit of this embodiment is different from that of the fifth embodiment in that the voltage difference corresponding to the current difference between the storage transistors MCN1 and MCN2 flowing through the current mirror circuit is a flip-flop unit. The point that is directly applied to the input / output LATT and LATB, and the voltage difference is output stably and the state of the flip-flop unit is determined. Then, the current path of the PMOS current mirror unit is cut off by the PMOS transistors MP7 and MP8. It is a point.

  A memory device is configured by connecting a plurality of memory cells shown in FIG. 28 in an array as shown in FIG.

  FIG. 29 is a diagram showing operating voltage conditions when data in the nonvolatile data storage unit is transferred to the flip-flop unit. The voltage application condition shown in this figure is based on the premise that the memory cell unit to be read is not indefinite, that is, the threshold voltages of the storage transistors MCN1 and MCN2 of the nonvolatile data storage unit are not Vth0. Data transfer to the flip-flop unit is performed in the following procedure under the condition that the source voltage SL of the memory transistors MCN1 and MCN2 is 0V. At time t0, the gate voltages MGT and MGB of the memory element transistors MCN1 and MCN2 are boosted from 0V to Vcc, the PMOS side source potential PCS of the flip-flop is lowered from Vcc to 1 / 2Vcc, and the NMOS side source potential NCS is decreased from 0V. The voltage is boosted to 1/2 Vcc, and the SENSEN signal of the PMOS current mirror unit is set from Vcc to 0 V to prepare for the sensing operation. At time t1, the RESP signal is set to Vcc to turn on the NMOS transistors MN3 and MN4, so that the drain side potentials LATT and LATB of the storage transistors MCN1 and MCN2 flow through the current mirror-connected PMOS transistors MP3 and MP4, respectively. It becomes a potential corresponding to the difference in current between the storage transistors MCN1 and MCN2. LATB is determined only by the current value on the storage transistor MCN2 side, and LATT is determined by the current difference between the storage transistors MCN1 and MCN2. For example, when the current on the storage transistor MCN1 side is larger than the current on the MCN2 side, LATT <LATB, and in the opposite case, LATT> LATB. By setting NCS to 0 V at time t2 when the potential difference between LATT and LATB is secured, and setting PCS to Vcc at time t3, the data in the flip-flop unit is determined. After the data in the flip-flop unit is determined, in order to eliminate the through current between the flip-flop unit input / output, the PMOS current mirror unit, and the storage element unit, RESP is set to 0 V, the SENSEN signal is set to Vcc, and the storage elements MCN1 and MCN2 The gate potentials MGT and MGB are returned to 0V. As a result, the electric field stress on the memory transistor can be reduced.

  Similar to the fifth embodiment (see FIG. 25), it is possible to improve the sense margin by generating a sufficient potential difference in the PMOS current mirror section. Further, as compared with the fifth embodiment, there is an advantage that the number of transistor elements and the number of control signals can be reduced by one.

  The above-described control method is based on the premise that the memory cell unit to be read is not indefinite, that is, the threshold voltages of the storage transistors MCN1 and MCN2 of the nonvolatile data storage unit are not Vth0. However, it may be necessary to read data from a memory cell unit whose data is not determined to be undefined in actual applications.

  FIG. 30 shows the data written in the non-volatile data storage unit in which data is already written while recognizing the indefinite data as data “1” even in the case where data indefinite memory cell units are mixed. It is a figure which shows the voltage application conditions which determine data as usual. This voltage application condition differs from the voltage application condition shown in FIG. 29 in that the gate voltage MGT of the memory transistor MCN1 is Vcc and the gate potential MGB of MCN2 is Vcc−ΔV (for example, ΔV = 0.2V). The gate voltage is set higher by ΔV than the gate voltage of MCN2. As a result, MCN1 becomes easier to turn on than MCN2, and the data set in the flip-flop section is forcibly changed even when data is uncertain such that the threshold voltages of the storage transistors MCN1 and MCN2 are both Vth0. 1 ". On the other hand, if data has already been written, the data is determined based on the difference between the threshold voltages of the storage transistors MCN1 and MCN2.

  Here, when the threshold voltages of the memory transistors MCN1 and MCN2 are both Vth0, it indicates that the memory transistors MCN1 and MCN2 have not been rewritten, and there is no transistor deterioration due to rewriting. it is conceivable that. For this reason, the magnitude of ΔV may be determined in consideration only of the initial threshold voltage variation of the transistor, and for example, about 0.2 V is considered sufficient.

  Although the case where the data set in the flip-flop unit is forcibly set to “1” when the data is indefinite has been described here, the setting data is set to “0” by inverting the potential difference of MGT-MGB. It is also possible.

<< Embodiment 8 >>
FIG. 31 is a diagram showing another embodiment (Embodiment 8) of the memory cell unit of the memory device. A difference from the seventh embodiment shown in FIG. 28 is that the gate voltages MG of the memory transistors MCN1 and MCN2 are made common. In this configuration, since the gate voltages MGT and MGB of the storage transistors MCN1 and MCN2 cannot be controlled separately as shown in FIG. 30, data in which the threshold voltages of the storage transistors MCN1 and MCN2 are both Vth0. Data cannot be fixed to “1” or “0” when indefinite, but when such memory cells with indefinite data are not mixed, the number of storage transistor gate control drivers can be reduced, and the structure Is useful because it is simplified. A plurality of memory cells shown in FIG. 31 are connected in an array as shown in FIG. 17 to constitute a memory device.

A diagram showing a conventional memory cell configuration The figure explaining the data setting method and read margin in the conventional memory cell The figure which shows the write-voltage application procedure to the non-volatile data storage part in the conventional memory cell The figure explaining the data transfer method from the non-volatile data storage part to the flip-flop part in the said conventional memory cell The figure which shows the example of the cross-section of the memory transistor used for embodiment of this invention The figure which shows the structure of the memory cell unit which is Embodiment 1 of this invention. FIG. 3 is a diagram illustrating a configuration of a memory device in which the memory cell units according to the first embodiment are arranged in an array. The figure which shows the voltage application conditions at the time of the data writing of the memory cell unit of the said Embodiment 1. The figure which shows the voltage application conditions at the time of the data erasure of the memory cell unit of the said Embodiment 1. The figure which shows the voltage application conditions at the time of the data read of the memory cell unit of the said Embodiment 1. The figure explaining the data potential and read margin in the memory cell unit The figure which shows the voltage application conditions at the time of the data read of the memory cell unit of the said Embodiment 1. The figure explaining the data potential and read margin in the memory cell unit FIG. 3 is a diagram for explaining a threshold voltage detection method of a storage transistor of the memory cell unit according to the first embodiment. The figure which shows the structure of the memory cell unit which is Embodiment 2 of this invention. The figure which shows the structure of the memory cell unit which is Embodiment 3 of this invention. The figure which shows the structure of the memory device which arranged the memory cell unit of the said Embodiment 3 in the array form. The figure which shows the voltage application conditions at the time of the data writing of the memory cell unit of the said Embodiment 3. The figure which shows the voltage application conditions at the time of the data erasure of the memory cell unit of the said Embodiment 3. The figure which shows the voltage application conditions when transferring the data of a non-volatile data storage part to a flip-flop part in the memory cell unit of the said Embodiment 3. The figure which shows the voltage application conditions when transferring the data of a non-volatile data storage part to a flip-flop part in the memory cell unit of the said Embodiment 3. FIG. 6 is a diagram for explaining a threshold voltage detection method of a storage transistor of the memory cell unit according to the third embodiment. The figure which shows the structure of the memory cell unit which is Embodiment 4 of this invention. The figure which shows the structure of the memory cell unit which is Embodiment 5 of this invention. The figure which shows the voltage application conditions when transferring the data of a non-volatile data storage part to a flip-flop part in the memory cell unit of the said Embodiment 5. The figure which shows the voltage application conditions when transferring the data of a non-volatile data storage part to a flip-flop part in the memory cell unit of the said Embodiment 5. The figure which shows the structure of the memory cell unit which is Embodiment 6 of this invention. The figure which shows the structure of the memory cell unit which is Embodiment 7 of this invention. The figure which shows the voltage application conditions when transferring the data of a non-volatile data storage part to a flip-flop part in the memory cell unit of the said Embodiment 7. The figure which shows the voltage application conditions when transferring the data of a non-volatile data storage part to a flip-flop part in the memory cell unit of the said Embodiment 7. The figure which shows the structure of the memory cell unit which is Embodiment 6 of this invention.

Claims (8)

A TRUE-side storage transistor and a BAR-side storage transistor, which are MOS transistors capable of controlling the threshold voltage by electron injection near the gate;
A source line connected to the sources of the two storage transistors;
A TRUE side select transistor that is a MOS transistor connected between the drain of the TRUE side storage transistor and the TRUE side bit line;
A BAR side select transistor that is a MOS transistor connected between the drain of the BAR side storage transistor and a BAR side bit line;
A word line connected to the gates of the two select transistors;
A nonvolatile semiconductor memory element. A TRUE-side storage transistor and a BAR-side storage transistor, which are MOS transistors capable of controlling the threshold voltage by electron injection near the gate;
A source line connected to the sources of the two storage transistors;
A TRUE side select transistor that is a MOS transistor connected between the drain of the TRUE side storage transistor and the TRUE side bit line;
A BAR side select transistor that is a MOS transistor connected between the drain of the BAR side storage transistor and a BAR side bit line;
A word line connected to the gates of the two select transistors;
A flip-flop configured by cross-connecting two CMOS inverters;
Two precharging transistors connected in parallel with the load transistors of each of the two inverters;
A TRUE-side gate transistor connected between the drain of the TRUE-side storage transistor and the TRUE-side input / output unit of the flip-flop;
A BAR side gate transistor connected between a drain of the BAR side storage transistor and a BAR side input / output unit of the flip-flop;
A nonvolatile semiconductor memory element. A TRUE-side storage transistor and a BAR-side storage transistor, which are MOS transistors capable of controlling the threshold voltage by electron injection near the gate;
A source line connected to the sources of the two storage transistors;
A TRUE side select transistor that is a MOS transistor connected between the drain of the TRUE side storage transistor and the TRUE side bit line;
A BAR side select transistor that is a MOS transistor connected between the drain of the BAR side storage transistor and a BAR side bit line;
A word line connected to the gates of the two select transistors;
A flip-flop configured by cross-connecting two CMOS inverters;
A current mirror circuit connected to the power supply;
A TRUE side gate transistor connected between the drain of the TRUE side storage transistor and the current mirror circuit;
A BAR side gate transistor connected between the drain of the BAR side storage transistor and the current mirror circuit;
A TRUE analog switch connected between the current mirror side terminal of the TRUE side gate transistor and the TRUE side input / output unit of the flip-flop;
A BAR-side analog switch connected between a current mirror-side terminal of the BAR-side gate transistor and a BAR-side input / output unit of the flip-flop;
A nonvolatile semiconductor memory element. A TRUE-side storage transistor and a BAR-side storage transistor, which are MOS transistors capable of controlling the threshold voltage by electron injection near the gate;
A source line connected to the sources of the two storage transistors;
A TRUE side select transistor that is a MOS transistor connected between the drain of the TRUE side storage transistor and the TRUE side bit line;
A BAR side select transistor that is a MOS transistor connected between the drain of the BAR side storage transistor and a BAR side bit line;
A word line connected to the gates of the two select transistors;
A flip-flop configured by cross-connecting two CMOS inverters;
A current mirror circuit connected to a power supply via a switching transistor;
A TRUE side gate transistor connected between the drain of the TRUE side storage transistor of the nonvolatile semiconductor memory element and the current side mirror circuit and the TRUE side input / output unit of the flip-flop;
A BAR side gate transistor connected between the drain of the BAR side storage transistor of the nonvolatile semiconductor memory element and the BAR side input / output unit of the current mirror circuit and the flip-flop;
A nonvolatile semiconductor memory element.   The inverter for TRUE output connected to the TRUE side input / output part of the flip-flop, and the inverter for BAR output connected to the BAR side input / output part, respectively, further comprising: Nonvolatile semiconductor memory element.   6. The nonvolatile semiconductor memory element according to claim 1, wherein a gate voltage of the TRUE side storage transistor and a gate voltage of the BAR side storage transistor are controlled independently.   6. The nonvolatile semiconductor memory element according to claim 1, wherein a gate voltage of the TRUE side storage transistor and a gate voltage of the BAR side storage transistor are controlled in common.   A non-volatile semiconductor memory device having a memory array in which the non-volatile semiconductor memory elements according to claim 1 are arranged in a matrix of a plurality of rows and a plurality of columns.

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