JP2009129487A5 - - Google Patents

Claims (8)

A TRUE-side storage transistors and BAR-side storage transistor a controllable MOS transistors the threshold voltage by electron injection,
A source line to which the sources of the two storage transistors are connected in common ;
A TRUE side select transistor that is a MOS transistor connected between the drain of the TRUE side storage transistor and the TRUE side bit line;
A BAR side select transistor that is a MOS transistor connected between the drain of the BAR side storage transistor and a BAR side bit line;
And a word line connected to gates of the two select transistors,
A positive voltage is applied to the source line with respect to the drain voltage of the TRUE side storage transistor, the drain voltage of the BAR side storage transistor, the gate voltage of the TRUE side storage transistor, and the BAR side storage transistor gate voltage. By injecting positive charges into the TRUE side storage transistor and the BAR side storage transistor, the information written and stored in the TRUE side storage transistor and the BAR side storage transistor is erased.
A non-volatile semiconductor memory element. A sense amplifier circuit electrically connected to the drain of the TRUE storage transistor and the drain of the BAR storage transistor;
A flip-flop connected to the sense amplifier circuit;
The nonvolatile semiconductor memory element according to claim 1, further comprising: The gate voltage of the TRUE storage transistor and the gate voltage of the BAR storage transistor are each set to Vcc;
Setting the voltage applied to the word line to Vcc;
The potential difference between the voltages appearing on the TRUE side bit line and the BAR side bit line is read by the sense amplifier circuit.
The nonvolatile semiconductor memory element according to claim 2 . 4. The nonvolatile semiconductor memory element according to claim 3, wherein the potential difference read by the sense amplifier circuit is transferred to a flip-flop . The nonvolatile semiconductor memory element according to claim 4, wherein after the potential difference is transferred to the flip-flop, the gate voltage of the TRUE side storage transistor and the gate voltage of the BAR side storage transistor are each set to 0V . The nonvolatile semiconductor memory device according to any one of claims 1 to 5 wherein the gate voltage and the gate voltage of the BAR side storage transistors of the TRUE side storage transistors are controlled independently. The nonvolatile semiconductor memory device according to any one of claims 1 to 5 wherein the gate voltage and the gate voltage of the BAR side storage transistors of the TRUE side storage transistors are commonly controlled. A non-volatile semiconductor memory device having a memory array in which the non-volatile semiconductor memory elements according to claim 1 are arranged in a matrix of a plurality of rows and a plurality of columns.