JPS60257561A - Semiconductor device - Google Patents

Abstract

PURPOSE:To read informations positively at high speed by forming a memory cell by an MOS transistor with two floating gates and connecting a bit line to the memory cell through a transistor for transfer. CONSTITUTION:N channel MOS transistors 12, 14 each connected in series with N channel and P channel MOS transistors 11, 13 with two floating gates Ga are formed, and bit lines 15, 16 are connected severally to a sense amplifier. A gate line 17 is grounded on reading, and potential VCG is applied to a gate line 18. Since the transistor 11 is brought to an ON state and the transistor 13 to an OFF state when an information ''0'' is stored, the potential of the bit line 15 is low, and the potential of the bit line 16 is high. When an information ''1'' is stored, these bit lines are brought to reverse potential. These potential is inputted to the sense amplifier, and ''0'' or ''1'' of informations stored in a memory cell is decided. Accordingly, the memory cell is decided by the potential difference of the bit lines 15, 16, thus positively reading informations at high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and particularly to a memory cell of an EEPROM.

[Prior art]

A conventional semiconductor device of this type will be explained with reference to FIG.

In FIG. 1, 1 is an N-channel M with a floating gate.
O8) is a transistor. 2 is the N-channel MO8)
This is an N-channel MO8) transistor for transmitting information on the transistor 1 to the bit line 3. The focus line 3 is connected to a sense tube (not shown). Reference numeral 4 denotes a control line for controlling writing, erasing, and reading of the N-channel MOS transistor 1. 5 is a word line that controls the transistor 2 of the N-channel MO8).

One memory cell is thus configured.

Note that S, D, G, and G in FIG. 1 represent the source, drain, gate, and floating gate of each transistor.

Next, the operation will be explained.

When a high voltage VPP is applied to the bit line 3 and VH=Vpp +V+h (V'+h is the threshold voltage of the N-channel MOS transistor 2) to the word line 5, an N-channel MOS transistor with a floating gate G is applied. The potential of the drain D of the transistor 1 (MOS) is Vpp Ic. At this time, when the gate G of the N-channel MOS transistor 1 is grounded, an N diffusion layer (drain - floating gate) G, , floating gate G2 - gate G is formed between the drain of the N-channel MOS transistor 1 and the floating gate Ga0. Due to the capacitive coupling of , a certain high voltage vP determined by the capacitance ratio of these (□) is applied.

This high voltage vP causes a tunnel current to flow through the oxide film between the N diffusion layer and the floating boot 01. In other words, electrons tunnel from the floating gate Gm to the N+ diffusion layer, and the electrons accumulated in the floating gate G are removed.

As a result, the threshold voltage seen from the control gate line 4 of the N-channel MO8I-transistor 1 moves from the curve 1 in FIG.
OS) The transistor 1 becomes a depression type. It is assumed that this state is a state in which the memory is erased and information "0" is stored.

Conversely, the bit line 3 is grounded and a voltage is applied to the word line 5 to turn on the N channel MOS transistor 2.
Channel MOS) When the drain potential of transistor 1 is set near Ov and VPF is applied to control gate line 4 at the same time, N-channel MOS
A high voltage Vp is applied between the drain of the S transistor 1 and the floating Ga. Due to this high voltage vP, a tunnel current flows in the opposite direction to the above through the oxide film between the N diffusion layer and the floating boot 01, that is, from the N diffusion layer to the floating gates G, V
C, electrons tunnel and accumulate in the floating cage G. As a result, the threshold voltage of the N-channel MOS transistor 1 as viewed from the control gate line 4 is
It moves higher as shown by curve A from curve B in the figure, and becomes a second-order type. This state is assumed to be the state in which the memory transistor is written, and information ``'1'' is accumulated.
Suppose there is.

Next, the read operation will be explained.

The sources of the control gate line 4 and the N-channel MOS transistor 1 are grounded, and the bit line 3 is connected to a certain potential vR.
and set the word line 5 to “H” level to turn the N-channel MOS
) U/Raster 2 is turned on. Now, for example, if electrons are accumulated in Ga (N-channel MOS) transistor 1 and it becomes an enhancement type, then N
Channel MO8) Since the transistor 1 is in the off state, the potential of the focus line 3 is maintained at approximately Vl. On the other hand, floating gate G of transistor 1 (N-channel MOS).

When electrons are removed and the state becomes a depletion type, the N-channel MOS run raster 11 is on, so current flows from the focus line 3 to the N-channel MOS transistor 2. N-channel MOS) flows through transistor 1,
The potential of bit line 3 becomes lower than vR. The potential of this bit line 3 is detected by a sense amplifier to determine whether it is 0" or "1".

Conventionally, this type of memory cell is configured as described above, and since it is necessary to perform erasing and writing until the N-channel MOS transistor 1 becomes completely depletion type or enhancement type, it takes time to erase and write. In addition to this, there is also the drawback that it takes a long time to read out because a change in the potential of one focus line is detected.

[Summary of the invention]

This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and the memory cell is formed by a MOS transistor with two floating transistors, P channel and N channel, and each is connected through one transfer transistor. Speed up reading and memo by connecting the bit lines of!
+) To provide a semiconductor device that can reliably perform reading even if the amount of change in threshold voltage of a transistor is small.

An embodiment of the present invention will be described below with reference to the drawings.

[Embodiments of the invention]

FIG. 2 shows an embodiment of the present invention.

In this figure, 11 is an N-channel MOS transistor having a floating gate G. 13 is floating gate G,
It is a P-channel MO8) transistor with 12.
14 is the N-channel MOS transistor 1. These are enhancement-type N-channel MOS transistors connected in series to the P-channel MOS transistors 13 and 13, respectively.

First bit line 15. The second bit lines 16 are each connected to a flip-flop type sense amplifier (not shown). 17 and 18 are the N-channel MOS transistors 1. P-channel MO8) A first control gate line and a second controller that control writing, erasing, and reading of the transistor 13 i)2. Goo 4. A6゜Next, the operation will be explained.

The write and read operations are similar to the device shown in FIG. Second bit lines 15, 16 . 1st. It is assumed that the second control gate lines 17 and 18 are at the same potential.

First, when erasing, the first. The second con)c=-Lugut wire 17.18 is grounded, and the first. Second two focus lines 1
VPP is applied to 5.16. Floating gate G, to N channel MOS) transistor? 11. P channel MO
8) Because electrons tunnel to the drain of the transistor 13, N-channel MOS) Randimetal 11. P channel M
O8) Each control gate line 17 of transistor 13.
The threshold voltage as seen from 18 shifts to the lower side, and the N-channel MOS transistor 11 becomes a depression type as shown by curve A in FIG. As shown by curve C, it becomes an enhancement type. In this state, it is assumed that information "0" is stored in this memory cell.

When writing, the first. Second control gate line 17.
18 are applied with V and P, and the first. 2nd bin) line 15
．． 16 is grounded, the N-channel MOS) range meta 11. Since electrons tunnel from the drain of the P channel MO8) transistor 13 to the floating gas G, the N channel MOS) transistor 11. The threshold voltage of the P-channel MO8) transistor 13 moves to a higher side, and the N-channel MOS) transistor 11 becomes a pressure enhancement type as shown by curve B in FIG.
8) The transistor 13 becomes a depression type as shown by the curved line in FIG. In this state, it is assumed that information "1" is stored in this memory cell.

During reading, the first control gate line 11 is grounded, and a potential VCO as shown by E in FIG. 4 is applied to the second control gate line 18.

When information "0" is stored, the N-channel MOS transistor 11 is on and the P-channel MOS transistor 13 is off, so the first focus line 15
becomes low, and the potential of the second focus line 16 remains high. Also, when information "I" is accumulated,
Conversely, the potential of the first bit line 15 remains high, and the potential of the second bit line 15 remains high.
The potential of the bit line 16 becomes low.

This first. By inputting the second bit lines 15 and 16 to a slip-flop type sense amplifier (not shown), it is determined whether the information stored in the memory cell is 0' or 1''.

In this way, the first. In order to determine whether the memory cell is 0'' or ``1'' based on the potential difference between the second bit lines 15 and 16, N0II is determined based on the absolute value of the potential on one bit line.

This enables faster and more reliable reading than the conventional device that makes a determination of l''.

Furthermore, as mentioned above, when the threshold value of the N-channel MOS transistor 11 shifts from the depletion type to the enhancement type, at the same time, the P-channel MOS transistor 11 shifts from the depletion type to the enhancement type.
The threshold value of transistor 13 shifts in the opposite direction, ie from the enhancement type towards the depletion type. The same is true vice versa. For this reason, each MOS
) Even if the writing and erasing is insufficient such that the transistors 11 and 13 do not completely move between the enhancement type and the depletion type, the first. It is possible to generate a sufficient potential difference between the second two focus lines 15 and 16, and reliable reading can be performed.

Note that in the above embodiment, the N-channel MOS transistor 1. Even if the floating gate G of the P-channel MO transistor 13 is connected, the same effect as in the above embodiment can be obtained. Furthermore, by appropriately adjusting the channel doping of the P-channel MOS transistor 3, it is possible to reduce the potential Vco shown by E in FIG. As a result, the same result can be obtained even if the first and second control gate lines 17 and 18 are used in common. This embodiment will be explained with reference to FIG.

In FIG. 5, 19 is a common control cable. When erasing and writing, follow the steps in Figure 2' f, lh
& +-) long. □、U1、2. . □. two.

・1 Since the control gate lines 17 and 18 were set to the same potential,
This is the same as the case of one common control gate line 19 in FIG.

When reading, using one control gate line means that the gate potential of the P channel MOS transistor 130 is N
It is to set the gate potential to the same as the gate potential of the channel MO8) transistor 11. If, for example, "information addition" is written now, the P channel MO8) transistor 13 will be set to the same potential as the gate potential of the transistor 11.
Like the embodiment shown in the figure, it is of the enhancement type, so it is non-conductive, and the N-channel MO8) transistor 11 is of the depletion type and conductive, so the potential of the second bit line 16 is higher than that of the first bit line 15. . Also, information 6
1'' is written, the P-channel MOS transistor 13 is of the depletion type as explained in the embodiment of FIG. 2, and the N-channel MOS transistor 11 is of the enhancement type, so naturally the second bit line 16 is The potential of the first bit line 15 is low, and the potential of the first bit line 15 is higher than the potential of the second bit line 16. Therefore, in the case of FIG. 5, as in the embodiment of FIG. By manually inputting 15 and 16 to the 7 limb 7O block type sense 7 amplifier, it is possible to determine whether the information stored in the memory cell is 0'' or ``I''.

Furthermore, the N-channel MOS transistors 12 and 14 have P
It is clear that the same effect can be obtained even for channels by appropriately selecting the potentials of the focus lines 15 and 16 and the word line 5.

〔Effect of the invention〕

As explained above, the present invention includes two MOS transistors and a first MOS transistor. A second focus line, one word line, and a first.
A second control gate line, an N-channel MO8) having a floating gate, and a P-channel MO8) transistor having a transistor and a floating gate;
The drain of the S transistor is connected to the first bit line, the gate is connected to the word line, and the source is connected to the drain of the N channel MOS transistor.
8) The gate of the transistor is connected to the first control gate line, the drain of the other MOS transistor is connected to the second bit line, the gate is connected to the word line, and the source is connected to the drain of the P-channel MO8) transistor. Since the gate of this P-channel MO8) transistor is connected to the second control gate line, the potential difference between the two bit lines causes "0" and "l"
This has the advantage of enabling faster and more reliable reading than conventional devices that make decisions based on the absolute value of the potential of a single bit line.

Also, 1st. A structure in which the second control gate line is composed of one line has the advantage that the structure is simpler.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a conventional memory cell, FIG. 2 is a circuit diagram of a memory cell according to an embodiment of the present invention, and FIG. 3 shows V in a memory transistor of a conventional device. FIG. 4 is an aIog (gate voltage-drain current) characteristic curve diagram showing V in a memory transistor of a device according to an embodiment of the present invention. ,
-■ Characteristic curve diagram; FIG. 5 is a circuit diagram of a memory cell according to another embodiment of the present invention. In the figure, 5 is a word line, 11 is an N-channel MOS transistor with a floating gate, 13 is a P-channel MOS transistor with a floating gate, 12 and 13 are enhancement type N-channel MOS transistors, and 15 is a first transistor. 16 is a second bit line, 17 is a first track gate line, 18 is a second track gate line, and 19 is a common track gate line. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent: Sori Oiwa (2 others) Figure 1 Figure 2 Figure 3 Figure 5 Procedural amendment (voluntary) Kuchi Sowa 6% January 23rd, Commissioner of the Japan Patent Office 1, Indication of case Patent application 1982- 11587θ No. 2, title of the invention Semiconductor device 3, relationship to the case of the person making the amendment Patent applicant address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name
(601) Mitsubishi Electric Co., Ltd. Representative Hitoshi Katayama 4, Agent 5, Column 9 for detailed explanation of the invention in the specification subject to amendment 9 Column for brief explanation of drawings and drawing 6, Contents of amendment (1) ``Same enhancement type as the embodiment shown in FIG. 2'' on page 12, lines 7-8 of the specification is corrected to ``strong enhancement type.'' (2) Similarly, on page 12, lines 13 to 14, change ``It is a depression type as explained in the example in Fig. 2,'' to ``It is a weak enhancement type, but the control gate line 1
Since the potential of 9 is low enough, it is turned on.'' (3) Similarly, page 15, lines 2-3, r12,13.''
r12, 14''. (4) Amend Figure 5 of the drawing as shown in the attached sheet. I"2

Claims (2)

[Claims] (1) two MOS transistors; a second bit line, a word line, a first . It consists of a second control gate line, an N-channel MO transistor with a floating gate, and a P-channel MO transistor with a floating gate, the drain of the one MOS transistor is connected to the first bit line, and the gate is connected to the first bit line. The source of the word line is connected to the drain of the N-channel MO8) transistor, the gate of this N-channel M,O8) transistor is connected to the first gate line, and the The drain of the other MOS) transistor is connected to the second pinto line, the gate to the word line, and the source to the drain of the P-channel MOS transistor. A semiconductor device characterized in that the semiconductor device is connected to a control gate line of No. 2. (2) The first control gate line of the N-channel MOS transistor and the second control gate line of the P-channel MOS transistor.
2. The semiconductor device according to claim 1, wherein the control gate line is formed by one common line.