CN104269188A - OTP (One Time Programmable) or MTP (Multiple Time Programmable) memory module with dual-cell structure - Google Patents

OTP (One Time Programmable) or MTP (Multiple Time Programmable) memory module with dual-cell structure Download PDF

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Publication number
CN104269188A
CN104269188A CN201410483097.6A CN201410483097A CN104269188A CN 104269188 A CN104269188 A CN 104269188A CN 201410483097 A CN201410483097 A CN 201410483097A CN 104269188 A CN104269188 A CN 104269188A
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CN
China
Prior art keywords
otp
unit
cell
memory array
output
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CN201410483097.6A
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Chinese (zh)
Inventor
方钢锋
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Su Zhoufeng Microtronics Of Speeding AS
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Su Zhoufeng Microtronics Of Speeding AS
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Priority to CN201410483097.6A priority Critical patent/CN104269188A/en
Publication of CN104269188A publication Critical patent/CN104269188A/en
Priority to PCT/CN2015/084194 priority patent/WO2016041408A1/en
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
    • G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices

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  • Read Only Memory (AREA)
  • Static Random-Access Memory (AREA)

Abstract

The invention provides an OTP (One Time Programmable) or MTP (Multiple Time Programmable) memory module with a dual-cell structure. The OTP or MTP memory module comprises a memory array, a data selector, a reading amplifier and a controller; two adjacent memory cells in the memory array form one group when in a dual-cell working mode, and the two memory cells are called as a first cell and a second cell respectively and form a differential dual-cell structure; when the first cell is 1 and the second cell is 0, the output of the reading amplifier is 1, when the first cell is 0 and the second cell is 1, the output of the reading amplifier is 0, that is, the final output of the dual-cell structure is one bit. The OTP or MTP memory module has the advantages that the reliability of the OTP or MTP memory module is improved in a differential dual-cell working mode, applications in different occasions are combined, the memory module can be flexibly adaptive to the demands, and the cost performance is high.

Description

There is OTP or the MTP memory module of two cellular construction
Technical field
The present invention relates to OTP(disposable programmable) or MTP(multiple programmable) memory module, specifically a kind of OTP or MTP memory module with two cellular construction mode of operation.
Background technology
With the non-volatility memory of CMOS logic process compatibility due to the unconventional special non-volatility memory technique of its technique adopted, data to be kept or the requirement of reliability not necessarily can meet usually, need certain methods to make up.And different application scenarios, also there are different reliability requirements and cost requirement.The OTP/MTP memory module reliability of single unit working method can be lower, but do not waste area, and relative cost is low.As adopted two cell operation to improve reliability, area is just large one times, the corresponding raising of cost.If the application of different occasion combined, then more can reach the demand of application.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, a kind of OTP or MTP memory module that can work under differential two unit modes is provided, single working method can be had, also can switch between two kinds of modes.
According to technical scheme provided by the invention, a kind of OTP or MTP memory module with two kinds of working methods, comprise memory array, data selector, sensor amplifier and controller, output connection data selector switch and the sensor amplifier successively of memory array, controller is connected with memory array, data selector, sensor amplifier respectively; When two unit mode works, in described memory array, adjacent two storage unit are one group, are called first module, second unit, form differential two cellular constructions, when first module is " 1 ", when second unit is " 0 ", the output through sensor amplifier is " 1 ", when first module is " 0 ", when second unit is " 1 ", the output through sensor amplifier is " 0 ", and namely described pair of cellular construction finally exports is a bit; When single unit mode works, in described memory array, the output of each storage unit contrasts with reference signal in the sense amplifier, is less than reference signal and then exports " 0 ", is greater than reference signal and then exports " 1 ".
When only considering data reliability, can make and only have a kind of mode of two unit.
Advantage of the present invention is: work under differential two unit modes, improve the reliability of OTP or MTP memory module, the application of different occasion is combined meanwhile, flexible adaptive demand, reaches cost performance the highest.
Accompanying drawing explanation
Fig. 1 is the signal boundary (signal margin) of single unit working method.
Fig. 2 is the signal boundary of differential and double cell operation mode.
Fig. 3 is two bit of differential and double cellular construction, and each bit comprises two unit.
Fig. 4 is the output of two bit of differential and double cellular construction.
Fig. 5 is an OTP memory cell structural representation.
Fig. 6 is that two OTP memory cell are combined into two unit.
Fig. 7 is 2 × 2 arrays of two unit composition shown in Fig. 6, and output is 4 bit.
Fig. 8 is the cell array that Fig. 7 is taken as 2 × 4 under single unit working method, exports 8 bit.
Fig. 9 is the structural representation of whole OTP memory module.
Embodiment
Below in conjunction with drawings and Examples, the invention will be further described.
As shown in Figure 3, be two bits (bit<1:0>) in memory array of the present invention, each bit comprises two OTP/MTP storage unit (cell).Cell3 and cell2 is one group, cell1 and cell0 is one group.
As Fig. 4, cell3 and cell2 forms differential (differential) two cellular construction, when cell3 is " 1 ", when cell2 is " 0 ", through SA(sense amplifier, sensor amplifier) output bit<1> be " 1 ".Cell1 and cell0 forms differential two cellular constructions, and when cell1 is " 0 ", when cell0 is " 1 ", be " 0 " through the output bit<0> of SA, namely each pair of cellular construction finally exports is a bit.
Be illustrated in figure 1 the signal boundary of single unit working method, Program signal is programming signal, and Erase signal is erase signal, and reference is reference signal.If an OTP or MTP storage unit is the unit (" 1 ") of program, another OTP or MTP storage unit is the unit (" 0 ") of erase.So just signal is exaggerated one times, as shown in Figure 2.Also the uncertain part of handlebar reference (reference) signal also eliminates.Signal is larger, as long as the unit of the unit of program and erase difference a little, just can distinguish is " 1 " or " 0 ", and the reliability of data is higher.But so also many element number of a times, for OTP or the MTP memory array of an identical capacity.So we to same memory array design two kinds of working methods, can making it when requiring Large Copacity, single unit mode can be adopted to work.Namely the output of each storage unit in the sense amplifier with reference (reference) signal contrast, be less than reference signal and then export " 0 ", be greater than reference signal and then export " 1 ".Capacity has just doubled accordingly.Such OTP or MTP memory module can carry out work as the OTP/MTP memory module of two kinds of different capabilities, and a kind of is differential two cellular constructions, can also become the single unit structure of twice capacity.
Explain for the simple OTP memory module configuration of one below.
If Fig. 5 is an OTP memory cell, comprise two PMOS, in figure, PL is Program line(line program), WL is Word line(wordline), BL is Bit line(bit line), the substrate of two PMOS is by NWell(N trap) link together.This cellular construction is a signal, OTP or the MTP storer that the storage unit that the present invention is applicable to various different physical arrangement is formed.
In Fig. 6, the structure of two OTP memory cell composition differential, one is Program, and one is Erase.
Structure composing Fig. 7 of 2 × 2 Fig. 6, the one-piece construction of composition graphs 9 is visible: through the selection of WL (1), BL (1) and the BLb (1) of upper left compare output a data through SA, and upper right BL (0) and BLb (0) compares output a data through SA; Select through WL (0), BL (1) and the BLb (1) of lower-left compare output a data through SA, and upper right BL (0) and BLb (0) compares output a data through SA again.Amount to 4 bit data.
If the structure of Fig. 7 does single unit work, then as 2 × 4 cellular arraies as Fig. 8, the one-piece construction of composition graphs 9 is visible: through the selection of WL (1), 4 unit in top compare through SA and reference signal, export BL (3) respectively, BL (2), BL (1), BL (0); Select through WL (0), 4, below unit compares through SA and reference signal, exports BL (3) respectively, BL (2), BL (1), BL (0) again.Amount to 8 bit data.
Fig. 9 is the structural representation of whole OTP memory module, comprise memory array, data selector BL MUX, sensor amplifier SA and controller, output connection data selector switch and the sensor amplifier successively of memory array, controller is connected with memory array, data selector, sensor amplifier respectively, provides control signal.BL MUX(Bit line MUX) select the cell signal on not corresponding lines to enter SA.

Claims (2)

1. OTP or the MTP memory module of a two cellular construction, comprise memory array, data selector, sensor amplifier and controller, output connection data selector switch and the sensor amplifier successively of memory array, controller respectively with memory array, data selector, sensor amplifier is connected, it is characterized in that: in described memory array, adjacent two storage unit are one group, be called first module, second unit, form differential two cellular constructions, when first module is " 1 ", when second unit is " 0 ", output through sensor amplifier is " 1 ", when first module is " 0 ", when second unit is " 1 ", output through sensor amplifier is " 0 ", namely described pair of cellular construction finally exports is a bit.
2. one kind has OTP or the MTP memory module of two kinds of working methods, comprise memory array, data selector, sensor amplifier and controller, output connection data selector switch and the sensor amplifier successively of memory array, controller respectively with memory array, data selector, sensor amplifier is connected, it is characterized in that: when two unit mode works, in described memory array, adjacent two storage unit are one group, be called first module, second unit, form differential two cellular constructions, when first module is " 1 ", when second unit is " 0 ", output through sensor amplifier is " 1 ", when first module is " 0 ", when second unit is " 1 ", output through sensor amplifier is " 0 ", namely described pair of cellular construction finally exports is a bit,
When single unit mode works, in described memory array, the output of each storage unit contrasts with reference signal in the sense amplifier, is less than reference signal and then exports " 0 ", is greater than reference signal and then exports " 1 ".
CN201410483097.6A 2014-09-19 2014-09-19 OTP (One Time Programmable) or MTP (Multiple Time Programmable) memory module with dual-cell structure Pending CN104269188A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201410483097.6A CN104269188A (en) 2014-09-19 2014-09-19 OTP (One Time Programmable) or MTP (Multiple Time Programmable) memory module with dual-cell structure
PCT/CN2015/084194 WO2016041408A1 (en) 2014-09-19 2015-07-16 Otp or mtp memory module with dual-cell structure

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Application Number Priority Date Filing Date Title
CN201410483097.6A CN104269188A (en) 2014-09-19 2014-09-19 OTP (One Time Programmable) or MTP (Multiple Time Programmable) memory module with dual-cell structure

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016041408A1 (en) * 2014-09-19 2016-03-24 苏州锋驰微电子有限公司 Otp or mtp memory module with dual-cell structure

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130235678A1 (en) * 2012-03-09 2013-09-12 Actel Corporation Non-volatile memory array architecture optimized for hi-reliability and commercial markets
CN103366821A (en) * 2013-06-26 2013-10-23 苏州宽温电子科技有限公司 Improved differential framework OTP (One Time Programmable) storage unit based on series transistor

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104269188A (en) * 2014-09-19 2015-01-07 苏州锋驰微电子有限公司 OTP (One Time Programmable) or MTP (Multiple Time Programmable) memory module with dual-cell structure

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130235678A1 (en) * 2012-03-09 2013-09-12 Actel Corporation Non-volatile memory array architecture optimized for hi-reliability and commercial markets
CN103366821A (en) * 2013-06-26 2013-10-23 苏州宽温电子科技有限公司 Improved differential framework OTP (One Time Programmable) storage unit based on series transistor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016041408A1 (en) * 2014-09-19 2016-03-24 苏州锋驰微电子有限公司 Otp or mtp memory module with dual-cell structure

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