CN205645281U

CN205645281U - Signal setting -up time control circuit and because dynamic memory of this circuit

Info

Publication number: CN205645281U
Application number: CN201620467820.6U
Authority: CN
Inventors: 亚历山大; 段会福
Original assignee: Xian Unilc Semiconductors Co Ltd
Current assignee: Xian Unilc Semiconductors Co Ltd
Priority date: 2016-05-20
Filing date: 2016-05-20
Publication date: 2016-10-12
Anticipated expiration: 2026-05-20

Abstract

The utility model relates to a signal setting -up time control circuit and because dynamic memory of this circuit, including first delay cell, its special character lies in, still include second delay cell and multiple selector, the word line is chosen signal wlmimic to divide into two the tunnel through first delay cell, article one, the direct output signal SA_en1 in route, the second route is through second delay cell output signal SA_en2, signal SA_en1 and signal SA_en2 all export sensitive amplifier enable signal SA_en through the selection of multiple selector, the gating of signal refresh control multiple selector. The utility model provides a current dynamic memory all adopt the same signal setting -up time in the activation operation when refreshing the operation, the short technical problem of storage hold time, the utility model discloses dynamic memory's data hold time has effectively been improved.

Description

A kind of signal sets up time control circuit and dynamic memory based on this circuit

Technical field

This utility model relates to a kind of dynamic memory, and it thes improvement is that dynamically depositing prior art Signal in reservoir is set up the time (signal develop time) and is lengthened under Flushing status thus increase dynamic The state memory data retention time.

Background technology

As it is shown in figure 1, dynamic memory memory element is by a transistor, an electric capacity is constituted, number According to being stored on electric capacity, owing to there is leakage path, the electric charge on electric capacity can be lost, so dynamic memory Device is it is necessary to have refresh operation is with the data in holding capacitor.The refresh operation of dynamic memory in inside is It is made up of multiple activation (ACT) operation.As shown in Figure 2, activation manipulation principle is as follows: activate behaviour Before work, word line voltage is low, and bit line (bl) and reference bit lines (ref_bl) voltage are a medium voltage, Assuming that the value that memory element stores is ' 1 ', its voltage is generally the twice of medium voltage on bit line, activates After operation, through address decoding, the selected voltage of wordline raises, at this moment transistor N0 conducting, because Electric capacity top crown voltage is higher than bit-line voltage, so the flow of charge bit line on electric capacity C0, bit-line voltage by Edge up height, owing to the wordline of the memory element of reference bit lines connection does not has selected, so reference bit lines is protected Holding at medium voltage, such bit line can be increasing with the voltage difference between reference bit lines, when this voltage When difference is sufficiently large, sense amplifier is unlocked, and bit line and reference bit lines are helped pendulum by sense amplifier amplification Width, the value of such memory element is also write back again, refreshes and is namely based on this principle by multiple activation behaviour Make to form, open sense amplifier from wordline and start working and be referred to as signal during this period of time and set up the time (signal develop time), within this time, bit line is gradually established with the voltage difference of reference bit lines. Signal sets up that the time is the longest, and voltage difference is the biggest, and the probability that sense amplifier correctly amplifies is the biggest.If built Between immediately the shortest, voltage difference is the least, and as shown in Figure 3, sense amplifier can amplify error in data. So wanting to reach identical voltage difference, it is the longest that signal sets up the time, on the memory cell capacitor of needs Voltage is the lowest；It is the shortest that signal sets up the time, and the voltage on the memory cell capacitor of needs is the highest, holds The ability leaked electricity is the least.

As shown in Figure 4, normal Activate operate, after can then read operation, normal Activate operates reading Operation has time restriction, and this time is called tRCD, is limited to this time, and the signal time of setting up can not Oversize, the most just it is difficult to meet tRCD.And when refresh operation, after constituting the activation manipulation of refresh operation Face will not connect read operation, so comparing normal Activate operation, during refresh operation, the signal time of setting up can set Length is a bit.

The signal time of setting up that prior art uses when normal Activate operation and refresh operation is identical, Both limited by tRCD.When refresh operation, to set up the time smaller for signal, and signal sets up the time as previously mentioned The least, the voltage difference between bit line and reference bit lines is the least, and sense amplifier just has the biggest probability to put Serious mistake, and identical signal is set up under the time, memory cell voltages is the highest, and storage electric charge is the most, that The bit line reached is the biggest with the voltage difference of reference bit lines, as it was previously stated, electric leakage is the most, and memory element Voltage reduces, and storage electric charge tails off, so the electric leakage that time of setting up the shortest dynamic memory can bear is more Little, the data hold time of dynamic memory is the least.

Accompanying drawing 5 show existing dynamic memory signal and sets up the control method of time, activation manipulation or brush When newly operating, wlmimic raises and indicates that wordline is the most selected and raises, and wlmimic is through Postponement module Sdt timer produces SA_en signal, and SA_en signal sets up the time just by Postponement module sdt timer decision, Activation manipulation and refresh operation are all to determine that signal sets up the time with this Postponement module.

Summary of the invention

Identical signal is all used when activation manipulation and refresh operation in order to solve existing dynamic memory Setting up the time, the technical problem that the storage retention time is short, one of this utility model purpose provides a kind of signal Setting up time control circuit, second purpose is a kind of dynamic memory based on control circuit of offer, with Increase the data hold time of dynamic memory.

Technical solution of the present utility model:

A kind of signal sets up time control circuit, and including the first delay cell, it is characterized in that, also Including the second delay cell and MUX, wordline selected signal wlmimic is single by the first delay Unit is divided into two-way, direct output signal SA_en1 in Article 1 path, and Article 2 path postpones single through second Unit's output signal SA_en2, signal SA_en1 and signal SA_en2 is all through the selection of MUX Output sense amplifier enables signal SA_en, signal refresh and controls the gating of MUX.

When dynamic memory performs activation manipulation, signal refresh=0, Article 1 path gates；When dynamic When state memorizer performs refresh operation, signal refresh=1, Article 2 path gates.

Dynamic memory, including memory element and sense amplifier, also includes control circuit, described control Circuit includes the first delay cell, the second delay cell and MUX, the selected signal of wordline Wlmimic is divided into two-way by the first delay cell, direct output signal SA_en1 in Article 1 path, and Two paths are through the second delay cell output signal SA_en2, signal SA_en1 and signal SA_en2 All selections through MUX export sense amplifier and enable signal SA_en, signal refresh control The gating of MUX.

Of the present utility model had an advantage in that

This utility model is effectively increased the data hold time of dynamic memory.As shown in Figure 7, existing Dynamic memory under technology is had to use identical signal to set up the time due to refresh operation with activation manipulation, TRCD when being limited to activation manipulation limits, and this operating time is smaller, does not has during due to refresh operation Having tRCD to limit, the dynamic memory in this utility model adds signal when setting up when refresh operation Between, so relative to the dynamic memory of prior art, in this utility model, the signal of dynamic memory is built To grow between immediately.

Accompanying drawing explanation

Fig. 1 is the structural representation of dynamic memory memory element；

Fig. 2 is that dynamic memory activates (ACTIVE) operating principle figure；

Fig. 3 is the sense amplifier amplification mistake principle that dynamic memory signal sets up that deficiency of time causes Figure；

Fig. 4 is dynamic memory tRCD schematic diagram；

Fig. 5 is that existing dynamic memory signal sets up time control schematic diagram；

Fig. 6 is that this utility model dynamic memory signal sets up time control schematic diagram；

The contrast schematic diagram of activation manipulation and refresh operation signal voltage difference in Fig. 7 this utility model；

When Fig. 8 sets up identical signal voltage difference, prior art and contrast schematic diagram of the present utility model.

Detailed description of the invention

A kind of dynamic memory signal sets up time new control method.As shown in Figure 6, activation manipulation Or during refresh operation, wlmimic can raise, indicate that wordline is the most selected and raises, wlmimic Having two paths to SA_en, path 1 is only through Postponement module sdt timer1, and path 2 is through sdt timer1 After again through sdt timer2, the multichannel choosing that output SA_en through which paths is controlled by signal refresh Selecting device to determine, signal sets up the time just by the Postponement module decision in this two paths, works as dynamic memory When performing activation manipulation, refresh=0, wlmimic to SA_en are through path 1, and signal only sets up the time There is the delay of Postponement module sdt timer1, when dynamic memory performs refresh operation, refresh=1, Wlmimic to SA_en is through path 2, and signal sets up the time delay base at Postponement module sdt timer1 Add again the time delay of Postponement module sdt timer2 on plinth, thus achieve dynamic memory refresh Time add signal set up the time relative to normal Activate operation.It is that present case activates as shown in Figure 7 Operation sets up the time different effect reached with refresh operation signal, and it is long that refresh operation signal sets up the time, Voltage difference between the bit line and the reference bit lines that reach is the biggest.

As shown in Figure 8, want to reach the voltage difference between identical bit line and reference bit lines, due to this reality Long than prior art dynamic memory of time is set up with the signal of novel dynamic memory, so such as figure Shown in, to set up the time short, so wanting with this utility model due to signal for prior art dynamic memory Dynamic memory reaches the voltage difference of identical bit line and reference bit lines and is necessary for requiring its memory cell voltages Vcell2 is more than this utility model memory cell voltages Vcell1, it may be assumed that due to this utility model dynamic memory It is long that the signal of device sets up the time, compared to existing technology dynamic memory, will reach identical bit line and reference The Vcell that bit-line voltage difference needs is little, as it was previously stated, dynamic memory exists electric leakage, electric leakage causes depositing Electric charge on storage unit electric capacity reduces, and voltage decreases, and due to this utility model dynamic memory It is long that signal sets up the time, compared to existing technology dynamic memory, will reach identical bit line and reference bit lines The Vcell that voltage difference needs is little, so the receptible electric leakage of this utility model dynamic memory is many, namely This utility model dynamic memory data hold time dynamic memory compared to existing technology is long, so this reality With the novel data hold time effectively improving dynamic memory.

It is illustrated in figure 6 dynamic memory signal of the present utility model and sets up time control structure, dynamically deposit When reservoir activation manipulation (ACTIVE) or refresh operation (refresh), wlmimic signal all can be uprised by low, Indicating that wordline (wordline) is enabled, during activation manipulation, refresh signal is low, refresh signal Controlling selector (mux) selects path1 to produce sense amplifier enable signal SA_en, i.e. signal is set up Time is only determined by delay circuit sdt timer1；During refresh operation, refresh signal is high, refresh Signal controls selector (mux) and selects path2 generation sense amplifier enable signal SA_en, i.e. signal to build Determined by delay circuit sdt timer1 and sdt timer2 between immediately.So during refresh operation, signal is set up The time of many delay circuits sdt timer2 when time compares activation manipulation.

Claims

1. signal sets up a time control circuit, including the first delay cell, it is characterised in that also wrap Including the second delay cell and MUX, wordline selected signal wlmimic passes through the first delay cell Being divided into two-way, direct output signal SA_en1 in Article 1 path, Article 2 path is through the second delay cell Output signal SA_en2, signal SA_en1 and signal SA_en2 are all defeated through the selection of MUX Go out sense amplifier and enable the gating of signal SA_en, signal refresh control MUX.

Signal the most according to claim 1 sets up time control circuit, it is characterised in that: when dynamically When memorizer performs activation manipulation, signal refresh=0, Article 1 path gates；When dynamic memory is held During row refresh operation, signal refresh=1, Article 2 path gates.

3. dynamic memory based on the control circuit described in claim 1, including memory element and sensitive Amplifier, it is characterised in that: also include control circuit, described control circuit include the first delay cell, Second delay cell and MUX, wordline selected signal wlmimic is divided by the first delay cell For two-way, direct output signal SA_en1 in Article 1 path, Article 2 path is defeated through the second delay cell Go out signal SA_en2, signal SA_en1 and signal SA_en2 all to export through the selection of MUX Sense amplifier enables signal SA_en, signal refresh and controls the gating of MUX.

Dynamic memory the most according to claim 3, it is characterised in that: when dynamic memory performs During activation manipulation, signal refresh=0, Article 1 path gates；When dynamic memory performs refresh operation Time, signal refresh=1, Article 2 path gates.