CN102194513B - Circuit, method and memory for automatically adjusting refresh frequency of memory - Google Patents
Circuit, method and memory for automatically adjusting refresh frequency of memory Download PDFInfo
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Abstract
The invention belongs to the technical field of memories, and particularly relates to a circuit, a method and a memory for automatically adjusting the refresh frequency of the memory. In the circuit, the data retention condition of a storage array monitored by the circuit is judged by reading redundancy storage units which respectively stores data 0 and data 1, and the refresh frequency of the memory can be automatically adjusted by the circuit according to different working conditions, forming process conditions and other factors which affect data retention characteristics. Therefore, the memory has the characteristic of low power consumption for refresh. Moreover, the refresh of the memory is automatically adjusted on chips, and off chip control is not required.
Description
Technical field
The invention belongs to the memory technology field, be specifically related to the refresh operation of storer, relate in particular to a kind of circuit, method and storer thereof of adjusting the memory refresh operation frequency by the monitoring redundancy unit automatically.
Background technology
Any storer all has certain data and keeps (Data Retention) characteristic, it also is the retention times of data in storage unit, different memory data retention performance differences, for example, the memory data that has can keep more than 10 years, and the data hold time of the storer that has has only short a few minutes or shorter.Equally, for same storer, its difference of making the process conditions that form also can cause the data retention characteristics difference of storer, for example in the same storage array, because the influence of process fluctuation can cause the relatively poor cell data retention performance of process conditions relatively poor.Further, for same storage unit, different conditions of work, data storage characteristics be difference to some extent also, storage data " 0 " and store also difference to some extent of data " 1 ", for example, the more high data retention characteristics of the working temperature of storer is more poor, and data retention characteristics also can be influential with factors such as operating voltage.
Usually, for the relatively poor relatively storer of data retention characteristics, need before the data failure of storing, carry out refresh operation to storer.The data hold time of storer is more long, and selected refreshing frequency is relatively more low.For the storage array that comprises a plurality of storage unit, since the data hold time between the unit be exist either large or small difference (for example, the data hold time difference that the difference of the process conditions that form, the difference of working temperature cause), generally can determine the frequency of refresh operation according to the worst unit of relative data storage characteristics in the array.The mode that refreshes of prior art is to provide a refresh signal at set intervals by peripheral control unit, tell storer this refreshed, so have the signaling interface of a REFRESH in the outside of storer (also being outside the sheet).
If under different data retention characteristics situations, all select the highest refreshing frequency under the worst case, good storer caused the situation of refresh operation can to cause the relative data retention performance, and this mistake refreshes and can cause unnecessary refresh operation power consumption and also life-span of storer be produced certain influence.Therefore, be necessary to propose a kind of method of automatic adjustment refresh operation frequency, also namely regulate the method for refreshing frequency according to the variation of storer self-condition (for example process conditions of Xing Chenging, condition of work etc.) automatically.When self-condition relatively poor (process conditions are poor, the working temperature height), self refresh operation can be operated on the higher frequency to prevent data failure, thereby power consumption also can raise.On the contrary, when self-condition is relatively good (process conditions are good, and working temperature is low), data can keep longer time thereby refresh interval can be adjusted into the longer power consumption decline that makes automatically.We claim this method for adjusting the scheme of memory refress frequency automatically.
Summary of the invention
The technical problem to be solved in the present invention is, for the power consumption that reduces refresh operation, reduce the frequency of refresh operation as far as possible, proposes a kind of technical scheme of automatic adjustment memory refresh operation frequency.
For solving above technical matters, the invention provides a kind of circuit of automatic adjustment memory refresh operation frequency, it comprises:
Store the redundant storage unit of data " 0 " and data " 1 " respectively;
The timing read/write circuit module of redundant storage unit;
The difference between current module is used for the read current of the redundancy unit of the read current of the redundancy unit of storage " 1 " and storage " 0 " is asked difference between current;
Comparison module is used for described difference between current and reference current are compared; And
Refresh pulse produces circuit module, is used for exporting the refresh pulse signal according to the output result of comparison module.
Circuit according to automatic adjustment memory refresh operation frequency provided by the present invention, wherein, refresh pulse produces circuit module when output refresh pulse signal, and also output feedback signal to described timing read/write circuit module is operated redundant storage unit is write again " 0 " or " 1 ".
According to the circuit of automatic adjustment memory refresh operation frequency provided by the present invention, wherein, described redundant storage unit can be for more than two, and it is arranged at every capable first and last and every row first and last of the storage array of monitoring.
Storing value in the described redundant storage unit alternately is written as " 1 " and " 0 ", the read current of the redundancy unit of described storage " 1 " is the mean value of read current of the redundancy unit of all storages " 1 ", and the read current of the redundancy unit of described storage " 0 " is the mean value of read current of the redundancy unit of all storages " 0 ".
Described redundant storage unit is arranged on the middle part of the storage array of monitoring, and perhaps is arranged on the middle part of the storage array of monitoring at random.
As preferred embodiment, the data retention characteristics of described redundant storage unit is worse than the data retention characteristics of the storage unit of the storage array of monitoring relatively.
The manufacturing of described redundant storage unit forms the technology relative different and forms technology so that the data retention characteristics of redundant storage unit is worse than the data retention characteristics of the storage unit of the storage array of monitoring relatively in the storage unit manufacturing of the storage array of monitoring.
The device architecture relative different of described redundant storage unit in the device architecture of the storage unit of the storage array of monitoring so that the data retention characteristics of redundant storage unit is worse than the data retention characteristics of the storage unit of the storage array of monitoring relatively.
According to the circuit of automatic adjustment memory refresh operation frequency provided by the present invention, wherein, described storer is for distinguishing the storer of " 0 " one state with the read current form.Described storer can be buoyancy aid shape dynamic RAM.
According to the circuit of automatic adjustment memory refresh operation frequency provided by the present invention, it also comprises the reference current source for generation of reference current.
The present invention provides a kind of method of automatic adjustment memory refresh operation frequency simultaneously, and it may further comprise the steps:
When (1) storage array carries out refresh operation, simultaneously redundant storage unit is stored data " 0 " and " 1 " respectively;
(2) regularly respectively the redundant storage unit of storage " 0 " and the redundant storage unit of storage " 1 " are carried out read operation;
(3) read current of the redundancy unit of depositing " 1 " and the read current of depositing the redundancy unit of " 0 " are asked difference between current;
(4) described difference between current and reference current are compared; If difference between current greater than reference current, then repeats to enter step (2); If difference between current is less than or equal to reference current, then produce circuit module by refresh pulse and produce the refresh pulse signal, enter step (1).
The present invention further provides a kind of storer of automatic adjustment memory refresh operation frequency, it comprises storage array, line decoder, column decoder, sense amplifier, word line driver module, bit-line drive module, Logic control module, and comprise the above and the circuit of arbitrary automatic adjustment memory refresh operation frequency, the circuit output refresh pulse signal of described automatic adjustment memory refresh operation frequency is to described Logic control module.
Technique effect of the present invention is, this circuit judges that by reading the redundant storage unit of storing data " 0 " and data " 1 " respectively the data of the storage array that it is monitored keep situation, the factor that it can be according to different conditions of work, form process conditions etc. influences data retention characteristics is adjusted the refresh operation frequency of storer automatically, therefore, this storer has refresh operation characteristics low in energy consumption.And the refresh operation of this storer is to adjust automatically on the sheet, does not need sheet to control outward.
Description of drawings
Fig. 1 is the buoyancy aid shape dynamic RAM synoptic diagram of prior art.
Fig. 2 is that prior art is about the synoptic diagram of the data retention characteristics of FBC storer.
Fig. 3 is the circuit diagram that the automatic adjustment memory refresh operation frequency that provides is provided in the present invention.
Fig. 4 is memory construction synoptic diagram provided by the invention, that comprise the circuit of automatic adjustment memory refresh operation frequency embodiment illustrated in fig. 3.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in further detail below in conjunction with accompanying drawing.
In following specific embodiment, (Floating body transistorcell FBC) is elaborated for the thought scheme of example to the refreshing frequency of the automatic adjustment storer of this invention with buoyancy aid shape dynamic RAM in selection.
Figure 1 shows that the buoyancy aid shape dynamic RAM synoptic diagram of prior art.Wherein Fig. 1 (a) is the cellular construction synoptic diagram of buoyancy aid shape dynamic RAM, the element circuit synoptic diagram of Fig. 1 (b) buoyancy aid shape dynamic RAM, wherein 601 is floater area, this storer 600 is whether to have many sons (be example many sons refer to the hole) to store data in floater area with NMOS, the hole that produces by ion collision is stored in the tagma and finishes the one writing operation, finishes erase operation by " taking " the PN junction positively biased between body-source/leakage away hole.Thereby the cavitation that is stored in buoyancy aid changes transistorized threshold voltage in depletion region, thereby the leakage current of the difference of this threshold voltage during by read operation is to distinguish difference " 1 " or " 0 " state.Therefore, the FBC storer is the storer of distinguishing store status with the size of read current.
Figure 2 shows that prior art is about the synoptic diagram of the data retention characteristics of FBC storer.As shown in Figure 2, for " 0 " and " 1 " two states, be significantly shorter than the data hold time of (25 degrees centigrade) under the room temperature at the data hold time under 85 degrees centigrade.Therefore as can be seen, along with the variation of the condition of work (for example working temperature) of FBC storer needs, because the variation of data hold time, need adjust the frequency of refresh operation adaptively.
Figure 3 shows that the circuit diagram of the automatic adjustment memory refresh operation frequency that provides is provided in the present invention.As shown in Figure 3, this circuit 700 mainly comprises redundant storage unit 701 and 702, regularly read/write circuit module 706, difference between current module 707, comparer 709 and refresh pulse produce circuit module circuit 711.Wherein, when powering on, write in the redundant storage unit 701 in " 1 ", the redundant storage unit 702 and write " 0 ".Common word line DWL 703 by redundant storage unit can choose the redundant storage unit 701 of storage " 1 " and the redundant storage unit 702 of storage " 0 ", one termination bit line DBL1 704 of redundant storage unit 701, one termination bit line DBL0 705 of redundant storage unit 702, redundant storage unit 701 and 702 common grounds, regularly read/write circuit 706 can apply about the signal read in 703,704 and 705, realize simultaneously the read operation to redundant storage unit 701 and 702, " regularly " described in its read operation refers to the time interval T to the read operation of redundancy unit, the time interval T of concrete read operation is generally much smaller than its common data hold time, be example with the FBC storer, if data hold time is 1 millisecond, T can select the time interval timing read operation redundant storage unit of 1-10 microsecond so.At that time, should be appreciated that specifically the time quantum of " regularly " was not limited by present embodiment.
See also Fig. 3, after the redundant storage unit 701 of the redundant storage unit 702 of each storage " 0 " and storage " 1 " carried out read operation, its read current I0, I1 were admitted to difference between current module 707 modules respectively in the hope of difference between current (I1-I0).Automatically the circuit of adjustment memory refresh operation frequency also comprises the reference current source 708 for generation of reference current Iref, need to prove that the reference current Iref of its generation does not change substantially with respect to the factor that influences the memory data retention performance (for example working temperature).Reference current Iref and difference between current (I1-I0) carry out current ratio in comparer 709, in this embodiment, comparer 709 is subjected to comparison enable signal 710 controls of regularly read/write circuit module 706 outputs simultaneously, thereby comparer is only just compared when reading at every turn.When (I1-I0)＞Iref, comparer output Φ RFSH is low level 0; In case (I1-I0)≤during Iref, comparer output Φ RFSH becomes high level 1, trigger refresh pulse immediately and produce circuit module 711 and produce the refresh pulse Φ RFSH in cycles, storage array is carried out refresh operation line by line.Simultaneously, in this embodiment, refresh pulse produces circuit module 711 also can provide a feedback signal Φ FB two redundant storage units 701 and 702 also to be write back again the state of " 1 ", " 0 " respectively to timing read/write circuit module in first cycle of refreshing startup.From the above, no matter storage array is under mode of operation or data hold mode, this circuit can both be followed the tracks of variation of temperature adaptively and change its refreshing frequency, has reduced the frequency of refresh operation as far as possible, thereby has farthest saved the power consumption of refresh operation.
This invention further provides the storer of the circuit 700 of the automatic adjustment memory refresh operation frequency described in this specific embodiment of use.
Figure 4 shows that memory construction synoptic diagram provided by the invention, as to comprise the circuit of automatic adjustment memory refresh operation frequency embodiment illustrated in fig. 3.In this embodiment, the FBC storer comprises the FBC cell array, and the FBC cell array is to be arranged by the form of row and column by the FBC unit to form.Word line and bit line cross arrangement, FBC unit place the cross arrangement point.This storer also comprises line decoder, column decoder, sense amplifier, word line driver module, bit-line drive module, Logic control module.The function of Logic control module is that control word line driver module and bit-line drive module keep the sequential in operation and the refresh operation in read operation, write operation, data.Wherein selected line chooses the bit-line voltage of row to change and can differentiate by sense amplifier, and compares with Iref2 (reference current), obtains sense data.Row address is counted the line of input code translator, is used for choosing WWL and the RWL of array, column address input column decoder.Wherein the refresh operation of FBC cell array is circuit 700 controls that are subjected to adjust automatically the memory refresh operation frequency, automatically adjust the direct input logic control module of refresh pulse Φ RFSH signal of the circuit 700 of memory refresh operation frequency, to realize the control of refresh operation.In this storer, thereby the data variation of redundant storage unit can be monitored the data situation of storage unit in the storage array and can automatically be adjusted refreshing frequency.Further, in this embodiment, redundant storage unit can be identical with the storage unit of storage array, and its physical location also can be close to storage array, and in same manufacture process, form, thereby make redundancy unit reflect the storage array data retention characteristics in optimization ground.
The refresh operation of the self-refresh of the described storer of Fig. 4 can be hidden in the sheet (being the inside of storer), namely can't see this REFRESH signaling interface in the storer outside.The cycle of inner self-refresh can be regulated on internal dynamic ground and change voluntarily, and be the refresh cycle of a definite value unlike external control, and the outside also refresh operation of control store again, finished voluntarily by storer, also easy to be many in operation.
Please continue to see also Fig. 3, in this embodiment, just illustrate among the figure to have provided two redundant storage units of storage " 1 " and " 0 " respectively, one of them fixed storage " 1 ", another fixed storage are " 0 ".These two redundant storage units can be to select from storage array; Also can be the storage unit of as far as possible close storage array, thereby can reflect to optimization the real data retention performance situation of storage unit in the array.But in some cases, two redundant storage units can not truly reflect the average case of the most of data cells in the storage array, therefore, also can select plural FBC unit as redundant storage unit.In another embodiment, can a redundancy unit all be set separately in every capable first and last and every row first and last of storage array, storing value in the redundant storage unit alternately is written as " 1 " and " 0 ", like this, and the redundant storage unit of the storage redundant storage unit of " 0 " and storage " 1 " each half.When carrying out the read operation of redundant storage unit, with the read current summation of the redundant storage unit of all storages " 1 " average, draw the read current I1 among Fig. 3, with the read current summation of the redundant storage unit of all storages " 0 " average, draw the read current I0 among Fig. 3, therefore, in this embodiment, the electric current I 1 that obtains and I0 are the mean value of a large amount of redundancy unit, and be distributed on the four edges of array, more can reflect the actual process situation of most of storage unit in the storage array.As from the foregoing, this embodiment not only can adjust the refresh operation frequency according to condition of work (for example working temperature) preferably automatically, also can be according to automatically adjusting the refresh operation frequency according to the formation process conditions of storage unit (forming the data retention characteristics difference to some extent of the different storage unit of fluctuation of process conditions) better.
In addition, redundant storage unit 701,702 to choose also can be the middle part that concentrates on the storage array of monitoring, or in the array that distributes randomly.All are chosen mode and only are the data retention characteristics of most of storage unit in the storage array that reflects required refresh operation better.
Also need to prove in addition, in another preferred embodiment, the storage unit of the storage array of redundant storage unit and required refresh operation can be different, the data retention characteristics of the storage unit of the storage array that the data retention characteristics of redundant storage unit can be monitored relatively is slightly a little bit poorer, thereby redundant storage unit generally is the memory cell data inefficacy prior to the storage array of monitoring, and has therefore as much as possible avoided the storage unit of storage array before data failure, automatically adjust the circuit 700 of memory refresh operation frequency also for sending refresh operation signal.Described " slightly a little bit poorer " refer in this embodiment the data retention characteristics of redundant storage unit can be its storage array of monitoring the memory cell data retention performance 85% to 95%, for example, it can be 90%.But its concrete scope is not limited by the invention process.For example, if the difference data retention time of the storage unit in the storage array is 100ms, the retention performance of two redundant storage units (being written as " 1 " and 0 respectively) can be done slightly nearly, such as about 98ms; Like this, can guarantee substantially before the cell data of storage array lost efficacy that refresh pulse produces circuit 711 can produce the refresh pulse signal.In this embodiment, the data retention characteristics of the storage unit of the relative storage array of monitoring of the data retention characteristics of redundant storage unit " slightly a little bit poorer " can realize by dual mode.First kind of mode is that the manufacturing of redundant storage unit forms the relative difference a little of technology and forms technology in the storage unit manufacturing of the storage array of monitoring, thereby makes the data retention characteristics of redundant storage unit relatively slightly poor.The second way is to realize in the device architecture of the storage unit of the storage array of monitoring by the device architecture difference that makes redundant storage unit; For example, under same fabrication process condition, in the long storage unit of same gate oxide thickness and different grid, the grid length of FBC unit is more short, data hold time is more long, so the grid length of redundant storage unit can be designed to such an extent that slightly be longer than unit in the storage array, the long numerical value of concrete grid can carry out choosing after the emulation according to the desired value of retention time.
Continue to see also Fig. 3, selection for the Iref value, preferably, can select the read current Iread0 of redundant storage unit normal storage " 0 " and redundant storage unit normal storage " 1 " read current Iread1 difference half, namely Iref equals (Iread1-Iread0)/2.
The present invention further provides the method for the automatic adjustment memory refresh operation frequency of circuit shown in Figure 3, mainly may further comprise the steps:
Step S10 when storage array carries out refresh operation, does not store data " 0 " and " 1 " to redundant storage unit 702,701 simultaneously; This storage array is the storage array that comprises that this circuit 700 is monitored; Thereby realized that storage array and redundancy unit begin to store data simultaneously, its data hold time begins to calculate simultaneously.
Step S20 regularly carries out read operation to the redundant storage unit of storage " 0 " and the redundant storage unit of storage " 1 " respectively by timing read/write circuit 706;
Step S30 by difference between current module 707, asks difference between current to the read current of the redundancy unit of depositing " 1 " and the read current of depositing the redundancy unit of " 0 ";
Step S40, by comparer 709, difference between current and reference current Iref that step S30 is drawn compare; If difference between current is greater than reference current Iref, the data storage in the expression redundancy unit was not also lost efficacy, and then repeated to enter step S20; If difference between current is less than or equal to reference current Iref, the data storage in the expression redundancy unit was lost efficacy, and then produced circuit module by refresh pulse and produced the refresh pulse signal, entered step 10.
Need to prove, the above and about automatic adjustment memory refresh operation frequency circuit, the embodiment of method and storer is that example puts forward with the FBC storer, those skilled in the art are according to the announcement of the embodiment of the invention, the FBC storage unit can be replaced to other forms of storage unit, for example, the capacitive character random access memory of 1T1C version, the dynamic RAM of 0/1 state is distinguished by reading voltage in the gain memory unit of 2T structure etc., also the storage unit of distinguishing 0/1 state with read current can be replaced with read the storage unit that voltage is distinguished 0/1 state, the situation of choosing of redundant storage unit is still the same, only need in Fig. 3 specific embodiment, make reference current source into reference voltage source, ask the difference between current circuit to change into and ask the voltage difference circuit, current comparator changes voltage comparator into, and therefore this scheme also is suitable for.
Although the description of this invention is to make in the mode of reference example and preferred embodiment, those skilled in the art arrives cognition, under the prerequisite that does not depart from the scope of the present invention with spirit, can make change in form or details.
Claims (10)
1. a circuit of adjusting the memory refresh operation frequency automatically is characterized in that, comprising:
Store the redundant storage unit of data " 0 " and data " 1 " respectively;
The timing read/write circuit module of redundant storage unit;
The difference between current module is used for the read current of the redundancy unit of the read current of the redundancy unit of storage " 1 " and storage " 0 " is asked difference between current;
Comparison module is used for described difference between current and reference current are compared; And
Refresh pulse produces circuit module, is used for exporting the refresh pulse signal according to the output result of comparison module, in the output result, if difference between current is less than or equal to reference current, then produces circuit module by described refresh pulse and produces the refresh pulse signal.
2. circuit as claimed in claim 1, it is characterized in that, described refresh pulse produces circuit module when output refresh pulse signal, and also output feedback signal is to described timing read/write circuit module, redundant storage unit is write again " 0 " or " 1 " operation.
3. circuit as claimed in claim 1 is characterized in that, described redundant storage unit is more than two, and is arranged at every capable first and last and every row first and last of the storage array of monitoring.
4. circuit as claimed in claim 3, it is characterized in that, storing value in the redundant storage unit alternately is written as " 1 " and " 0 ", the read current of the redundancy unit of described storage " 1 " is the mean value of read current of the redundancy unit of all storages " 1 ", and the read current of the redundancy unit of described storage " 0 " is the mean value of read current of the redundancy unit of all storages " 0 ".
5. circuit as claimed in claim 1 is characterized in that, described redundant storage unit is arranged on the middle part of the storage array of monitoring.
6. circuit as claimed in claim 1 is characterized in that, the data retention characteristics of described redundant storage unit is worse than the data retention characteristics of the storage unit of the storage array of monitoring relatively, and its implementation is:
The manufacturing of described redundant storage unit forms the technology relative different and forms technology in the storage unit manufacturing of the storage array of monitoring, and perhaps the device architecture relative different of described redundant storage unit is in the device architecture of the storage unit of the storage array of monitoring.
7. circuit as claimed in claim 1 is characterized in that, described storer is for distinguishing the storer of " 0 " and one state with the read current form.
8. circuit as claimed in claim 1 is characterized in that, also comprises the reference current source for generation of reference current.
9. a method of adjusting the memory refresh operation frequency automatically is characterized in that, comprises step:
When (1) storage array carries out refresh operation, simultaneously redundant storage unit is stored data " 0 " and " 1 " respectively;
(2) regularly respectively the redundant storage unit of storage " 0 " and the redundant storage unit of storage " 1 " are carried out read operation;
(3) read current of the redundancy unit of depositing " 1 " and the read current of depositing the redundancy unit of " 0 " are asked difference between current;
(4) described difference between current and reference current are compared; If difference between current greater than reference current, then repeats to enter step (2); If difference between current is less than or equal to reference current, then produce circuit module by refresh pulse and produce the refresh pulse signal, enter step (1).
10. storer of automatically adjusting the memory refresh operation frequency, comprise storage array, line decoder, column decoder, sense amplifier, word line driver module, bit-line drive module, Logic control module, it is characterized in that, also comprise the circuit as the arbitrary described automatic adjustment memory refresh operation frequency of claim 1 to 8, the circuit output refresh pulse signal of described automatic adjustment memory refresh operation frequency is to described Logic control module.
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| CN103426465B (en) * | 2013-08-26 | 2016-09-07 | 郑君 | Memory comparing brushes novel circuit module |
| JP6705604B2 (en) | 2016-03-09 | 2020-06-03 | ホアウェイ・テクノロジーズ・カンパニー・リミテッド | Method and apparatus for refreshing a flash memory device |
| TWI695386B (en) | 2018-07-17 | 2020-06-01 | 旺宏電子股份有限公司 | Semiconductor circuit and operating method for the same |
| CN114974343A (en) * | 2021-02-24 | 2022-08-30 | 华邦电子股份有限公司 | Semiconductor memory device with a plurality of memory cells |
| CN115954026B (en) * | 2023-03-10 | 2023-07-28 | 长鑫存储技术有限公司 | Method and device for determining refresh times |
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