KR20140116650A - Dynamic random access memory system and operating method for the same - Google Patents

Dynamic random access memory system and operating method for the same Download PDF

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Publication number
KR20140116650A
KR20140116650A KR1020130031488A KR20130031488A KR20140116650A KR 20140116650 A KR20140116650 A KR 20140116650A KR 1020130031488 A KR1020130031488 A KR 1020130031488A KR 20130031488 A KR20130031488 A KR 20130031488A KR 20140116650 A KR20140116650 A KR 20140116650A
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South Korea
Prior art keywords
refresh
self
command
word line
memory
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KR1020130031488A
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Korean (ko)
Inventor
조용기
신원화
문길신
박철구
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삼성전자주식회사
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Priority to KR1020130031488A priority Critical patent/KR20140116650A/en
Publication of KR20140116650A publication Critical patent/KR20140116650A/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1636—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using refresh
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0625—Power saving in storage systems

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Dram (AREA)

Abstract

A memory system according to an embodiment of the present invention includes a memory device including a memory cell array including a plurality of memory cells; Refresh command from the external device and responsive to the received dip self refresh command to send a deep self refresh entry command to the memory device and the memory self- The memory device adjusts the substrate voltage supplied to the substrate of the memory cell array and the word line voltage supplied to the word line connected to the memory cell array in response to the dip self-refresh entering command, Self-refresh operation.

Description

[0001] DYNAMIC RANDOM ACCESS MEMORY SYSTEM AND OPERATING METHOD FOR THE SAME [0002]

The present invention relates to semiconductor memory devices, and more particularly, to dynamic random access memory devices and methods of operation thereof.

A semiconductor memory device is a memory device implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP) to be. Semiconductor memory devices are classified into a volatile memory device and a nonvolatile memory device.

The volatile memory device is a memory device in which data stored in the volatile memory device is lost when power supply is interrupted. Volatile memory devices include static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM). A nonvolatile memory device is a memory device that retains data that has been stored even when power is turned off. A nonvolatile memory device includes a ROM (Read Only Memory), a PROM (Programmable ROM), an EPROM (Electrically Programmable ROM), an EEPROM (Electrically Erasable and Programmable ROM), a flash memory device, a PRAM ), RRAM (Resistive RAM), and FRAM (Ferroelectric RAM).

2. Description of the Related Art [0002] As semiconductor devices have become smaller in recent years, various technologies for reducing power consumption have been developed. For example, if a particular condition occurs (e.g., idle for a period of time), the user system including the DRAM enters the power down mode to reduce power consumption. At this time, the DRAM device performs a self-refresh operation to save the stored data.

It is an object of the present invention to provide a dynamic random access memory device having a reduced self-refresh current value and a method of operation thereof.

A memory system according to an embodiment of the present invention includes a memory device including a memory cell array including a plurality of memory cells; Wherein the memory controller receives a deep self-refresh command from an external device and, in response to the received deep self-refresh command, sends a deep self-refresh entry command to the memory device Said memory device being responsive to said dip self-refreshing enter command to adjust a substrate voltage supplied to a substrate of said memory cell array and a word line voltage supplied to a word line connected to said memory cell array, Self-refresh operation based on the applied substrate voltage and word line voltage.

In an embodiment, the regulated substrate voltage is lower than the substrate voltage by a predetermined level, and the regulated word line voltage is lower than the word line voltage by a predetermined level.

In an embodiment, the memory device adjusts the refresh period in response to the received deep self-refresh command.

In an embodiment, the memory device repeatedly performs the self-refresh operation based on the adjusted refresh period.

In an embodiment, the memory device comprises: a voltage generator for generating the substrate voltage and the word line voltage; And control logic for receiving the dip self refresh input command and adjusting the substrate voltage, the word line voltage in response to the received dip self refresh input command.

As an embodiment, the dip-self refresh command is a mode register setting command.

In an embodiment, the memory controller receives the deep self-refresh command in a power down mode.

A method of operating a dynamic random access memory device in accordance with another embodiment of the present invention includes receiving a deep self-refresh entry command from an external device; Adjusting a substrate voltage, a word line voltage, and a refresh period in response to the received dip self-refresh enter command; And repeating the self-refresh operation based on the adjusted substrate voltage, the word line voltage, and the refresh period.

As an embodiment, the step of adjusting the substrate voltage, the word line voltage, and the refresh period in response to the received dip self-refresh enter command may comprise: lowering the substrate voltage and the word line voltage by a predetermined level, For a predetermined period of time.

Receiving as an embodiment a dip self-refresh terminate command from the external device; And terminating the self-refresh operation in response to the received dip self-refresh terminate command.

The memory system according to the present invention may adjust the body bias voltage and the self-refresh period in response to the self-refresh command. Therefore, the self-refresh current can be reduced and the power consumption of the semiconductor memory device can be reduced.

1 is a block diagram illustrating a memory system in accordance with an embodiment of the present invention.
FIG. 2 is a block diagram illustrating the memory device shown in FIG. 1; FIG.
3 is a flow chart illustrating the operation of the memory device shown in FIG.
FIG. 4 is a circuit diagram showing one of the plurality of memory cells shown in FIG. 2. FIG.
5 is a timing chart for explaining the operation of the memory device shown in Fig.
FIG. 6 is a block diagram illustrating an example of a user system to which the memory device according to the present invention is applied.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the technical idea of the present invention. .

The memory system according to the present invention controls the substrate voltage, the word line voltage, and the refresh period in response to the deep self-refresh command in the power down mode. Thus, the refresh current is reduced in the self-refresh operation of the memory system. For the sake of brevity, it is assumed below that the memory device included in the memory system is a DRAM device. However, the scope of the present invention is not limited thereto, and the memory device according to the present invention may include a random access memory such as a DRAM, an SDRAM, a DDR SDRAM, a DDR2 SDRAM, a DDR3 SDRAM, a GDDR5 SDRAM, and an LPDDR SDRAM.

1 is a block diagram illustrating a memory system in accordance with an embodiment of the present invention. Referring to FIG. 1, a memory system 100 includes a memory controller 110 and a memory device 120. The memory controller 110 may control the memory device 120. For example, the memory controller 110 receives a command CMD, an address ADDR, and data DATA from an external device (e.g., a host) and outputs the received command CMD, address ADDR, , And data (DATA). The memory controller 110 generates a data clock WCK and a command clock CK used in the memory device 120 and transmits the generated data clock WCK and command clock CK to the memory device 120 .

Illustratively, when memory system 100 enters a power down mode, memory controller 110 may receive a deep self-refresh command (DSR) from an external device. Memory controller 110 may send the deep self-refresh entry / exit commands DSRE, DSRX to the memory device in response to the received deep self-refresh command DSR. Illustratively, the deep self-refresh command (DSR) may be a mode register setting command (MRS command).

The memory device 120 stores the data DATA on the basis of the command CMD, the address ADDR, the data DATA, the data clock WCK, and the command clock CK received from the memory controller 110 Or output the stored data (DATA).

Illustratively, the memory device 120 may receive the deep self-refresh entry / exit commands DSRE, DSRX from the memory controller 110. The memory device 120 may adjust the substrate voltage, the word line voltage, and the refresh period in response to the received deep self-refresh enter command DSRE. For example, the memory device 120 may adjust the substrate voltage and the word line voltage to be lower by a predetermined level in response to the received refresh entry command DSRE.

The memory device 120 may increase the refresh period in response to the received deep self-refresh enter command DSRE. In other words, the memory device 120 may increase the self-refresh operation interval. As the self-refresh operation interval increases, the self-refresh current consumed in the memory device 120 is reduced.

Illustratively, after the memory device 120 receives the deep self-refresh enter command DSRE, the memory system 100 maintains the adjusted substrate voltage, word line voltage, and refresh cycle until the memory system 100 operates in the normal mode . Or the memory device 120 may maintain the adjusted substrate voltage, word line voltage, and refresh period before receiving the dip self-refresh termination command DSRX.

2 is a block diagram illustrating the memory device 120 shown in FIG. 1 in greater detail. 2, memory device 120 includes control logic 121, a voltage generator 122, a memory cell array 123, a row decoder 124, a column decoder 125, a sense amplifier and a write driver 126 ), And an input / output buffer 127.

The control logic 121 receives the command CMD, the address ADDR, the data clock WCK and the command clock CK from the memory controller 110 (see Fig. 1) The device 120 can be controlled.

The voltage generator 122 may generate the word line voltage VWL and the substrate voltage VBB. Illustratively, the voltage generator 122 may adjust the substrate voltage VBB and the word line voltage Vwl under the control of the control logic 120. [

The memory cell array 123 includes a plurality of memory cells MC. Each of the plurality of memory cells may comprise a transistor and a capacitor. Each of the plurality of memory cells may be located at a point where a plurality of word lines WL and a plurality of bit lines BL intersect each other. A plurality of memory cells MC may be provided in a matrix form. The plurality of word lines may be connected to the rows of memory cells of the memory cell array 123. The plurality of bit lines are connected to the columns of memory cells of the memory cell array 123.

The row decoder 124 may select some of the plurality of word lines coupled to the memory cell array 123. [ For example, the row decoder 123 may receive the word line voltage Vwl from the voltage generator 122. The row decoder 123 may select some of the plurality of word lines WL under the control of the control logic 121 and apply the received word line voltage Vwl to selected selected word lines.

The column decoder 125 may select some of the plurality of bit lines connected to the memory cell array 123. For example, the column decoder 123 may select some of the plurality of bit lines under the control of the control logic 121. [

The sense amplifier and write driver 126 are coupled to a plurality of bit lines coupled to the memory cell array 123. The sense amplifier and write driver 126 detects the voltage change of the activated bit line among the plurality of bit lines, amplifies and outputs the detected voltage change. The sense amplifier and write driver 126 may control the voltage of the plurality of bit lines such that the plurality of memory cells has either data 0 or data 1 data state.

The input / output buffer 127 can output data based on the amplified voltage from the sense amplifier and the write driver 126.

The operation of the memory device 120 according to an embodiment of the present invention will now be described with reference to FIGS. 1 and 2. FIG. The memory controller 110 may send the deep self-refresh entry / exit commands DSRE, DSRX to the memory device 120. [

The memory device 120 may adjust the substrate voltage VBB, the word line voltage Vwl, and the self-refresh period tREF in response to the received deep self-refresh enter command DSRE. For example, the control logic 121 controls the voltage generator 122 such that the substrate voltage VBB and the word line voltage Vwl are lowered by a predetermined level in response to the dip self-refresh enter command DSRE . The adjusted substrate voltage VBB ' may be supplied to the substrate of the memory cell array 123. [ In this case, the threshold voltage of the plurality of memory cells included in the memory cell array 123 will be lowered by the body bias effect. Therefore, the word line voltage Vw1 supplied to the word line can be lowered, so that the refresh current consumed in the refresh operation of the memory device 120 will decrease.

The control logic 121 may also include an oscillator 121a that determines the refresh period tREF of the memory device 120. [ The control logic 110 may control the oscillator 121a to increase the refresh period tREF in response to the received deep self-refresh enter command DRSE. By the increased refresh period tREF, the overall refresh current of the memory device 120 will be reduced.

The memory controller 110 sends a deep self-refresh ingress / egress command to the memory device 120 and the memory device 120 receives the received deep self-refresh enter command DSRE , The word line voltage Vwl, and the refresh period tREF in response to the word line voltage VBB, the word line voltage Vwl, and the refresh period tREF. Thus, since the refresh current is entirely reduced, a memory system having reduced power consumption is provided.

3 is a flow chart illustrating the operation of the memory system shown in FIG. Referring to Figs. 1 to 3, in step S110, the memory controller 110 may receive a deep self-refresh command (DSR) from an external device. Illustratively, the memory system 1

In step S120, the memory controller 110 may transmit the deep self-refresh enter command DSRE to the memory device 120. [

In step S130, the memory device 120 may adjust the substrate voltage VBB, the word line voltage Vwl, and the refresh period tREF in response to the received deep self-refresh enter command DSRE. For example, the memory device 120 may lower the substrate voltage VBB and the word line voltage Vwl by a predetermined level in response to the deep self-refresh enter command DSRE. The memory device 120 may increase the refresh period tREF in response to the dip self-refresh enter command DSRE.

In step S140, the memory device 120 performs a self-refresh operation based on the adjusted substrate voltage VBB`, the adjusted word line voltage Vwl`, and the refresh period tREF`. For example, the memory device 120 may perform a refresh operation that reads and stores data stored in the memory device based on the adjusted substrate voltage VBB ' and the adjusted word line voltage Vwl. The memory device 120 may repeatedly perform the self-refresh operation based on the adjusted refresh period tREF.

In step S150, the memory controller 110 can transmit a deep self-refresh end command DSRX. Illustratively, the memory controller 110 may send a dip self refresh termination command (DSRX) to the memory device 120 when the memory system 100 is about to enter normal mode or when performing wakeup training.

In step S160, the memory device 120 terminates the self-refresh operation in response to the received dip self-refresh end command DSRX. Illustratively, the memory device 120 responds to the received dip self-refresh terminate command DSRX by adjusting the adjusted substrate voltage VBB ', the word line voltage Vwl ', and the refresh period tREF & It is possible to restore the state before the adjustment in step S130.

According to the embodiment of the invention described above, the memory system 100 adjusts the substrate voltage VBB, the word line voltage Vwl, and the refresh period tREF in response to the deep self-refresh command DSR . Thus, a memory system with reduced power consumption is provided.

FIG. 4 is a circuit diagram showing one of the plurality of memory cells shown in FIG. 2. FIG. Referring to Figs. 2 and 4, the memory cell MC includes a transistor TR and a capacitor C. When the word line voltage Vw1 is applied higher than the threshold voltage of the transistor TR, the transistor TR will be turned on and the charge charged in the capacitor C will be discharged. At this time, the discharged electric charges will flow through the bit line BL.

Exemplarily, when the control logic 121 receives the dip self-refresh enter command DSRE, the control logic 121 sets the voltage VBB and the word line voltage Vwl lower by a predetermined level, The generator 122 can be controlled. That is, as the substrate voltage VBB is lowered by a predetermined level, the threshold voltage of the transistor TR will be lowered. Thus, the refresh current consumed during the refresh operation of the memory device 120 can be reduced.

5 is a timing diagram showing the operation of the memory device shown in Fig. Illustratively, the timing diagram shown in Figure 5 is a timing diagram showing signals after memory system 100 enters a power down mode. Referring to Figures 1 and 5, memory controller 110 may send clock signals (CK, CK /), and dip self-refresh enter / exit commands (DSRE, DSRX) to memory device 120. At this time, the memory controller 110 does not transmit and receive the address ADDR and the data DATA.

First, the memory controller 110 sends a deep self-refresh enter command DSRE to the memory device 120. The memory device 120 may adjust the substrate voltage VBB, the word line voltage Vwl, and the refresh period tREF in response to the deep self-refresh entry command DSRE at a first time point tl. Illustratively, the memory device 120 receives the substrate voltage VBB, the word line voltage Vwl, and the refresh period < RTI ID = 0.0 > tREF < / RTI >

Thereafter, the memory device 120 may repeatedly perform the self-refresh operation until the second time point t2 when the dip self-refresh end command DSRX is received. At this time, the memory device 120 may repeatedly perform the self-refresh operation based on the adjusted substrate voltage VBB ', the word line voltage Vwl', and the refresh period tREF '.

FIG. 6 is a block diagram illustrating an example of a user system to which the memory device according to the present invention is applied. 6, the user system 1000 may be a computer, an Ultra Mobile PC (UMPC), a workstation, a netbook, a PDA (Personal Digital Assistant), a portable computer, a web tablet, , A wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game machine, a navigation device, a black box a digital camera, a digital camera, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a digital audio recorder, a digital audio player, a digital picture recorder, a digital video player, a digital video player, a digital video player, and the like.

The user system 1000 includes a central processing unit 1100, a main storage unit 1200, an auxiliary storage unit 1300, and an input / output interface 1400 and a system bus.

The central processing unit 1100 is a device that controls the operation of the devices included in the user system 1000 and decrypts or executes the program name.

The main storage device 1200 is a device for temporarily storing a program or data to be executed by the central processing unit 1100 in order to buffer the operation speed between the central processing unit 1100 and the auxiliary storage unit 1300. [ For example, the main memory 1200 may be a DRAM (Dynamic Random Access Memory), an SDRAM (Synchronous DRAM), an SRAM (Static RAM), a DDR SDRAM, a DDR2 SDRAM, a DDR3 SDRAM, a GDDR5 SDRAM, , A PRAM (Phase-change RAM), a MRAM (Magnetic RAM), a RRAM (Resistive RAM), or the like. By way of example, main memory 1200 may include the memory system described with reference to Figures 1-5.

The auxiliary storage device 1300 is a device for storing a program or data. Illustratively, the auxiliary storage device 1300 may be provided as a mass storage device such as a hard disk drive, a solid state drive, or the like.

The user interface 1400 is an interface that provides an input / output operation so that a user can control the user system 1000.

The system bus 1500 is connected to the central processing unit 1100, the main storage unit 1200, the auxiliary storage unit 1300 and the user interface 1400 to provide a channel for transmitting data.

The memory system according to the embodiment of the present invention described above can adjust the refresh period tREF, the substrate voltage VBB, and the word line voltage Vwl in response to the deep self-refresh command DSR. Thus, a memory system with reduced power consumption is provided.

Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the claims equivalent to the claims of the present invention as well as the following claims.

100: Memory system
110: Memory controller
120: memory device
DSR: Deep Self-Refresh command
DSRE: Deep Self-Refresh Entry Command
DSRX: Deep Self-Refresh Terminate Command
tREF: Refresh cycle

Claims (10)

A memory device including a memory cell array including a plurality of memory cells;
And a memory controller for controlling the memory device,
Wherein the memory controller receives a deep self-refresh command from an external device and, in response to the received deep self-refresh command, sends a deep self-refresh enter command to the memory device,
Wherein the memory device adjusts a substrate voltage supplied to a substrate of the memory cell array and a word line voltage supplied to a word line coupled to the memory cell array in response to the dip self- A memory system that performs a self-refresh operation based on a word line voltage. The method according to claim 1,
Wherein the regulated substrate voltage is lower than the substrate voltage by a predetermined level and the regulated word line voltage is lower than the word line voltage by a predetermined level. The method according to claim 1,
Wherein the memory device adjusts the refresh period in response to the received deep self-refresh command. The method of claim 3,
Wherein the memory device repeatedly performs the self-refresh operation based on the adjusted refresh period. 5. The method of claim 4,
The memory device
A voltage generator for generating the substrate voltage and the word line voltage; And
And control logic to receive the dip self refresh input command and adjust the substrate voltage, the word line voltage in response to the received dip self refresh input command. The method according to claim 1,
Wherein the dip-self refresh command is a mode register setting command. The method according to claim 1,
Wherein the memory controller receives the deep self-refresh command in a power down mode. A method of operating a dynamic random access memory device,
Receiving a deep self-refresh entering command from an external device;
Adjusting a substrate voltage, a word line voltage, and a refresh period in response to the received dip self-refresh enter command; And
Repeating the self-refresh operation based on the adjusted substrate voltage, the word line voltage, and the refresh period. The method according to claim 1,
In response to the received dip self-refresh enter command, adjusting the substrate voltage, word line voltage, and refresh period comprises:
The substrate voltage and the word line voltage are lowered by a predetermined level, and the refresh period is increased by a predetermined time. The method according to claim 1,
Receiving a dip self-refresh terminate command from the external device; And
And terminating the self-refresh operation in response to the received dip self-refresh terminate command.
KR1020130031488A 2013-03-25 2013-03-25 Dynamic random access memory system and operating method for the same KR20140116650A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11264076B2 (en) 2019-01-02 2022-03-01 SK Hynix Inc. Power control circuit, semiconductor apparatus including the same and power control method of semiconductor apparatus
US11615832B2 (en) 2020-12-01 2023-03-28 SK Hynix Inc. Electronic devices executing a refresh operation based on temperature
US11894041B2 (en) 2020-12-01 2024-02-06 SK Hynix Inc. Electronic devices executing refresh operation based on adjusted internal voltage

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11264076B2 (en) 2019-01-02 2022-03-01 SK Hynix Inc. Power control circuit, semiconductor apparatus including the same and power control method of semiconductor apparatus
US11615832B2 (en) 2020-12-01 2023-03-28 SK Hynix Inc. Electronic devices executing a refresh operation based on temperature
US11894041B2 (en) 2020-12-01 2024-02-06 SK Hynix Inc. Electronic devices executing refresh operation based on adjusted internal voltage

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