WO2016041408A1

WO2016041408A1 - Otp or mtp memory module with dual-cell structure

Info

Publication number: WO2016041408A1
Application number: PCT/CN2015/084194
Authority: WO
Inventors: 方钢锋
Original assignee: 苏州锋驰微电子有限公司
Priority date: 2014-09-19
Filing date: 2015-07-16
Publication date: 2016-03-24
Also published as: CN104269188A

Abstract

An OTP (One-Time Programmable) or MTP (Multi-Time Programmable) memory module with a dual-cell structure comprises a memory array, a data selector, a sense amplifier and a controller; two adjacent memory cells form one group in the memory array during operation in a dual-cell mode, and the two memory cells are referred to as a first cell and a second cell respectively, and the first cell and the second cell constitute a differential dual-cell structure; when the first cell is "1" and the second cell is "0", the output passing through the sense amplifier is "1", and when the first cell is "0" and the second cell is "1", the output passing through the sense amplifier is "0", that is, the final output of the dual-cell structure is one bit. The reliability of the OTP or MTP memory module is improved during operation in a differential dual-cell mode, and meanwhile, applications under different situations are combined together to flexibly meet the demands and also achieve the highest cost performance.

Description

OTP or MTP memory module with dual unit structure

Technical field

The present invention relates to an OTP (One Time Programmable) or MTP (Multiple Programmable) memory module, and more particularly to an OTP or MTP memory module having a dual cell structure operation mode.

Background technique

Non-volatile memory compatible with CMOS logic processes Due to the process used in non-traditional dedicated non-volatile memory processes, data retention or reliability requirements are often not met and some methods are needed to compensate. Different applications have different reliability requirements and cost requirements. The reliability of the OTP/MTP memory module in single-unit operation mode is lower, but the area is not wasted and the relative cost is low. If two-unit work is used to improve reliability, the area is doubled and the cost is increased accordingly. If you can combine applications in different situations, you can better meet the needs of your application.

Summary of the invention

The object of the present invention is to overcome the deficiencies in the prior art and to provide an OTP or MTP storage module that can operate in a differential dual unit mode, and can have a single working mode or can switch between two modes.

According to the technical solution provided by the present invention, an OTP or MTP memory module having two working modes includes a memory array, a data selector, a sense amplifier and a controller, and the output of the memory array is sequentially connected to the data selector and the sense amplifier. The controller is respectively connected to the memory array, the data selector, and the sense amplifier; in the dual-cell mode, in the memory array, two adjacent storage units are a group, which are respectively referred to as a first unit and a second unit. Forming a differential two-cell structure. When the first cell is "1" and the second cell is "0", the output through the sense amplifier is "1", and when the first cell is "0", the second cell When it is "1", the output through the sense amplifier is "0", that is, the two-element structure is finally output as one bit; in the single-cell mode, the output of each memory cell is read in the memory array. Compared with the reference signal in the output amplifier, the output is “0” smaller than the reference signal, and “1” is output when the reference signal is larger than the reference signal.

When only data reliability is considered, it can be made into a single unit only.

The invention has the advantages of working in the differential dual unit mode, improving the reliability of the OTP or MTP storage module, and simultaneously combining the applications of different occasions, flexibly adapting the requirements, and achieving the highest cost performance.

DRAWINGS

Figure 1 is the signal margin of a single unit mode of operation.

Figure 2 is the signal boundary of the differential dual unit mode of operation.

Figure 3 is two bits of a differential dual unit structure, each bit containing two units.

Figure 4 is the output of two bits of a differential dual unit structure.

Figure 5 is a schematic diagram of the structure of an OTP memory cell.

Figure 6 is a combination of two OTP memory cells in a dual cell.

Figure 7 is a 2 x 2 array of the two cells shown in Figure 6, with an output of 4 bits.

Figure 8 is a diagram showing Figure 7 as a 2 x 4 cell array in a single cell mode of operation with 8 bits output.

FIG. 9 is a schematic structural diagram of the entire OTP storage module.

detailed description

The invention will now be further described with reference to the accompanying drawings and embodiments.

As shown in FIG. 3, there are two bits (bit<1:0>) in the memory array of the present invention, each bit containing two OTP/MTP memory cells. Cell3 and cell2 are a group, and cell1 and cell0 are a group.

As shown in FIG. 4, cell3 and cell2 form a differential dual-cell structure. When cell3 is "1" and cell2 is "0", the output bit <1> of the SA (sense amplifier) is " 1". Cell1 and cell0 form a differential dual-cell structure. When cell1 is "0" and cell0 is "1", the output bit<0> of the SA is "0", that is, each bi-cell structure is finally output as one bit.

Figure 1 shows the signal boundary of a single-cell operation. The Program signal is the programming signal, the Erase signal is the erase signal, and the reference is the reference signal. If an OTP or MTP memory cell is a program unit ("1"), another OTP or MTP memory cell is an erase unit ("0"). This doubles the signal, as shown in Figure 2. There is also the elimination of the uncertainty of the reference signal. The signal is larger, as long as the program unit and the erase unit are slightly different, it can be distinguished as "1" or "0", and the reliability of the data is higher. But this also doubles the number of cells for an OTP or MTP memory array of the same capacity. Therefore, we can design two working modes for the same memory array, so that it can work in a single unit when large capacity is required. That is, the output of each memory cell is compared with a reference signal in the sense amplifier, and "0" is output when the reference signal is smaller than the reference signal, and "1" is output when the reference signal is larger than the reference signal. The capacity is doubled accordingly. Such an OTP or MTP memory module can operate as two OTP/MTP memory modules of different capacities, one is a differential two-cell structure, and can also be a single-cell structure with twice the capacity.

The following is an example of a simple OTP memory module structure.

Figure 5 shows an OTP memory cell, including two PMOS transistors. In the figure, PL is the Program line, WL is the Word line, and BL is the Bit line. (Bit line), the substrates of the two PMOS transistors are connected together by NWell (N well). The unit structure is only an illustration, and the present invention is applicable to an OTP or MTP memory composed of memory cells of various physical structures.

In Figure 6, two OTP memory cells form a differential structure, one is Program and the other is Erase.

2 × 2 structure of Figure 6 constitutes Figure 7, combined with the overall structure of Figure 9: through the selection of WL (1), the upper left BL (1) and BLb (1) through the SA comparison output one bit of data, the upper right BL ( 0) and BLb(0) output a bit of data through SA comparison; after WL(0) selection, BL(1) and BLb(1) in the lower left are compared by SA to output one bit of data, upper right BL(0) and BLb ( 0) Output one bit of data by SA comparison. A total of 4 digits of data.

If the structure of FIG. 7 is a single unit operation, as an array of 2×4 cells, as shown in FIG. 8, the overall structure of FIG. 9 can be seen: after the selection of WL(1), the upper four cells are compared by SA and reference signals. Output BL(3), BL(2), BL(1), BL(0) respectively; after WL(0) selection, the lower 4 units are compared by SA and reference signals, respectively output BL(3), BL( 2), BL(1), BL(0). A total of 8 digits of data.

9 is a schematic structural diagram of an entire OTP memory module, including a memory array, a data selector BL MUX, a sense amplifier SA, and a controller. The output of the memory array is sequentially connected to a data selector and a sense amplifier, and the controller and the memory array are respectively A data selector and a sense amplifier are connected to provide a control signal. The BL MUX (Bit line MUX) selects the unit signals on different bit lines to enter the SA.

Claims

A dual-cell OTP or MTP memory module includes a memory array, a data selector, a sense amplifier, and a controller. The output of the memory array is sequentially connected to a data selector and a sense amplifier, respectively, and the memory array and data selection And the sense amplifiers are connected, wherein: in the memory array, two adjacent storage units are a group, which are respectively referred to as a first unit and a second unit, and constitute a differential dual unit structure, when the first unit When it is "1" and the second cell is "0", the output through the sense amplifier is "1". When the first cell is "0" and the second cell is "1", the output through the sense amplifier is “0”, that is, the dual unit structure is finally output as one bit.
An OTP or MTP memory module having two modes of operation, including a memory array, a data selector, a sense amplifier, and a controller, wherein the output of the memory array is sequentially connected to the data selector and the sense amplifier, and the controller and the memory array, respectively The data selector and the sense amplifier are connected, and are characterized in that: when operating in the dual unit mode, two adjacent storage units in the memory array are a group, which are respectively referred to as a first unit and a second unit, and constitute a differential. The dual cell structure, when the first cell is "1" and the second cell is "0", the output through the sense amplifier is "1", when the first cell is "0" and the second cell is "1" When the output of the sense amplifier is "0", that is, the final output of the dual unit structure is one bit;
In the single cell mode, in the memory array, the output of each memory cell is compared with the reference signal in the sense amplifier, and "0" is output when the reference signal is smaller than the reference signal, and "1" is output when the reference signal is larger than the reference signal.