CN104299648B - A kind of differential architecture read-only memory unit - Google Patents
A kind of differential architecture read-only memory unit Download PDFInfo
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- CN104299648B CN104299648B CN201410495362.2A CN201410495362A CN104299648B CN 104299648 B CN104299648 B CN 104299648B CN 201410495362 A CN201410495362 A CN 201410495362A CN 104299648 B CN104299648 B CN 104299648B
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- branch road
- mos field
- bit line
- effect transistors
- differential pair
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Abstract
The present invention is a kind of differential architecture read-only memory unit, each unit includes four bit line branch roads BL1, BL1B, BL2 and BL2B, an and wordline WL, differential pair is formed between the branch road BL1 and branch road BL1B, differential pair is formed between the branch road BL2 and branch road BL2B, two MOS field-effect transistors are shared between each differential pair.Using technical solution of the present invention, differential architecture ROM cell expands differentiable current range during device read operation to a certain extent, when reading simultaneously input difference amplifier is contrasted using two branch roads, the mismatch problem brought using reference circuit can be avoided, the stability of reading is drastically increased, there is wide market application foreground.
Description
Technical field
The present invention relates to a kind of semiconductor storage unit, and in particular to a kind of improved read-only storage of differential architecture（ROM）
Unit.
Background technology
With developing rapidly for microelectric technique and computer technology, we are just marching toward an information-intensive society.Information-intensive society
It is unable to do without the storage of information.Since nearly half a century, people constantly explore storage new technology, form various in style deposit
Reservoir family.Existing memory species is a lot, in terms of access facility, they can be divided into read-only（Read Only
Memory, ROM）Memory and random（Random Access Memory, RAM）The major class of memory two.
ROM memory therein in the operating condition, can only therefrom read data, and data will not disappear after power-off, belong to
In semiconductor non-volatile memory (Non-Volatile Semiconductor Memory) category.
Traditional ROM memory is formed with one and multiple NMOS tubes, and is used as elementary cell using a NMOS tube.Tradition
ROM bit cell as shown in figure 1, its source ground（GND）, drain and connect or be not connected to bit line（Bit Line, BL）,
And grid is connected to wordline（Word Line, WL）.Traditional data " 0 " are compiled by the way that NMOS drain electrode is connected into bit line to realize
Journey, traditional data " 1 " realize programming by the way that NMOS drain electrode is not connected into bit line.
In general, it is such programming be using formed ROM cell nmos pass transistor front end layer realize, so as to
ROM cell is integrated in ROM device more to high-density.Generally utilize through hole（Contact）Mask plate programs or active area
（Diffusion）Mask plate is programmed to.
With the continuous development of integrated circuit technology in recent years, process rule, the area of ROM basic units of storage are limited to
Process scaled down can not be accomplished to follow, unit storage unit area is larger.With the progress of technique, ROM reading is grasped
Also face the challenge, differentiable current range is also less and less during read operation, and the limitation of current range seriously limits reference
The impedance selection of circuit, it is easy to bring impedance mismatch problem, cause read error.
In view of this, it is necessary to propose a kind of improved differential architecture ROM bit cell structure to optimize these problems.
The content of the invention
To overcome deficiency of the prior art, the present invention provides a kind of differential architecture read-only memory unit, deposited in traditional ROM
On the basis of storage unit, input difference amplifiers are contrasted using two branch roads during reading, avoid what is brought using reference circuit
Mismatch problem, drastically increase the stability of reading.
To realize above-mentioned technical purpose and the technique effect, the present invention is achieved through the following technical solutions：
A kind of differential architecture read-only memory unit, it is characterised in that each unit include four bit line branch road BL1, BL1B,
BL2 and BL2B, and a wordline WL, form differential pair, the branch road BL2 and branch between the branch road BL1 and branch road BL1B
Differential pair is formed between the BL2B of road, two MOS field-effect transistors are shared between each differential pair；
The MOS field-effect transistors include grid, source electrode and drain electrode, two
The grid of MOS field-effect transistors connects wordline WL, source ground jointly；
The differential pair being made up of branch road BL1 and branch road BL1B, the drain electrode connection branch road of one of MOS field-effect transistors
BL1, the drain electrode connection branch road BL1B of another MOS field-effect transistor；
The differential pair being made up of branch road BL2 and branch road BL2B, the drain electrode connection branch road of one of MOS field-effect transistors
BL2, the drain electrode connection branch road BL2B of another MOS field-effect transistor.
Further, in the differential pair that the branch road BL1 and branch road BL1B are formed, the leakage of a MOS field-effect transistor
Pole is connection status with bit line branch road, and the drain electrode of another MOS field-effect transistor and bit line branch road are not-connected status.
Further, in the differential pair that the branch road BL2 and branch road BL2B are formed, the leakage of a MOS field-effect transistor
Pole is connection status with bit line branch road, and the drain electrode of another MOS field-effect transistor and bit line branch road are not-connected status.
Further, the MOS field-effect transistors include the 1st and below the gate medium and gate medium of grid, grid
2nd doped semiconductor area, the 1st and the 2nd doped semiconductor area are imitated respectively as the source electrode of metal-oxide-semiconductor and the MOS fields that drain
Answering transistor has an a conductive structure i.e. grid of MOS field-effect transistors, one layer of ultra-thin medium below conductive structure, conductive
The 1st doped semiconductor area below structure, the 1st and the 2nd doped semiconductor area of the MOS field-effect transistors spatially every
Open and channel region is determined therebetween, the wordline of the grids of the MOS field-effect transistors as integral device, the MOS
Bit line of the drain electrode of field-effect transistor as integral device.
The beneficial effects of the invention are as follows:
1st, the present invention use differential architecture, and two branch roads are as differential pair input sense amplifier, thus during read operation
Current range, which can be distinguished, can reach maximum.Meanwhile since two branch roads store " 0 " and " 1 " respectively, thus meeting read operation
It on the premise of speed and accuracy, can moderately reduce the size of memory cell MOS elements, so can be very good to optimize
ROM storage array area for cutting.
2nd, the present invention uses symmetric difference framework, and the impedance matching of memory cell branch road is more preferable, and stability is higher.For existing
For some memory cell, one reference circuit of generally use is input to spirit together as reference arm, and bit line BL during reading
In quick amplifier.The impedance of this branch road have to be between BL ends equiva lent impedance and memory cell when memory cell deposits 0 deposit it is equivalent when 1
Among impedance, the necessary careful design of reference arm here, not so it is easy to cause mistake, and for difference proposed by the present invention
Structure, two bit line branch roads are all identical structures, impedance value also certainly when depositing 0 equiva lent impedance and when depositing 1 equiva lent impedance it
Between change, thus without worrying resistance matching problem, the stability of memory cell can also be protected.
Brief description of the drawings
Accompanying drawing described herein is used for providing a further understanding of the present invention, forms the part of the application, this hair
Bright schematic description and description is used to explain the present invention, does not form inappropriate limitation of the present invention.In the accompanying drawings：
Fig. 1 is traditional ROM bit cell structural representation；
Fig. 2 is ROM bit cell structural representation of the present invention.
Embodiment
Below with reference to the accompanying drawings and in conjunction with the embodiments, the present invention is described in detail.
Shown in reference picture 2, a kind of differential architecture read-only memory unit, wherein, each unit includes four bit line branch roads
BL1, BL1B, BL2 and BL2B, and a wordline WL, differential pair, the branch are formed between the branch road BL1 and branch road BL1B
Differential pair is formed between road BL2 and branch road BL2B, two MOS field-effect transistors, the present embodiment are shared between each differential pair
In two MOS field-effect transistors be respectively M1 pipe and M2 pipe；
M1 is managed and M2 pipes all include grid, source electrode and drain electrode, and the grid of M1 pipes and M2 pipes connects wordline WL jointly, and source electrode is all
Ground connection.
In the differential pair that branch road BL1 and branch road BL1B is formed, the wherein drain electrode of M2 pipes is not connected with bit line branch road BL1,
The drain electrode of M1 pipes is connected with bit line branch road BL1B, in the present embodiment, can be realized with metal level or through hole and be allowed both（Drain electrode
With bit line）Connect, can also realize and be not connected to, similar to switch, selection is any, according to depending on concrete technology.
In the differential pair that branch road BL2 and branch road BL2B is formed, the wherein drain electrode of M2 pipes is not connected with bit line branch road BL2,
The drain electrode of M1 pipes is connected with bit line branch road BL2B, in the present embodiment, can be realized with metal level or through hole and be allowed both（Drain electrode
With bit line）Connect, can also realize and be not connected to, similar to switch, selection is any, according to depending on concrete technology.
The MOS field-effect transistors include the 1st and the 2nd doping half below the gate medium and gate medium of grid, grid
Conductor region, the 1st and the 2nd doped semiconductor area have respectively as the source electrode of metal-oxide-semiconductor and the MOS field-effect transistors that drain
One conductive structure is the grid of MOS field-effect transistors, one layer of ultra-thin medium below conductive structure, below conductive structure
1st doped semiconductor area, the 1st and the 2nd doped semiconductor area of the MOS field-effect transistors are spatially separated and wherein
Between be determined channel region, the wordline of the grids of the MOS field-effect transistors as integral device, the MOS field effect transistors
Bit line of the drain electrode of pipe as integral device.
The principle of the present invention：
Continuing with shown in Fig. 2, when bit line chooses BL1 and BL1B differential pairs, two bit lines BL1 and BL1B pass through preliminary filling
Circuit charges to high level, and M1 pipes and M2 pipes are all standard MOS field-effect transistors, is connected when M1 pipes with the grid of M2 pipes
Wordline WL is opened, and the drain electrode of M2 pipes is not attached to BL1, it is impossible to discharge operation is carried out to bit line BL1, i.e. bit line BL1 keeps original
Level, M1 pipes, which are opened, carries out discharge operation to BL1B, and BL1B level is reduced, and certain electricity at this moment can be produced between BL1 and BL1B
Pressure difference, we define this state to have deposited data " 1 ", i.e. One_cell, at this moment by BL1 and BL1B in read only memory ROM
In input difference sensitive amplifier circuit, it is possible to fast and effectively read data.
Similarly, when bit line chooses BL2 and BL2B differential pairs, two bit lines BL2 and BL2B are charged by pre-charge circuit
To high level, M1 pipes and M2 pipes are all standard MOS field-effect transistors, when the wordline WL that M1 pipes connect with the grid of M2 pipes is beaten
Open, the drain electrode of M2 pipes is not attached to BL2B, it is impossible to discharge operation is carried out to bit line BL2B, i.e. bit line BL2B keeps original level,
M1 pipes, which are opened, carries out discharge operation to BL2, and BL2 level is reduced, and certain voltage difference at this moment can be produced between BL2 and BL2B, I
Define this state to have deposited data " 0 " in read only memory ROM, i.e. Zero_cell is at this moment poor by BL2 and BL2B inputs
Divide in sensitive amplifier circuit, it is possible to fast and effectively read data.
The preferred embodiments of the present invention are the foregoing is only, are not intended to limit the invention, for the skill of this area
For art personnel, the present invention can have various modifications and variations.Within the spirit and principles of the invention, that is made any repaiies
Change, equivalent substitution, improvement etc., should be included in the scope of the protection.
Claims (2)
- A kind of 1. differential architecture read-only memory unit, it is characterised in that each unit include four bit line branch road BL1, BL1B, BL2 and BL2B, and a wordline WL, form differential pair, the branch road BL2 and branch between the branch road BL1 and branch road BL1B Differential pair is formed between the BL2B of road, two MOS field-effect transistors are shared between each differential pair；The MOS field-effect transistors include grid, source electrode and drain electrode,The grid of two MOS field-effect transistors connects wordline WL, source ground jointly；In the differential pair that the branch road BL1 and branch road BL1B are formed, drain electrode and the bit line branch road of a MOS field-effect transistor are Connection status, the drain electrode of another MOS field-effect transistor and bit line branch road are not-connected status；In the differential pair that the branch road BL2 and branch road BL2B are formed, drain electrode and the bit line branch road of a MOS field-effect transistor are Connection status, the drain electrode of another MOS field-effect transistor and bit line branch road are not-connected status.
- 2. differential architecture read-only memory unit according to claim 1, it is characterised in that the MOS field-effect transistors Including grid, grid gate medium and gate medium below the 1st and the 2nd doped semiconductor area, it is described 1st and the 2nd doping partly lead There are a conductive structure i.e. MOS field effect transistors in body area respectively as the source electrode of metal-oxide-semiconductor and the MOS field-effect transistors that drain The grid of pipe, one layer of ultra-thin medium below conductive structure, the 1st doped semiconductor area below conductive structure, the MOS fields effect Answer the 1st and the 2nd doped semiconductor area of transistor spatially separated and channel region is determined therebetween, the MOS fields effect The grid of transistor is answered as the wordline of integral device, the bit line to drain as integral device of the MOS field-effect transistors.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410495362.2A CN104299648B (en) | 2014-09-25 | 2014-09-25 | A kind of differential architecture read-only memory unit |
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| CN201410495362.2A CN104299648B (en) | 2014-09-25 | 2014-09-25 | A kind of differential architecture read-only memory unit |
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| CN104299648A CN104299648A (en) | 2015-01-21 |
| CN104299648B true CN104299648B (en) | 2017-12-26 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1726562A (en) * | 2002-12-19 | 2006-01-25 | 恩艾斯克株式会社 | CMIS semiconductor nonvolatile storage circuit |
| CN204178726U (en) * | 2014-09-25 | 2015-02-25 | 苏州宽温电子科技有限公司 | A kind of differential architecture read-only memory unit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080008019A1 (en) * | 2006-07-06 | 2008-01-10 | Texas Instruments Incorporated | High Speed Read-Only Memory |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1726562A (en) * | 2002-12-19 | 2006-01-25 | 恩艾斯克株式会社 | CMIS semiconductor nonvolatile storage circuit |
| CN204178726U (en) * | 2014-09-25 | 2015-02-25 | 苏州宽温电子科技有限公司 | A kind of differential architecture read-only memory unit |
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