CN104282740A - Silicon-on-insulator lateral P-type insulated gate bipolar transistor - Google Patents
Silicon-on-insulator lateral P-type insulated gate bipolar transistor Download PDFInfo
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- CN104282740A CN104282740A CN200910212770.1A CN200910212770A CN104282740A CN 104282740 A CN104282740 A CN 104282740A CN 200910212770 A CN200910212770 A CN 200910212770A CN 104282740 A CN104282740 A CN 104282740A
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- igbt
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- 239000012212 insulator Substances 0.000 title claims abstract description 24
- 239000004065 semiconductor Substances 0.000 claims abstract description 37
- 210000003323 beak Anatomy 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 14
- 229920005591 polysilicon Polymers 0.000 claims description 14
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 7
- 229910052760 oxygen Inorganic materials 0.000 claims description 7
- 239000001301 oxygen Substances 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000035755 proliferation Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7394—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
Abstract
The invention discloses a silicon-on-insulator lateral P-type insulated gate bipolar transistor which comprises an N-type doped semiconductor substrate. The N-type doped semiconductor substrate is provided with a buried oxide layer on which a P-type drift region is arranged. The P-type drift region is internally provided with a P-type doped semiconductor region with a relatively high concentration. The P-type doped semiconductor region with the relatively high concentration is arranged below a beak region at the right end of a field oxide layer and surrounds the whole beak region, wherein the concentration of the P-type doped semiconductor region is higher than the concentration of the P-type drift region. Simultaneously, the anode contact area of the silicon-on-insulator lateral P-type insulated gate bipolar transistor is formed through alternately arranging P-type doped areas and N-type doped areas in the width direction of the silicon-on-insulator lateral P-type insulated gate bipolar transistor. Furthermore, the field oxide layer of the silicon-on-insulator lateral P-type insulated gate bipolar transistor belongs to a two-grade field oxide layer. A field plate which is formed through extension of a gate electrode to the part above the field oxide layer is also a two-grade field board. The silicon-on-insulator lateral P-type insulated gate bipolar transistor has effectively improved lateral voltage resistance.
Description
Technical field
The invention belongs to technical field of integrated circuits, relate to a kind of horizontal high voltage power device, in particular, is about a kind of transverse P-type igbt simultaneously with the silicon-on-insulator of fast switching speed and large On current.
Background technology
Igbt (IGBT) is that one has the insulated gate structure advantage of metal-oxide semiconductor (MOS) (MOS) transistor and has the device of high current density advantage of bipolar transistor, and it is a kind of power semiconductor that can be used for the conduction loss effectively reducing traditional power MOSFET (mos field effect transistor).
At present, this kind of power device obtains and applies very widely in power integrated circuit, such as at plasma panel (Plasma Display Panel, be called for short PDP) driving chip in, due to the similar common fluorescent lamp of PDP working mechanism, drive circuit needs high potential to discharge, therefore drive circuit must use higher withstand voltage power-type lateral double-diffused metallic oxide semiconductor tube (Lateral Double DiffusedMOSFET at first, be called for short LDMOS), but the On current of LDMOS is less, in order to obtain larger operating current, promote driving power, multiple LDMOS is needed to carry out parallel connection to realize, but which adds chip manufacturing cost.For solving the deficiency of above-mentioned LDMOS in PDP driving chip realizes, replace LDMOS with lateral insulated gate bipolar transistor (Lateral Insulated Gate Bipolar Transistor is called for short LIGBT) and be applied to the extensive concern that PDP driving chip causes people.Simultaneously, silicon-on-insulator (Silicon On Insulator, being called for short SOI) technology is with its desirable Fully dielectric isolation performance, relatively simple isolation technology, the ghost effect significantly weakened, and compatible mutually and get most of the attention with complementary metal-oxide-semiconductor (CMOS) very lagre scale integrated circuit (VLSIC) (VLSI) manufacturing process.Therefore by SOI technology for the manufacture of LIGBT, the silicon-on-insulator lateral igbt (being called for short SOI-LIGBT) be configured to has isolation performance number, little and the puncture voltage advantages of higher of leakage current, development potentiality is huge, nowadays the manufacture level of SOI-LIGBT is more and more ripe, replaces LDMOS be used for the manufacture of PDP driving chip to reduce costs the inexorable trend becoming development with SOI-LIGBT.In the manufacture of existing PDP driving chip, use the LDMOS of P type raceway groove LDMOS and N-type raceway groove simultaneously, but only had the SOI-LIGBT of N-type raceway groove at present, there is no the SOI-LIGBT of P type raceway groove.
Summary of the invention
The present invention is directed to the deficiencies in the prior art, propose a kind of transverse P-type igbt and its manufacture method of silicon-on-insulator, the igbt of the silicon-on-insulator of this P type raceway groove can be used for replacing P type raceway groove LDMOS in PDP driving chip.
The present invention adopts following technical scheme:
N-type dope semiconductor substrates, oxygen buried layer is provided with on described N-type dope semiconductor substrates, described oxygen buried layer is provided with N-type doped epitaxial layer, P type doping deep-well region is provided with in the left side of described N-type doped epitaxial layer, N-type doping deep-well region is provided with on the right side of described N-type doped epitaxial layer, above described P type doping deep-well region and the described N-type doped epitaxial layer of part, be provided with P type doped drift region, above described N-type doping deep-well region and the described N-type doped epitaxial layer of part, be provided with N-type doped semiconductor area.In described P type doped drift region, left side is provided with P type doped buffer region, N-type doped region is provided with in described P type doped buffer region, described P type doped buffer region and N-type doped region form the positive contact region of described igbt jointly, P type doped region and N-type doped region is provided with in described N-type doped semiconductor area, described P type doped region and N-type doped region form the cathode contact region of described igbt jointly, gate oxide is provided with above part described P type doped drift region and the described N-type doped semiconductor area of part, field oxide is provided with above part described P type doped drift region, beak region 18 and 19 is all there is at the left and right sides end of described field oxide, metal level is provided with above described positive contact region, constitute the anode metal electrodes of described igbt, metal level is provided with above described cathode contact region, constitute the cathodic metal electrode of described igbt, polysilicon is provided with above described gate oxide, and the top that the left end of described polysilicon extends to described field oxide forms polysilicon field plate structure.
Compared with prior art, tool of the present invention has the following advantages:
(1) in structure of the present invention, a higher concentration P type doped semiconductor area is provided with below the beak region of oxygen right end on the scene, its concentration is higher than the concentration of P type doped drift region, therefore effectively can stop the horizontal proliferation of right side N-type doping deep-well region, thus effective channel length can be reduced, reduce the threshold voltage of device.
(2) present invention employs the structure of second order field oxide and second order field plate, effectively can improve the horizontal withstand voltage level of device.
(3) what positive contact region of the present invention adopted is the form that P type contact area and N-type contact area are arranged alternately with each other in the direction of the width, such structure reduces the extraction time of the few son of device, thus shorten the turn-off time of device, reduce the shutoff power consumption of device.
Accompanying drawing explanation
Fig. 1 is the profile of an embodiment of the transverse P-type igbt of a kind of silicon-on-insulator of the present invention.
Fig. 2 is the space schematic top plan view of the anode region of the transverse P-type igbt of a kind of silicon-on-insulator of the present invention, (wherein Z-direction is the Width of device).
Embodiment
With reference to Fig. 1, a kind of transverse P-type igbt of silicon-on-insulator, comprise: N-type dope semiconductor substrates 1, oxygen buried layer 2 is provided with on described N-type dope semiconductor substrates 1, described oxygen buried layer 2 is provided with N-type doped epitaxial layer 3, P type doping deep-well region 4 is provided with in the left side of described N-type doped epitaxial layer 3, N-type doping deep-well region 5 is provided with on the right side of described N-type doped epitaxial layer 3, P type doped drift region 6 is provided with above described P type doping deep-well region 4 and the described N-type doped epitaxial layer 3 of part, N-type doped semiconductor area 7 is provided with above described N-type doping deep-well region 5 and the described N-type doped epitaxial layer 3 of part.In described P type doped drift region 6, left side is provided with P type doped buffer region 9, N-type doped region 10 is provided with in described P type doped buffer region 9, described P type doped buffer region 9 and N-type doped region 10 form the positive contact region of described igbt jointly, P type doped region 11 and N-type doped region 12 is provided with in described N-type doped semiconductor area 7, described P type doped region 11 and N-type doped region 12 form the cathode contact region of described igbt jointly, gate oxide 13 is provided with above part described P type doped drift region 6 and the described N-type doped semiconductor area 7 of part, field oxide 14 is provided with above part described P type doped drift region 6, beak region 18 and 19 is all there is at the left and right sides end of described field oxide 14, metal level 16 is provided with above described positive contact region, constitute the anode metal electrodes of described igbt, metal level 15 is provided with above described cathode contact region, constitute the cathodic metal electrode of described igbt, polysilicon 17 is provided with above described gate oxide 13, and the top that the left end of described polysilicon 17 extends to described field oxide 14 forms polysilicon field plate structure.
In described P type doped drift region 6, right side is provided with P type doped semiconductor area 8, and the concentration of P type doped semiconductor area 8 is higher than the concentration of P type doped drift region 6;
Described P type doped semiconductor area 8 is positioned at the below in field oxide 14 right end beak region 19, and P type doped semiconductor area 8 surrounds whole beak region, but the right side boundary of P type doped semiconductor area 8 is no more than the right side boundary of P type doped drift region 6;
The positive contact region of described device architecture is alternately arranged by N-type doped region 10 and P type doped region 9 and is formed on the Width of device, and the size of On current that should be met by this device of the width ratio between N-type doped region 10 and P type doped region 9 and the speed of switch determine jointly;
Described field oxide 14 is second order field oxides;
The field plate structure that the top that described polysilicon 17 extends to field oxide 14 is formed is second order field plate structure;
With reference to Fig. 2, this figure is the space schematic top plan view in the positive contact region of the transverse P-type igbt of a kind of silicon-on-insulator of the present invention, in figure, 9 is P type doped regions of high concentration, the positive contact region of the P type doped region 9 be alternately arranged and N-type doped region 10 composition device jointly.
The present invention adopts and prepares with the following method:
1, get one piece of N-type SOI, epitaxial growth N-type epitaxy layer, form N-type doped epitaxial layer 3, then adopt ion implantation and follow-up annealing process to form P type doping deep-well region 4 and N-type doping deep-well region 5;
2, adopt ion implantation technology to form P type doped drift region 6, type doped buffer region, type doped semiconductor area 8, P, N-type doped semiconductor area 7, P 9, then generate second order field oxide 14 through overheated growth and etching technics;
3, then grow gate oxide 13, depositing polysilicon, and carry out etching formation polysilicon gate and polysilicon field plate structure, then form type doping cathode contact region 11, N-type doping positive contact region 10, P and N-type adulterate body contact zone 12 through ion implantation.
4, through deposit aluminium and etching aluminium technique, form metal level 15 and metal level 16, wherein metal level 16 is as the anode of device, and metal level 15 is as the negative electrode of device.Finally carry out follow-up Passivation Treatment.
Claims (7)
1. the transverse P-type igbt of a silicon-on-insulator, comprise: N-type dope semiconductor substrates (1), oxygen buried layer (2) is provided with on described N-type dope semiconductor substrates (1), described oxygen buried layer (2) is provided with N-type doped epitaxial layer (3), P type doping deep-well region (4) is provided with in the left side of described N-type doped epitaxial layer (3), N-type doping deep-well region (5) is provided with on the right side of described N-type doped epitaxial layer (3), P type doped drift region (6) is provided with in the top of described P type doping deep-well region (4) and the described N-type doped epitaxial layer (3) of part, N-type doped semiconductor area (7) is provided with in the top of described N-type doping deep-well region (5) and the described N-type doped epitaxial layer (3) of part, in described P type doped drift region (6), left side is provided with P type doped buffer region (9), N-type doped region (10) is provided with in described P type doped buffer region (9), described P type doped buffer region (9) and N-type doped region (10) form the positive contact region of described igbt jointly, P type doped region (11) and N-type doped region (12) is provided with in described N-type doped semiconductor area (7), described P type doped region (11) and N-type doped region (12) form the cathode contact region of described igbt jointly, gate oxide (13) is provided with in the top of part described P type doped drift region (6) and the described N-type doped semiconductor area (7) of part, field oxide (14) is provided with in the top of part described P type doped drift region (6), all there are beak region (18) and (19) at the left and right sides end of described field oxide (14), metal level (16) is provided with above described positive contact region, constitute the anode metal electrodes of described igbt, metal level (15) is provided with above described cathode contact region, constitute the cathodic metal electrode of described igbt, polysilicon (17) is provided with in the top of described gate oxide (13), and the top that the left end of described polysilicon (17) extends to described field oxide (14) forms polysilicon field plate structure, it is characterized in that, in described P type doped drift region (6), right side is provided with P type doped semiconductor area (8), the concentration of described P type doped semiconductor area (8) is higher than the concentration of described P type doped drift region (6), described N-type doping positive contact region (10) and described P type doping positive contact region (9) are alternately arranged.
2. the transverse P-type igbt of silicon-on-insulator according to claim 1, it is characterized in that, described P type doped semiconductor area (8) is positioned at the below of described field oxide (14) right end beak region (19).
3. the transverse P-type igbt of silicon-on-insulator according to claim 1, it is characterized in that, described P type doped semiconductor area (8) surrounds whole described field oxide (14) right end beak region (19), but the right side boundary of described P type doped semiconductor area (8) is no more than the right side boundary of described P type doped drift region (6).
4. the transverse P-type igbt of silicon-on-insulator according to claim 1, it is characterized in that, described positive contact region is discontinuous region on the Width of device, for the structure that described N-type doped region (10) and described P type doped region (9) are alternately formed, and the width of described N-type doped region (10) is greater than described P type doped region (9).
5. the transverse P-type igbt of silicon-on-insulator according to claim 4, it is characterized in that, the width ratio relation of described N-type doped region (10) and described P type doped region (9) is determined by the On current index of this device.
6. the transverse P-type igbt of silicon-on-insulator according to claim 1, is characterized in that, described field oxide (14) is a second order field oxide.
7. the transverse P-type igbt of silicon-on-insulator according to claim 1, it is characterized in that, the field plate structure that the top that described polysilicon (17) extends to described field oxide (14) is formed is second order field plate structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910212770.1A CN104282740B (en) | 2009-11-09 | 2009-11-09 | The transverse P-type igbt of silicon-on-insulator |
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| Application Number | Priority Date | Filing Date | Title |
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| CN200910212770.1A CN104282740B (en) | 2009-11-09 | 2009-11-09 | The transverse P-type igbt of silicon-on-insulator |
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| CN104282740A true CN104282740A (en) | 2015-01-14 |
| CN104282740B CN104282740B (en) | 2017-03-01 |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH098322A (en) * | 1995-06-14 | 1997-01-10 | Samsung Electron Co Ltd | Hybrid schottky injection field-effect transistor |
| EP0682811B1 (en) * | 1993-12-08 | 1999-04-21 | Koninklijke Philips Electronics N.V. | Lateral semiconductor-on-insulator (soi) semiconductor device having a buried diode |
| US6191456B1 (en) * | 1998-06-26 | 2001-02-20 | Siemens Aktiengesellschaft | Lateral IGBT in an SOI configuration and method for its fabrication |
| US6198130B1 (en) * | 1997-08-04 | 2001-03-06 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method for manufacturing the same |
| CN101288176A (en) * | 2005-10-12 | 2008-10-15 | 富士电机控股株式会社 | Traverse type IGBT of SOI groove |
| JP4175750B2 (en) * | 1999-10-27 | 2008-11-05 | 株式会社東芝 | Insulated gate semiconductor device |
-
2009
- 2009-11-09 CN CN200910212770.1A patent/CN104282740B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0682811B1 (en) * | 1993-12-08 | 1999-04-21 | Koninklijke Philips Electronics N.V. | Lateral semiconductor-on-insulator (soi) semiconductor device having a buried diode |
| JPH098322A (en) * | 1995-06-14 | 1997-01-10 | Samsung Electron Co Ltd | Hybrid schottky injection field-effect transistor |
| US6198130B1 (en) * | 1997-08-04 | 2001-03-06 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method for manufacturing the same |
| US6191456B1 (en) * | 1998-06-26 | 2001-02-20 | Siemens Aktiengesellschaft | Lateral IGBT in an SOI configuration and method for its fabrication |
| JP4175750B2 (en) * | 1999-10-27 | 2008-11-05 | 株式会社東芝 | Insulated gate semiconductor device |
| CN101288176A (en) * | 2005-10-12 | 2008-10-15 | 富士电机控股株式会社 | Traverse type IGBT of SOI groove |
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| CN104282740B (en) | 2017-03-01 |
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