CN104282594A - Test structure for monitoring performance of dielectric layers - Google Patents
Test structure for monitoring performance of dielectric layers Download PDFInfo
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- CN104282594A CN104282594A CN201410557542.9A CN201410557542A CN104282594A CN 104282594 A CN104282594 A CN 104282594A CN 201410557542 A CN201410557542 A CN 201410557542A CN 104282594 A CN104282594 A CN 104282594A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
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- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
Abstract
The invention provides a test structure for monitoring the performance of dielectric layers. A first metal connecting wire and a second metal connecting wire which are staggered and arranged in a comb shape are formed in the dielectric layer between first metal layers, a third metal connecting wire and a fourth metal connecting wire which are staggered and arranged in a comb shape are formed in the dielectric layer between second metal layers, a dielectric interlayer is formed between the dielectric layer between the first metal layers and the dielectric layer between the second metal layers, the first metal connecting wire is connected with the fourth metal connecting wire through through hole connecting wires, and the second metal connecting wire and the third metal connecting wire are connected through through hole connecting wires. By monitoring the leakage current between the first metal connecting wire and the second metal connecting wire, the performance of the same dielectric layer and different dielectric layers can be monitored, and the monitoring efficiency is improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of test structure of monitoring dielectric film performance.
Background technology
In semiconductor fabrication, dielectric layer plays a part to isolate different components, different metal line etc., along with the integrated level of semiconductor device is more and more higher, also more and more stricter to the performance requirement of dielectric layer.The quality of dielectric layer often can affect the yield of whole chip.In order to the dielectric layer performance of formation can be monitored how, following several test structure in prior art, is usually adopted to monitor.
Please refer to Fig. 1 a and Fig. 1 b, Fig. 1 a and Fig. 1 b is the first test structure in prior art, wherein, Fig. 1 b be along A-A ' in Fig. 1 a to generalized section, the first test structure comprises: the first metal wire 10, second metal wire 11 and the 3rd metal wire 12, wherein, described first metal wire 10, second metal wire 11 and the 3rd metal wire 12 are all formed in metal interlamination medium layer 13, and have metal interlamination medium layer 13 to keep apart, described first metal wire 10 and the 3rd metal wire 12 are pectinate texture, second metal wire 11 is serpentine configuration, and interlaced arrangement.When monitoring, voltage can be applied on the first metal wire 10, thus test the first metal wire 10 and the second metal wire 11 or whether there is the performance that leakage current can monitor out metal interlamination medium layer 13 between the second metal wire 11 and the 3rd metal wire 12.Second metal wire 11 also can monitor the resistance of metal wire.
Please refer to Fig. 2 a and 2b, Fig. 2 a and Fig. 2 b is the second test structure in prior art, wherein, Fig. 2 b be along B-B ' in Fig. 2 a to generalized section, the second test structure comprises: the first metal wire 10, second metal wire 11 and through hole line 20, wherein, described first metal wire 10, second metal wire 11 is formed in the metal interlamination medium layer 13 of same layer, first metal wire 10, second metal wire 11 is pectinate texture, and interlaced arrangement, through hole line 20 all with described first metal wire 10, second metal wire 11 is connected, and be arranged in interlayer dielectric layer 14.The method of testing of the second test structure is identical with the method for testing of the first test structure, all apply voltage at the first metal wire 10 end, monitor the leakage current between the first metal wire 10 and the second metal wire 11, because through hole line 20 is connected with the second metal wire 11 with the first metal wire 10, if thus side skew occurs through hole line 20, then can monitor out the leakage current produced when skew occurs through hole line 20.
Please refer to Fig. 3 a and Fig. 3 b, Fig. 3 a and Fig. 3 b is the third test structure in prior art, wherein, Fig. 3 b be along C-C ' in Fig. 3 a to generalized section, the third test structure comprises: the first metal wire 10 and the second metal wire 11, wherein, first metal wire 10 and the second metal wire 11 are formed in the metal interlamination medium layer 13 and 15 of different layers, and be formed with interlayer dielectric layer 14 between different layers metal interlamination medium layer 13 and 15, first metal wire 10, second metal wire 11 is pectinate texture, and is positioned at same vertical position.The third test structure can monitor out the performance of interlayer dielectric layer 14.
Please refer to Fig. 4 a and Fig. 4 b, Fig. 4 a and Fig. 4 b is the 4th kind of test structure in prior art, wherein, Fig. 4 b be along D-D ' in Fig. 4 a to generalized section, 4th kind of test structure and the third test structure difference are that the first metal wire 10 and the second metal wire 11 are bulk, area is comparatively large, is formed with interlayer dielectric layer 14 between the two, adopts the 4th kind of test structure can carry out the monitoring of intrinsic to the performance of interlayer dielectric layer 14.
From above, several test structure of the prior art only can be simple the dielectric layer to same layer or interlayer dielectric layer is monitored, and can not dielectric layer (as the interlayer dielectric layer) performance between the dielectric layer of same layer and different layers be monitored, be unfavorable for improving monitoring efficiency. simultaneously
Summary of the invention
The object of the present invention is to provide a kind of test structure of monitoring dielectric film performance, can monitor the performance of the dielectric layer of same layer and the dielectric layer of different layers simultaneously, improve the efficiency of monitoring.
To achieve these goals, the present invention proposes a kind of test structure of monitoring dielectric film performance, comprise: the first metal wire (100), second metal connecting line (200), 3rd metal connecting line (300), 4th metal connecting line (400) and through hole line (500), wherein, described first metal wire (100) and the second metal connecting line (200) are formed in the first layer metal interlayer dielectric layer (600) of same layer, described first metal wire (100) and the second metal connecting line (200) are pectinate texture, and be staggered, described 3rd metal connecting line (300) and the 4th metal connecting line (400) are formed in the second layer metal interlayer dielectric layer (800) of same layer, described 3rd metal connecting line (300) and the 4th metal connecting line (400) are pectinate texture, and be staggered, described through hole line (500) is formed in interlayer dielectric layer (700), described interlayer dielectric layer (700) is positioned between described first layer metal interlayer dielectric layer (600) and second layer metal interlayer dielectric layer (800), described through hole line (500) is for connecting described first metal wire (100) and the 4th metal connecting line (400) and described second metal connecting line (200) and the 3rd metal connecting line (300).
Further, also comprise the first test panel and the second test panel, described first test panel connects described first metal wire (100) and the 4th metal connecting line (400), and described second test panel connects described second metal connecting line (200) and the 3rd metal connecting line (300).
Further, the pectinate texture of described first metal wire (100) and the second metal connecting line (200) is positioned at first direction (Y), the pectinate texture of described 3rd metal connecting line (300) and the 4th metal connecting line (400) is positioned at second direction (X), and described first direction (Y) is mutually vertical with second direction (X).
Further, described through hole line (500) diagonal angle arrangement.
Further, adjacent the first metal wire (100) and the second metal connecting line (200), spacing between the 3rd metal connecting line (300) and the 4th metal connecting line (400) meet the minimum spacing that design specification allows.
Compared with prior art, beneficial effect of the present invention is embodied in: in first layer metal interlayer dielectric layer, form staggered first metal connecting line of pectination and the second metal connecting line, staggered 3rd metal connecting line of pectination and the 4th metal connecting line is formed in second layer metal interlayer dielectric layer, interlayer dielectric layer is formed between first layer metal interlayer dielectric layer and second layer metal interlayer dielectric layer, first metal wire is connected by through hole line with the 3rd metal connecting line with the 4th metal connecting line and the second metal connecting line, just the performance of the dielectric layer of monitoring same layer and different layers can be realized by the leakage current of monitoring between the first metal wire and the second metal wire, improve monitoring efficiency.
Accompanying drawing explanation
Fig. 1 a and Fig. 1 b is the structural representation of the first test structure in prior art;
Fig. 2 a and Fig. 2 b is the structural representation of the second test structure in prior art;
Fig. 3 a and Fig. 3 b is the structural representation of the third test structure in prior art;
Fig. 4 a and Fig. 4 b is the structural representation of the 4th kind of test structure in prior art;
Fig. 5 is the structural representation of the test structure of monitoring dielectric film performance in one embodiment of the invention;
Fig. 6 is the generalized section along X-direction in Fig. 5;
Fig. 7 is the generalized section along Y-direction in Fig. 5.
Embodiment
Be described in more detail below in conjunction with the test structure of schematic diagram to monitoring dielectric film performance of the present invention, which show the preferred embodiments of the present invention, should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
In order to clear, whole features of practical embodiments are not described.They in the following description, are not described in detail known function and structure, because can make the present invention chaotic due to unnecessary details.Will be understood that in the exploitation of any practical embodiments, a large amount of implementation detail must be made to realize the specific objective of developer, such as, according to regarding system or the restriction about business, change into another embodiment by an embodiment.In addition, will be understood that this development may be complicated and time-consuming, but be only routine work to those skilled in the art.
In the following passage, more specifically the present invention is described by way of example with reference to accompanying drawing.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, the aid illustration embodiment of the present invention lucidly.
Please refer to Fig. 5 to Fig. 7, in the present embodiment, propose a kind of test structure of monitoring dielectric film performance, comprise: the first metal wire 100, second metal connecting line 200, 3rd metal connecting line 300, 4th metal connecting line 400 and through hole line 500, wherein, described first metal wire 100 and the second metal connecting line 200 are formed in the first layer metal interlayer dielectric layer 600 of same layer, described first metal wire 100 and the second metal connecting line 200 are pectinate texture, and be staggered, described 3rd metal connecting line 300 and the 4th metal connecting line 400 are formed in the second layer metal interlayer dielectric layer 800 of same layer, described 3rd metal connecting line 300 and the 4th metal connecting line 400 are pectinate texture, and be staggered, described through hole line 500 is formed in interlayer dielectric layer 700, described interlayer dielectric layer 700 is between described first layer metal interlayer dielectric layer 600 and second layer metal interlayer dielectric layer 800, described through hole line 500 is for connecting described first metal wire 100 and the 4th metal connecting line 400 and described second metal connecting line 200 and the 3rd metal connecting line 300.
Concrete, the pectinate texture of described first metal wire 100 and the second metal connecting line 200 is positioned at first direction Y, the pectinate texture of described 3rd metal connecting line 300 and the 4th metal connecting line 400 is positioned at second direction X, described first direction Y is mutually vertical with second direction X, even if described first metal wire 100 is vertical with the pectinate texture of the 4th metal connecting line 400 with described 3rd metal connecting line 300 with the pectinate texture of the second metal connecting line 200.
In the present embodiment, offset the performance losses of the interlayer dielectric layer 400 caused in order to described through hole line 500 more comprehensively can be monitored, described through hole line 500 diagonal angle is arranged.No matter when can there is skew towards X-direction or Y-direction in through hole line 500, the interlayer dielectric layer 400 caused damage all can monitored go out.
Because the spacing between metal wire is less, more easily monitor out the problem of dielectric layer, and spacing is too small, then the device of formation can be caused normally to use.Therefore, in order to improve the precision of monitoring, and do not affect the production requirement of technique, the first adjacent metal wire 100 and the second metal connecting line 200 can be made, spacing between the 3rd metal connecting line 300 and the 4th metal connecting line 400 meets the minimum spacing that design specification allows.
Conveniently monitor, the test structure of the monitoring dielectric film performance that the present embodiment proposes also comprises the first test panel and the second test panel (scheming not shown), described first test panel connects described first metal wire 100 and the 4th metal connecting line 400, and described second test panel connects described second metal connecting line 200 and the 3rd metal connecting line 300.
When testing, only need to apply voltage to the first test panel, thus whether there is the performance that leakage current can judge the metal interlamination medium layer of same layer and the interlayer dielectric layer with its different layers between test the first test panel and the second test panel, through hole line can be monitored out in addition occur to offset the problem caused, for follow-up Resolving probiems provides a kind of useful analytical information.
To sum up, in the test structure of the monitoring dielectric film performance provided in the embodiment of the present invention, staggered first metal connecting line of pectination and the second metal connecting line is formed in first layer metal interlayer dielectric layer, staggered 3rd metal connecting line of pectination and the 4th metal connecting line is formed in second layer metal interlayer dielectric layer, interlayer dielectric layer is formed between first layer metal interlayer dielectric layer and second layer metal interlayer dielectric layer, first metal wire is connected by through hole line with the 3rd metal connecting line with the 4th metal connecting line and the second metal connecting line, just the performance of the dielectric layer of monitoring same layer and different layers can be realized by the leakage current of monitoring between the first metal wire and the second metal wire, improve monitoring efficiency.
Above are only the preferred embodiments of the present invention, any restriction is not played to the present invention.Any person of ordinary skill in the field; in the scope not departing from technical scheme of the present invention; the technical scheme disclose the present invention and technology contents make the variations such as any type of equivalent replacement or amendment; all belong to the content not departing from technical scheme of the present invention, still belong within protection scope of the present invention.
Claims (5)
1. the test structure of a monitoring dielectric film performance, it is characterized in that, comprise: the first metal wire (100), second metal connecting line (200), 3rd metal connecting line (300), 4th metal connecting line (400) and through hole line (500), wherein, described first metal wire (100) and the second metal connecting line (200) are formed in the first layer metal interlayer dielectric layer (600) of same layer, described first metal wire (100) and the second metal connecting line (200) are pectinate texture, and be staggered, described 3rd metal connecting line (300) and the 4th metal connecting line (400) are formed in the second layer metal interlayer dielectric layer (800) of same layer, described 3rd metal connecting line (300) and the 4th metal connecting line (400) are pectinate texture, and be staggered, described through hole line (500) is formed in interlayer dielectric layer (700), described interlayer dielectric layer (700) is positioned between described first layer metal interlayer dielectric layer (600) and second layer metal interlayer dielectric layer (800), described through hole line (500) is for connecting described first metal wire (100) and the 4th metal connecting line (400) and described second metal connecting line (200) and the 3rd metal connecting line (300).
2. the test structure of monitoring dielectric film performance as claimed in claim 1, it is characterized in that, also comprise the first test panel and the second test panel, described first test panel connects described first metal wire (100) and the 4th metal connecting line (400), and described second test panel connects described second metal connecting line (200) and the 3rd metal connecting line (300).
3. the test structure of monitoring dielectric film performance as claimed in claim 1, it is characterized in that, the pectinate texture of described first metal wire (100) and the second metal connecting line (200) is positioned at first direction (Y), the pectinate texture of described 3rd metal connecting line (300) and the 4th metal connecting line (400) is positioned at second direction (X), and described first direction (Y) is mutually vertical with second direction (X).
4. the test structure of monitoring dielectric film performance as claimed in claim 1, is characterized in that, the arrangement of described through hole line (500) diagonal angle.
5. the test structure of monitoring dielectric film performance as claimed in claim 1, it is characterized in that, adjacent the first metal wire (100) and the second metal connecting line (200), spacing between the 3rd metal connecting line (300) and the 4th metal connecting line (400) meet the minimum spacing that design specification allows.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201410557542.9A CN104282594A (en) | 2014-10-20 | 2014-10-20 | Test structure for monitoring performance of dielectric layers |
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| CN201410557542.9A CN104282594A (en) | 2014-10-20 | 2014-10-20 | Test structure for monitoring performance of dielectric layers |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106328630A (en) * | 2016-11-09 | 2017-01-11 | 上海华力微电子有限公司 | Testing structure and testing method for monitoring isolation performance among different layers of metal layer |
| JP2017108138A (en) * | 2015-12-09 | 2017-06-15 | 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． | Test pattern, and computer-implemented method for designing integrated circuit layout |
| CN107346751A (en) * | 2016-05-05 | 2017-11-14 | 中芯国际集成电路制造(上海)有限公司 | Test structure and forming method thereof and method of testing |
| CN107579016A (en) * | 2017-08-31 | 2018-01-12 | 长江存储科技有限责任公司 | A kind of interdigitated test structure |
| CN107978537A (en) * | 2016-10-25 | 2018-05-01 | 中芯国际集成电路制造(上海)有限公司 | Test structure and test cell |
| CN109801855A (en) * | 2019-01-22 | 2019-05-24 | 上海华虹宏力半导体制造有限公司 | For detecting WAT test device, preparation method and the test method of metal connecting line protuberance |
| CN112103202A (en) * | 2020-11-10 | 2020-12-18 | 晶芯成(北京)科技有限公司 | Semiconductor test structure and quality test method of semiconductor passivation layer |
| CN112366199A (en) * | 2020-11-10 | 2021-02-12 | 西安紫光国芯半导体有限公司 | Metal wiring structure of chip and chip thereof |
| CN113066782A (en) * | 2021-03-15 | 2021-07-02 | 上海华力微电子有限公司 | Electromigration test structure with failure analysis scale |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1527385A (en) * | 2003-03-04 | 2004-09-08 | 台湾积体电路制造股份有限公司 | Multilayer composite metal capacitor structure |
| CN2686061Y (en) * | 2004-01-12 | 2005-03-16 | 威盛电子股份有限公司 | Electric capacity pair structure capable of raising matching |
| US20100061036A1 (en) * | 2004-07-08 | 2010-03-11 | Harris Edward B | Interdigitated capacitors |
-
2014
- 2014-10-20 CN CN201410557542.9A patent/CN104282594A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1527385A (en) * | 2003-03-04 | 2004-09-08 | 台湾积体电路制造股份有限公司 | Multilayer composite metal capacitor structure |
| CN2686061Y (en) * | 2004-01-12 | 2005-03-16 | 威盛电子股份有限公司 | Electric capacity pair structure capable of raising matching |
| US20100061036A1 (en) * | 2004-07-08 | 2010-03-11 | Harris Edward B | Interdigitated capacitors |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017108138A (en) * | 2015-12-09 | 2017-06-15 | 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． | Test pattern, and computer-implemented method for designing integrated circuit layout |
| CN107346751A (en) * | 2016-05-05 | 2017-11-14 | 中芯国际集成电路制造(上海)有限公司 | Test structure and forming method thereof and method of testing |
| CN107346751B (en) * | 2016-05-05 | 2020-03-10 | 中芯国际集成电路制造(上海)有限公司 | Test structure, forming method thereof and test method |
| CN107978537B (en) * | 2016-10-25 | 2020-06-09 | 中芯国际集成电路制造(上海)有限公司 | Test structure and test unit |
| CN107978537A (en) * | 2016-10-25 | 2018-05-01 | 中芯国际集成电路制造(上海)有限公司 | Test structure and test cell |
| CN106328630A (en) * | 2016-11-09 | 2017-01-11 | 上海华力微电子有限公司 | Testing structure and testing method for monitoring isolation performance among different layers of metal layer |
| CN107579016A (en) * | 2017-08-31 | 2018-01-12 | 长江存储科技有限责任公司 | A kind of interdigitated test structure |
| CN107579016B (en) * | 2017-08-31 | 2018-09-14 | 长江存储科技有限责任公司 | A kind of interdigitated test structure |
| CN109801855A (en) * | 2019-01-22 | 2019-05-24 | 上海华虹宏力半导体制造有限公司 | For detecting WAT test device, preparation method and the test method of metal connecting line protuberance |
| CN109801855B (en) * | 2019-01-22 | 2021-01-29 | 上海华虹宏力半导体制造有限公司 | WAT testing device for detecting uplift of metal connecting wire, preparation method and testing method |
| CN112103202A (en) * | 2020-11-10 | 2020-12-18 | 晶芯成(北京)科技有限公司 | Semiconductor test structure and quality test method of semiconductor passivation layer |
| CN112103202B (en) * | 2020-11-10 | 2021-02-12 | 晶芯成(北京)科技有限公司 | Semiconductor test structure and quality test method of semiconductor passivation layer |
| CN112366199A (en) * | 2020-11-10 | 2021-02-12 | 西安紫光国芯半导体有限公司 | Metal wiring structure of chip and chip thereof |
| CN113066782A (en) * | 2021-03-15 | 2021-07-02 | 上海华力微电子有限公司 | Electromigration test structure with failure analysis scale |
| CN113066782B (en) * | 2021-03-15 | 2023-08-18 | 上海华力微电子有限公司 | Electromigration test structure with failure analysis ruler |
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