CN112366199A - Metal wiring structure of chip and chip thereof - Google Patents
Metal wiring structure of chip and chip thereof Download PDFInfo
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- CN112366199A CN112366199A CN202011249489.8A CN202011249489A CN112366199A CN 112366199 A CN112366199 A CN 112366199A CN 202011249489 A CN202011249489 A CN 202011249489A CN 112366199 A CN112366199 A CN 112366199A
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- 239000002184 metal Substances 0.000 title claims abstract description 210
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 210
- 230000008901 benefit Effects 0.000 abstract description 7
- 239000010410 layer Substances 0.000 description 58
- 230000035882 stress Effects 0.000 description 22
- 230000015654 memory Effects 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 230000003252 repetitive effect Effects 0.000 description 5
- 238000013461 design Methods 0.000 description 3
- 238000002474 experimental method Methods 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 238000003491 array Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000032683 aging Effects 0.000 description 1
- 238000007405 data analysis Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
Abstract
The invention provides a metal wiring structure of a chip and the chip thereof. The chip comprises the metal wiring structure. The invention has the following advantages: through the special arrangement of the metal wiring, the reliability problem caused by mechanical stress can be overcome to a great extent, and the working stability of the chip is improved.
Description
Technical Field
The invention relates to the technical field of semiconductor chips, in particular to a metal wiring structure of a chip and the chip.
Background
As chip Feature Size (Feature Size) shrinks, there is mechanical stress in the gaps at the edges of the same level of metal (which can be simply understood as the spaces between the same level of metal lines); especially, when the metal gaps of the multiple metal layers overlap to form different metal layers, the mechanical stress is more obvious.
As shown in one of the prior art Metal wiring plan views of fig. 1, a plan structure of different levels of Metal lines is shown in fig. 1, here illustrating a second level Metal M2(Metal2) and a third level Metal M3(Metal 3). In practice there are still more metal layers, which are not illustrated in fig. 1. The metal wiring (or called connecting wire) of M2 is in a transverse wiring form, as shown in M2, metal wirings M2-a and M2-b; the metal wiring of M3 is in the form of longitudinal traces, as shown by metal wirings M3-a and M3-b of M3. The space between the metal wirings M2-a and M2-b may be referred to as a gap, as shown by gap 11, and the space between the same metal wirings M3-a and M3-b may be referred to as a gap. As shown by the gap 11. Of course, there are many metal lines in an actual chip, and only two layers of metal are shown here for illustrative purposes only.
The edge of M2-a coincides with the terminal edge of M3-a, and the edge of M2-b coincides with the terminal edge of M3-b; the gap between the metal wirings M2-a and M2-b and the gap between the metal wirings M3-a and M3-b coincide, so that an overlapping gap 11 is formed in the space where they coincide.
Of course, the connecting lines of the second layer metal M2 and the third layer metal M3 can also be routed in the same direction, for example, both metal traces M2-a and M2-b are in the same trace pattern (as shown in fig. 2, which is the second plan view of the prior art metal trace), are in the form of horizontal traces in line with metal traces M2-a and M3-b, respectively), or the wires are partially routed in the same manner (as shown in fig. 4, which is a third schematic plan view of the prior art metal wire), the metal wires M2-a and M3-a are both in the form of horizontal wires, the metal wires M2-b and M3-b are not in the form of horizontal wires, the metal wires M2-b and M3-b are in the form of vertical wires, and in short, the overlapped gap 11 is formed in the overlapped (overlapped) space.
For clarity, the cross-sectional view along line AA' of fig. 1 is shown in fig. 4, where additional metal layers are added to fig. 4. As can be seen from fig. 2, the overlapping gaps 11 are formed under the different metal wiring relationships of the different metal layers M2 to Mn.
For the above-mentioned overlap gap 11, in the Layout (Layout) design of a generally existing integrated circuit chip, especially in the wiring of a metal layer, the relationship between the upper and lower layers of the metal is basically not considered, and it is sufficient if the rules such as lvs (Layout letters), drc (design Rule check) and the like are satisfied. This is because the chip feature size was previously large and therefore the distance of the overlapping gap 11 (i.e., the distance between M3-a and M3-b in the figure) was large and did not damage the chip.
However, as the chip feature size is smaller and smaller, the gap is smaller and smaller, and the mechanical stress between the gaps is more and more significant, and the mechanical stress is stretched towards the metal wiring direction (as shown by the black arrow in the figure) on both sides. When there is a metal line below (or above) the gap (e.g., metal wire M1-a of M1 in fig. 2), the mechanical stress may cause damage to the metal line below (or above). Particularly, in the case where a plurality of metal layers are stacked to form an overlapped gap, the influence of mechanical stress on the metal line under the gap (or on the gap) is more significant, and a defect such as a potential crack may be generated in the metal line. Meanwhile, as the characteristic size of the chip is smaller and smaller, the width of the metal wire is smaller and smaller, and the metal wire is broken even due to enough metal stress, so that the chip fails and cannot work normally. The metal wiring M1-a, such as M1 in fig. 4, is damaged due to mechanical stress.
Disclosure of Invention
In order to solve the problems: according to a first aspect of the present invention, the present invention proposes a metal wiring structure of a chip, the metal wiring structure including a plurality of layers of metal wirings, gaps of the plurality of layers of metal wirings being not overlapped.
Preferably, the gaps of the metal wirings of the plurality of layers do not overlap with each other.
Preferably, the gaps of the metal wirings of the adjacent layers do not overlap: the metal wiring edge gaps are crossed or staggered by the wiring of the metal of the adjacent layer.
Further preferably, the adjacent layer metal is the target metal layer and its upper layer metal.
Further preferably, the adjacent layer metal is the target metal layer and its lower layer metal.
Still further preferably, a wiring edge of the upper layer metal or the lower layer metal does not overlap with a wiring edge of the target metal layer.
Still further preferably, the edge of the wiring of the upper layer metal or the lower layer metal is in a tooth shape, a first part of the wiring of the tooth-shaped upper layer metal or the lower layer metal misses the gap inside the edge of the wiring of the target metal layer, and a second part of the wiring of the tooth-shaped upper layer metal or the lower layer metal spans the gap outside the edge of the wiring of the target metal layer.
Further preferably, the teeth of the wiring of the upper layer metal or the lower layer metal are correspondingly arranged in an interdigitated structure.
Further preferably, the wiring of the upper layer metal or the lower layer metal is a plurality of metal wirings arranged in parallel.
According to a second aspect of the present invention, a chip is provided, which includes the metal wiring structure.
Preferably, the chip comprises repeating units.
Further preferably, the repeating unit is a repeating metal wiring.
Further preferably, the chip is an analog or digital chip
Still further preferably, the chip is a memory chip.
Still further preferably, the memory chip is of the volatile or non-volatile type.
Still further preferably, the chip is a logic operation chip with a cache.
Still further preferably, the logic operation chip with the cache is a CPU chip or an SOC.
Still further preferably, the chip is an FPGA chip.
Still further preferably, the metal wiring structure is located in a middle region of the repeating unit.
Still further preferably, the metal wiring structure is located at an edge of the chip.
The invention has the following advantages:
through the special arrangement of the metal wiring, the reliability problem caused by mechanical stress can be overcome to a great extent, and the working stability of the chip is improved.
Drawings
FIG. 1 is one of the schematic plan views of a prior art metal wiring;
FIG. 2 is a second schematic plan view of a prior art metal wiring;
FIG. 3 is a third schematic plan view of a prior art metal wiring;
FIG. 4 is a schematic cross-sectional view of one of the prior art metal wiring plan views;
FIG. 5 illustrates a first preferred embodiment of the present invention;
FIG. 6 illustrates a second preferred embodiment of the present invention;
FIG. 7 illustrates a third preferred embodiment of the present invention;
FIG. 8 illustrates a fourth preferred embodiment of the present invention;
Detailed Description
The present invention will be described more fully with reference to the following embodiments and accompanying drawings.
As will be further explained herein, the reliability of the metal in the chip is difficult to detect. In contrast to the chip function (function) problem, the reliability problem of the chip is implicit in the test verification process of the chip and is difficult to find and locate. In the certification stage after the chip design is completed, a large number of different experiments, such as aging experiments, high and low temperature experiments, etc., are required for reliability. The technical problem to be solved by the invention is discovered based on a large number of different types of experimental data analysis.
The main ideas of the invention are as follows: in the metal (layer) wiring of the chip, the edge of the metal wiring of a plurality of layers is prevented from overlapping or is prevented from overlapping, especially the edge of the metal wiring of the adjacent layers is prevented from overlapping, and the edge gap of the further metal wiring is crossed or staggered by the adjacent (upper layer or lower layer) metal wiring.
As shown in fig. 5, a first preferred embodiment of the present invention; as can be seen from FIG. 5, the two layers of metals M2 and M3 are included; metal M3 is above metal M2. The illustration of only two metal wires is only for clarity of illustration, and in practice, any two or more layers of metal may be used. The metal wiring M2-a and M2-b of M2 form a gap 11 therebetween.
Here and in the following examples M2-a and M2-b of M2 form a gap between them, it can be considered that there is a gap, and the M2 metal layer is considered as the target metal layer, and its adjacent metal layers are disposed to avoid the formation of an overlapping gap. Of course, this is only an illustration, and in practice, any metal layer with a gap may be regarded as an existing gap, and may be treated as a target metal layer, and then metal wirings of adjacent layers thereof are disposed to avoid formation of an overlapping gap.
In order to solve the problems in the background art, metal wirings M3-a and M3-b of metal M3 over metal M2 are specifically provided. In practice, the metal layer below the metal layer M2 may or should be configured accordingly.
The gaps formed by the two wirings M3-a and M3-b of the metal M3 are arranged in a staggered distribution with the gaps formed by the wirings M2-a and M2-b of the metal M2. While one wire M3-b of metal M3 spans the gap 11 of the metal M2 wire.
This has the advantage that by staggering the gaps between adjacent layers of metal wiring, the formation of overlapping gaps is avoided.
In an improved mode of the invention, on the basis of the first embodiment, metal wirings M3-a and M3-b of the metal M3 above the metal M2 are further improved. FIG. 6 illustrates a second preferred embodiment of the present invention; the following is explained in conjunction with fig. 6:
first, similarly to the preferred embodiment, the edge of metal wire M2-a and the end edge of metal wire M3-a are not coincident, nor are the edge of M2-b and the end edge of M3-b coincident; so that they do not form overlapping gaps 11 in the overlapping space. The gap 11 is formed only between the metal wirings M2-a and M2-b of M2. This greatly reduces the mechanical stress at the gap.
Next, the ends (edges) of the metal wirings M3-a and M3-b of the metal layer M3 were specially set. The edges of the metal wires M3-a and M3-b are respectively in a tooth shape. Namely: the ends of the metal wires M3-a and M3-b are no longer on the same horizontal line, with a portion spanning the gap 11 outside the edge of the metal wire M2 (M2-a and M2-b) and another portion inside the edge of the metal wire M2 (M2-a and M2-b). As shown, the ends of the metal wire M3-a in the figure (M3-a1 and M3-a2) are not on the same horizontal line, a portion (M3-a1 in the figure) crosses the gap 11 outside the edge of the metal wire M2-a of M2, and another portion (M3-a 2 in the figure) misses the gap 11 inside the edge of the metal wire M2-a of M2.
In practice it may also be the case that only the metal wiring M3-a or only M3-b is present.
The advantages of this are: not only is the formation of the overlapped gap 11 avoided (the gap 11 in the figure is formed by only a single layer of metal M2), but also the mechanical stress of the gap towards two sides can be reduced because the metal wiring M3-a and/or M3-b partially spans the gap by utilizing the dentate edge formation (for example: M3-a1 is outside the edge of the metal wiring M2-b of M2) and partially departs from the metal gap (for example: M3-a2 is inside the edge of the metal wiring M2-b of M2), thereby better improving the reliability of the chip.
Another improvement of the present invention, optimization based on the second embodiment, is shown in fig. 7, which is a third preferred embodiment of the present invention; as can be seen from FIG. 7, similar to the second preferred embodiment, two layers of metals M2 and M3 are included; metal M3 is above metal M2. Two metal M3 wires M3-a and M3-b, located above metal M2, form an interdigitated structure with toothed edges. The so-called interdigitated structure is shown, with the teeth of the edges of M3-a and M3-b being staggered, respectively.
The interdigitated structure, in addition to the benefits of the first preferred embodiment, also because of the staggered spanning gaps 11: the mechanical stress caused by the gap can be better avoided or reduced.
Another modification of the present invention is shown in fig. 8, which is a fourth preferred embodiment of the present invention; as can be seen from fig. 8, similar to the previous preferred embodiment, the two layers of metals M2 and M3 are included; metal M3 is above metal M2. In contrast, the metal M3 is a plurality of wirings arranged in parallel, such as upper wirings M3-a1, M3-a2 … … M3-an; lower wirings M3-b1, M3-b2 … … M3-bn. With the metal wiring in such a manner, the corresponding wirings are staggered with each other to form an interdigitated structure collectively.
Namely:
the upper metal wire M3-a1 of M3 is located outside the edge of metal wire M2-a so as to span gap 11, and the lower metal wire M3-b1 of the corresponding M3 is located inside the edge of metal wire M2-b so as to stagger gap 11;
the upper metal wire M3-a2 of M3 is located inside the edge of metal wire M2-a, thereby staggering the gap 11, and the lower metal wire M3-b2 of the corresponding M3 is located outside the edge of metal wire M2-b, thereby spanning the gap 11.
The upper and lower metal wires of M3 are arranged in staggered mode.
The benefits of this arrangement are: not only is the formation of the overlapped gap 11 avoided, but also the mechanical stress is offset by the staggered arrangement of different metal wires which are distributed into an interdigital structure, so that the mechanical stress of the gap can be reduced to a greater extent.
It should also be noted that if a large number of repeating units are present in the chip, the mechanical stress is very concentrated in the middle region of the repeating units. The mechanical stress of the above-mentioned metal layers is greatly increased in the case of the prior art described in the background. Mechanical stress can vary dramatically, especially in environments where high and low temperatures alternate. Therefore, the metal wiring arrangement according to the present invention and the above-described embodiments is more required to be used and arranged in the middle region of a large number of repetitive units (or repetitive wirings) of the chip.
It is emphasized here that in both analog and digital chips there may be a large number of repeating units, and that the inventive technique may be used in intermediate positions of the repeating units. Especially in digital circuit based chips. For example, a chip having a large number of memory arrays, typically such as memory chips, where the memory chips may be of the volatile or non-volatile type; or may be embedded memory. Since they have a large number of memory arrays, which are repeating units, in order to store data. In the middle of the memory array, mechanical stresses are more concentrated, and so the techniques of the present invention are more desirable for use. In particular, in the decoding and decoding area of the memory array (especially, decoding and decoding of the corresponding address) and the area for storing data transmission, a large number of repeating units exist, and the repeating units also have a large number of repeated metal wirings, in this case, the aforementioned problem that the chip cannot work due to mechanical stress is more serious, so that in the case that not only the repeating units but also the repeated metal wires are used in the decoding and decoding area, especially, the upper layer metal is used repeatedly, the effect produced by applying the technology of the present invention is better. Of course, the metal wiring with a large number of repetitions is not limited to the decoding area and the area for storing data transmission.
In a logic operation chip with cache, such as a CPU chip or a soc (system On chip) chip, a large amount of computation includes an embedded memory, such as SRAM, even DRAM, etc., therein. As previously mentioned, the techniques of the present invention may also be used in these memories.
In addition, in an FPGA (field programmable Gate Array), there are a large number of repetitive programmable cells, and the middle positions of these repetitive cells may also cause the concentration of mechanical stress, especially when there is metal repetition in these repetitive cells, the possibility of damage caused by mechanical stress is greater, and the invention can be better improved.
In addition, since the mechanical pressure of the housing is more concentrated at the edge of the chip after the chip is packaged, the metal wiring manner should be optimized by the technique of the present invention and the arrangement manner of the metal wiring performed by the above embodiments at the edge of the chip.
The invention has the advantages that: through the special arrangement of the metal wiring, the reliability problem caused by mechanical stress can be overcome to a great extent, and the working stability of the chip is improved.
Claims (10)
1. A metal wiring structure of a chip is characterized in that: the metal wiring structure includes a plurality of layers of metal wirings, and gaps of the plurality of layers of metal wirings do not overlap.
2. The metal wiring structure of claim 1, wherein: the gaps of the metal wirings of the plurality of layers do not overlap with each other, and the gaps of the metal wirings of adjacent layers do not overlap with each other.
3. The metal wiring structure of claim 2, wherein: the gaps of the adjacent layers of metal wiring do not overlap as follows: the metal wiring edge gaps are crossed or staggered by the wiring of the metal of the adjacent layer.
4. The metal wiring structure according to claim 3, wherein: the adjacent layer metal is the target metal layer and the upper layer metal thereof.
5. The metal wiring structure according to claim 3, wherein: the adjacent layer metal is the target metal layer and the lower layer metal thereof.
6. The metal wiring structure according to claim 4 or 5, wherein: and the wiring edge of the upper layer metal or the lower layer metal is not overlapped with the wiring edge of the target metal layer.
7. The metal wiring structure according to claim 4 or 5, wherein: the wiring edge of the upper layer metal or the lower layer metal is in a tooth shape, the first part of the tooth-shaped wiring of the upper layer metal or the lower layer metal misses the gap inside the edge of the target metal layer wiring, and the second part of the tooth-shaped wiring of the upper layer metal or the lower layer metal spans the gap outside the edge of the target metal layer wiring.
8. The metal wiring structure of claim 7, wherein: the teeth of the wiring of the upper layer metal or the lower layer metal are correspondingly arranged into an interdigital structure.
9. The metal wiring structure of claim 7, wherein: the wiring of the upper layer metal or the lower layer metal is a plurality of parallel metal wirings.
10. A chip, characterized by: the chip comprises a metal wiring structure as claimed in any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011249489.8A CN112366199A (en) | 2020-11-10 | 2020-11-10 | Metal wiring structure of chip and chip thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011249489.8A CN112366199A (en) | 2020-11-10 | 2020-11-10 | Metal wiring structure of chip and chip thereof |
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| Publication Number | Publication Date |
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| CN112366199A true CN112366199A (en) | 2021-02-12 |
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| CN202011249489.8A Pending CN112366199A (en) | 2020-11-10 | 2020-11-10 | Metal wiring structure of chip and chip thereof |
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| US20080079026A1 (en) * | 2006-10-03 | 2008-04-03 | Hiroshi Tomotani | Semiconductor integrated circuit |
| CN103531577A (en) * | 2013-10-30 | 2014-01-22 | 西安华芯半导体有限公司 | Metal wiring structure of integrated circuit |
| CN104282594A (en) * | 2014-10-20 | 2015-01-14 | 武汉新芯集成电路制造有限公司 | Test structure for monitoring performance of dielectric layers |
| US20160300764A1 (en) * | 2013-07-05 | 2016-10-13 | Hitachi, Ltd. | Semiconductor device and method for manufacturing the same |
| CN205789942U (en) * | 2016-06-02 | 2016-12-07 | 中芯国际集成电路制造（天津）有限公司 | Semiconductor structure |
| CN213401178U (en) * | 2020-11-10 | 2021-06-08 | 西安紫光国芯半导体有限公司 | Metal wiring device and chip using same |
-
2020
- 2020-11-10 CN CN202011249489.8A patent/CN112366199A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101114305A (en) * | 2006-07-25 | 2008-01-30 | 格科微电子（上海）有限公司 | Standard unit picture structure used for digital circuit |
| US20080079026A1 (en) * | 2006-10-03 | 2008-04-03 | Hiroshi Tomotani | Semiconductor integrated circuit |
| US20160300764A1 (en) * | 2013-07-05 | 2016-10-13 | Hitachi, Ltd. | Semiconductor device and method for manufacturing the same |
| CN103531577A (en) * | 2013-10-30 | 2014-01-22 | 西安华芯半导体有限公司 | Metal wiring structure of integrated circuit |
| CN104282594A (en) * | 2014-10-20 | 2015-01-14 | 武汉新芯集成电路制造有限公司 | Test structure for monitoring performance of dielectric layers |
| CN205789942U (en) * | 2016-06-02 | 2016-12-07 | 中芯国际集成电路制造（天津）有限公司 | Semiconductor structure |
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