CN104280675B - Multi-SITE parallel test method - Google Patents
Multi-SITE parallel test method Download PDFInfo
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- CN104280675B CN104280675B CN201310294841.3A CN201310294841A CN104280675B CN 104280675 B CN104280675 B CN 104280675B CN 201310294841 A CN201310294841 A CN 201310294841A CN 104280675 B CN104280675 B CN 104280675B
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Abstract
The invention relates to the technical field of semiconductor tests, in particular to a multi-SITE parallel test method. Because multi-SITE parallel test design is carried out on an MOSFET product and the drain electrode of the MOSFET serves as the reference ground of a test circuit, on the basis that common test items are carried out on the MOSFET product, the condition of contact between the MOSFET product and a test arm can be tested, and the situation that because of contact problems, a product is damaged in a test can be avoided.
Description
Technical field
The present invention relates to semiconductor test technical field is and in particular to a kind of many SITE parallel test method.
Background technology
MOSFET（Metal oxide layer-semiconductor-field-effect transistor）Abbreviation metal-oxide half field effect transistor, because it is profit
Carry out conduction with a kind of carrier（Unipolar device）, and have input resistance height, preparation process is simple, easy of integration, small power consumption,
The features such as small volume, low cost, so be widely used in analog circuit and digital circuit as field-effect transistor（field-
effect transistor）；MOSFET is different according to the polarity of its " passage ", can be divided into the MOSFET of n-type and p-type,
I.e. NMOSFET and PMOSFET.
At present, when the function to MOSFET product and its superiority-inferiority are tested, mainly include VTH（During product work
Start voltage）、IGSS（Leakage current between grid source electrode）、IDSS（Electric leakage between hourglass source electrode）、RDSON（The leading of chip operation
Energising resistance）、VFSD（The forward voltage drop of diode between hourglass source electrode）Etc. test event, but it is not directed to product and manipulator
（handler）Between contact situation test, if product and manipulator go wrong it is easy to cause in test technology
The damage of product.
Chinese patent（CN102928761A）Describe a kind of wafer test system and crystal round test approach, including probe
Card, probe card sanding apparatus and the wafer test machine including control unit, probe card receives the test letter that wafer test machine sends
Number, the chip to be measured in wafer is tested, after test, test result is fed back to wafer test machine, above-mentioned test result
Source and drain forward conduction voltage drop VFSD including chip to be measured；When continuously occur VFSD be higher or lower than source and drain forward conduction standard
Pressure drop VFSDStandardWhen, stop test, control unit controls probe sanding apparatus that probe card is polished, and after polishing, enters
The test of the next chip to be measured of row.
Chinese patent（CN202330636U）Describe a kind of circuit for testing MOSFET, by by NMOSFET's
The drain voltage of source voltage or PMOSFET is applied to first resistor two ends to determine dash current, and utilizes operation amplifier
Device is to adjust the conducting degree of NMOSFET or PMOSFET, to guarantee the source voltage of NMOSFET or the drain electrode of PMOSFET
Voltage between voltage and pulse signal high period is consistent such that it is able to make dash current be controlled by pulse signal exactly high
Voltage during level.
Content of the invention
The technical solution used in the present invention is：
A kind of many SITE parallel test method, is applied on MOSFET product, wherein, methods described includes：
Some MOS products to be measured are provided；
Test parameter preparation test load plate according to described MOS product to be measured and user test card；
Test event is set on tester table according to testing requirement；
Described tester table utilize described test load plate and described user test card some described MOS to be measured are produced
Product carry out the test of described test event simultaneously；
Wherein, carry out described test event test when MOS product drain electrode be connected with AGND.
Above-mentioned many SITE parallel test method, wherein, methods described also includes：Will be described using transistor-transistor logic circuit
The test signal of MOS product feeds back on described tester table.
Above-mentioned many SITE parallel test method, wherein, described test event include described MOS product and test arm it
Between contact situation test.
Above-mentioned many SITE parallel test method, wherein, described test event also includes startup voltage during product work
Electric leakage current test between electric leakage current test between test, grid source electrode, hourglass source electrode, the conducting resistance test of chip operation and leakage
The forward voltage drop test of diode between source electrode.
Above-mentioned many SITE parallel test method, wherein, methods described also includes：By the grid in described MOS product
Excitation line terminal connect an external impressed current source, and the drain electrode of the grid source class of described MOS product is electrically connected to form a survey grid
The loop of voltage, to carry out the test of the contact situation between described MOS product and described test arm.
Above-mentioned many SITE parallel test method, wherein, described external impressed current source provides the electric current of 0.1mA.
Above-mentioned many SITE parallel test method, wherein, described MOS product to be measured is double MOSFET product.
Above-mentioned many SITE parallel test method, wherein, described pair of MOSFET product includes the first metal-oxide-semiconductor and the 2nd MOS
Pipe；
When carrying out the contact situation test between described MOS product and described test arm, its test circuit includes：
Described external impressed current source is electrically connected with the excitation line terminal of described first metal-oxide-semiconductor grid, described first metal-oxide-semiconductor grid
Measurement circuitry end electrically connect with the excitation line terminal of described first metal-oxide-semiconductor source class, the measurement circuitry of described first metal-oxide-semiconductor source class
End electrically connects with the excitation line terminal of described second metal-oxide-semiconductor grid, the measurement circuitry end of described second metal-oxide-semiconductor grid and described the
The excitation line terminal electrical connection of two metal-oxide-semiconductor source class, the measurement circuitry end of described second metal-oxide-semiconductor source class and described second metal-oxide-semiconductor leakage
The excitation line terminal electrical connection of pole, the excitation line of the measurement circuitry end of described second metal-oxide-semiconductor drain electrode and described first metal-oxide-semiconductor drain electrode
Terminal electrically connects, the measurement circuitry end ground connection of described first metal-oxide-semiconductor drain electrode.
Above-mentioned many SITE parallel test method, wherein, the described pair of MOSFET product also includes first switch, second opens
Close, the 3rd switch, the 4th switch and the 5th switch；
The measurement circuitry end of described first metal-oxide-semiconductor grid swashing by described first switch and described first metal-oxide-semiconductor source class
Encourage line scan pickup coil side electrical connection；
Swashing of described second switch and described second metal-oxide-semiconductor grid is passed through at the measurement circuitry end of described first metal-oxide-semiconductor source class
Encourage line scan pickup coil side electrical connection；
The measurement circuitry end of described second metal-oxide-semiconductor grid switchs sharp with described second metal-oxide-semiconductor source class by the described 3rd
Encourage line scan pickup coil side electrical connection；
Described 4th switch and swashing that described second metal-oxide-semiconductor drains are passed through in the measurement circuitry end of described second metal-oxide-semiconductor source class
Encourage line scan pickup coil side electrical connection；
Described 5th switch ground connection is passed through at the measurement circuitry end of described first metal-oxide-semiconductor drain electrode.
Above-mentioned many SITE parallel test method, wherein, first switch, second switch, the 3rd switch, the 4th switch and the
Five switches are the relay of DPDT.
In sum, due to present invention employs above technical scheme, parallel by many SITE are carried out to MOSFET product
Test design, and using the drain electrode of MOSFET as the reference ground of test circuit, ensureing the survey that MOSFET product is carried out with routine
Moreover it is possible to MOSFET product be carried out with the test of the contact situation between product and test arm, to avoid on the basis of examination project
Because contact problems lead to test to damage of product.
Brief description
Fig. 1 is the schematic diagram carrying out many SITE concurrent testing in one embodiment of the invention；
Fig. 2 is the circuit diagram carrying out the contact situation test between MOS product and test arm in one embodiment of the invention；
Fig. 3-5 is the circuit diagram carrying out many SITE concurrent testing in one embodiment of the invention.
Specific embodiment
In conjunction with specific examples below and accompanying drawing, the present invention is described in further detail.The process of the enforcement present invention,
Condition, method of testing, circuit etc., in addition to the following content specially referring to, remaining is the universal knowledege of this area and known
General knowledge, the present invention is not particularly limited content.
Fig. 1 is the schematic diagram carrying out many SITE concurrent testing in one embodiment of the invention；As shown in figure 1, a kind of many SITE
Parallel test method, is applied on double MOSFET products, including：
First, some MOS products to be measured are provided, in the present embodiment double MOSFET products of preferred two SITE, and
Test parameter according to above-mentioned double MOSFET products（Can be different according to the demand of test, in actual production test
Cheng Zhong, user can provide the number such as the testing requirement of this product and the performance parameter of corresponding product while providing test product
According to）With MOSFET test philosophy, design and prepare test load plate（load board）With user test card（DUTCARD）.
Secondly, according to MOSFET test specification, in tester table（As MS7000 test machine etc.）Upper setting test event is such as
Double MOSFET and test arm（Handler）Between contact situation test（CONT）, double MOSFET product work when startup
Voltage tester（VTH）, double MOSFET products grid source electrode between electric leakage current test（IGSS）, the hourglass source electrode of double MOSFET products
Between electric leakage current test（IDSS）, double MOSFET product works conducting resistance test（RDSON）With double MOSFET products
The forward voltage drop test of diode between hourglass source electrode（VFSD）Deng.
Finally, above-mentioned tester table is produced to double MOSFET of two SITE using test load plate and user test card
Product carry out each above-mentioned test event simultaneously successively, and utilize transistor-transistor logic circuit（TTL communicates）By above-mentioned couple of MOSFET
The test signal of product feeds back on tester table；Joining according to tester table software and hardware is needed in carrying out above-mentioned testing procedure
Put, realize the concurrent testing of the double MOSFET products of double SITE by way of group, and then reach and put forward efficient purpose.
Wherein, in order to avoid be likely to occur some double MOSFET products survey RDSON this when test risk occurs,
Need, by increasing the methods such as DGS, the drain electrode of double MOSFET products is set to source reference point（The i.e. drain electrode of double MOSFET products
Section is connected with AGND）, and then avoid the appearance of the problems referred to above.
Further, by way of switching relay on DUTCARD, it is possible to achieve product source drain and equipment sources
Switching and ground between, so that energy flexible Application during test, meets the different test request of client.
Further, when carrying out CONT test event, by the excitation line terminal of the grid in double MOSFET products even
Connect an external impressed current source（As provided external impressed current source of 0.1mA electric current etc.）, and the grid source class leakage by this pair of MOSFET product
Pole is electrically connected to form the loop of a survey grid voltage, to carry out double MOSFET products and test arm（handler）Between connect
Tactile situation test（CONT）.
Fig. 2 is the circuit diagram carrying out the contact situation test between MOS product and test arm in one embodiment of the invention；
As shown in Fig. 2 the above-mentioned grid source class drain electrode by this pair of MOSFET product is electrically connected to form the loop of a survey grid voltage
In circuit, double MOSFET products include the first metal-oxide-semiconductor Q1 and the second metal-oxide-semiconductor Q2, specially：
External impressed current source OVI and excitation line terminal GF of the first metal-oxide-semiconductor Q1 grid G（G force）Electrical connection, outer to provide
Connect electric current；The measurement circuitry end GS of the first metal-oxide-semiconductor Q1 grid G（G sense）By first switch K1 and the first metal-oxide-semiconductor Q1 source class
The excitation line terminal SF electrical connection of S, the measurement circuitry end SS of the first metal-oxide-semiconductor Q1 source class S passes through second switch K2 and the second metal-oxide-semiconductor
The excitation line terminal GF electrical connection of Q2 grid G, the measurement circuitry end GS of the second metal-oxide-semiconductor Q2 grid G is by the 3rd switch K3 and the
The excitation line terminal SF electrical connection of two metal-oxide-semiconductor Q2 source class S, the measurement circuitry end SS of the second metal-oxide-semiconductor Q2 source class S passes through the 4th and switchs
K4 is electrically connected with excitation line terminal DF of the second metal-oxide-semiconductor Q2 drain D, the measurement circuitry end DS and first of the second metal-oxide-semiconductor Q2 drain D
The excitation line terminal DF electrical connection of metal-oxide-semiconductor Q1 drain D, the measurement circuitry end DS of the first metal-oxide-semiconductor Q1 drain D is by the 5th switch K5
Ground connection（AGND）.
Further, above-mentioned first switch K1, second switch K2, the 3rd switch K3, the 4th switch K4 and the 5th switch
K5 is the relay of DPDT（Rerlay-DPDT）, and each above-mentioned relay is all by its pin 1 and pin 4
It is connected in above-mentioned circuit, the pin 4 of such as first switch K1 is connected with the measurement circuitry end GS of the first metal-oxide-semiconductor grid Q1,
Pin 1 is connected with excitation line terminal SF of the first metal-oxide-semiconductor source class Q1, and the connected mode of other relays and first switch K1
Connected mode is identical, and here is not repeated.
Fig. 3-5 is the circuit diagram carrying out many SITE concurrent testing in one embodiment of the invention；Above-mentioned DUTCARD can also be real
Existing switching between product source drain and equipment sources and ground, so that energy flexible Application during test, meets the different test of client
Require；As in Figure 3-5, a circuit SITE tested includes：
Said one SITE includes first couple of MOSFET pipe M1 and second couple of MOSFET pipe M2, and this first pair of MOSFET pipe
M1 and second couple of MOSFET pipe M2 passes through multiple relays（As KC7-10,21,23-35 etc.）Constitute a double SITE concurrent testing
Circuit；Wherein, the circuit of another SITE in this test circuit connects, here identical with the circuit connection shown in Fig. 3-5
It is not repeated.
Specifically, referring to shown in Fig. 3-5, when carrying out above-mentioned CONT test event, need to close continuing shown in Fig. 3
Electrical equipment KC7, KC8 and KC9；When carrying out VTH test event, then by the relay KC2A shown in Fig. 4-5, KC5A, KC23A,
KC24A, KC25A, KC26A, KC27A, KC28A, KC29A and KC30A close；When carrying out RDSON test event, then by Fig. 4-
Relay KC23A, KC24A, KC25A, KC27A, KC28A, KC29A, KC30A and KC32A closure shown in 5 is it is also possible to only
Relay KC23A, KC24A, KC25A, KC27A, KC28A, KC29A and KC30A are closed；Carrying out BVdss（Source and drain breakdown potential
Pressure）During test event, then by the relay KC1A shown in Fig. 4-5, KC4A, KC23A, KC24A, KC25A, KC26A, KC27A,
KC28A, KC29A and KC30A close；When carrying out IGSS test event, then by the relay KC3A shown in Fig. 4-5, KC6A,
KC23A, KC24A, KC25A, KC26A, KC27A, KC28A, KC29A and KC30A close；When carrying out IDSS test event, then
By relay KC1A, KC4A, KC23A, KC24A, KC25A, KC26A, KC27A, KC28A, the KC29A shown in Fig. 4-5 and
KC30A closes.
Further, by the switching of each above-mentioned relay, realize such as CONT, RDSON, VTH, IGSS etc. are tested
The test of project.
In sum, due to present invention employs above technical scheme, parallel by many SITE are carried out to MOSFET product
Test design, and using the drain electrode of MOSFET as the reference ground of test circuit, ensureing the survey that MOSFET product is carried out with routine
Moreover it is possible to MOSFET product be carried out with the test of the contact situation between product and test arm, to avoid on the basis of examination project
Because contact problems lead to test to damage of product.
The protection content of the present invention is not limited to above example.Under the spirit and scope without departing substantially from invention, this area
Technical staff it is conceivable that change and advantage be all included in the present invention, and with appending claims for protect model
Enclose.
Claims (6)
1. a kind of many SITE parallel test method, is applied on MOS product to be measured it is characterised in that methods described includes：
Some MOS products to be measured are provided；
Test parameter preparation test load plate according to described MOS product to be measured and user test card；
Test event is set on tester table according to testing requirement；
Described tester table utilize described test load plate and described user test card same to some described MOS products to be measured
The test of test event described in Shi Jinhang；
Wherein, carry out described test event test when MOS product to be measured drain electrode be connected with AGND；
Described test event includes the contact situation test between described MOS product to be measured and test arm, by treating described
The excitation line terminal surveying the grid of MOS product connects an external impressed current source, and the grid source class drain electrode by described MOS product to be measured
It is electrically connected to form the loop of a survey grid voltage, to carry out the contact feelings between described MOS product to be measured and described test arm
Condition is tested；
Described MOS product to be measured is double MOSFET product, and described pair of MOSFET product includes the first metal-oxide-semiconductor and the second metal-oxide-semiconductor；
When carrying out the contact situation test between described pair of MOSFET product and described test arm, its test circuit includes：
Described external impressed current source is electrically connected with the excitation line terminal of described first metal-oxide-semiconductor grid, the survey of described first metal-oxide-semiconductor grid
Amount line scan pickup coil side electrically connect with the excitation line terminal of described first metal-oxide-semiconductor source class, the measurement circuitry end of described first metal-oxide-semiconductor source class and
The excitation line terminal electrical connection of described second metal-oxide-semiconductor grid, the measurement circuitry end and described second of described second metal-oxide-semiconductor grid
The excitation line terminal electrical connection of metal-oxide-semiconductor source class, the measurement circuitry end of described second metal-oxide-semiconductor source class and described second metal-oxide-semiconductor drain electrode
Excitation line terminal electrical connection, described second metal-oxide-semiconductor drain electrode measurement circuitry end with described first metal-oxide-semiconductor drain electrode excitation wires
End electrical connection, the measurement circuitry end ground connection of described first metal-oxide-semiconductor drain electrode.
2. as claimed in claim 1 many SITE parallel test method it is characterised in that methods described also includes：Using crystal
Pipe logic circuit feeds back to the test signal of described MOS product to be measured on described tester table.
3. as claimed in claim 1 many SITE parallel test method it is characterised in that described test event also includes product work
Start voltage tester, the electric leakage current test between grid source electrode, the electric leakage current test between hourglass source electrode, the leading of chip operation when making
The forward voltage drop test of diode between logical resistance test and hourglass source electrode.
4. as claimed in claim 1 many SITE parallel test method it is characterised in that described external impressed current source provide 0.1mA
Electric current.
5. as claimed in claim 1 many SITE parallel test method it is characterised in that described pair of MOSFET product also includes
One switch, second switch, the 3rd switch, the 4th switch and the 5th switch；
The measurement circuitry end of described first metal-oxide-semiconductor grid is by the excitation line of described first switch and described first metal-oxide-semiconductor source class
Terminal electrically connects；
The measurement circuitry end of described first metal-oxide-semiconductor source class is by the excitation line of described second switch and described second metal-oxide-semiconductor grid
Terminal electrically connects；
The measurement circuitry end of described second metal-oxide-semiconductor grid is by the excitation line of the described 3rd switch and described second metal-oxide-semiconductor source class
Terminal electrically connects；
The measurement circuitry end of described second metal-oxide-semiconductor source class is by the excitation line of the described 4th switch and described second metal-oxide-semiconductor drain electrode
Terminal electrically connects；
Described 5th switch ground connection is passed through at the measurement circuitry end of described first metal-oxide-semiconductor drain electrode.
6. as claimed in claim 5 many SITE parallel test method it is characterised in that first switch, second switch, the 3rd opening
Close, the 4th switch and the 5th switchs the relay being DPDT.
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| CN107908507B (en) * | 2017-10-10 | 2021-07-02 | 芯海科技（深圳）股份有限公司 | double-CPU multichannel FT (FT) mass production test system and method |
| CN108344936B (en) * | 2018-01-22 | 2020-05-08 | 无锡昌德微电子股份有限公司 | Test method of power semiconductor device |
| CN108732480B (en) * | 2018-05-24 | 2020-07-10 | 江苏矽导集成科技有限公司 | Automatic sorting circuit and automatic sorting method based on parallel use of SiC MOSFET devices |
| CN112201588B (en) * | 2020-10-12 | 2021-08-17 | 南京宏泰半导体科技有限公司 | Method for solving problem of incapability of multi-site concurrent testing under condition of common substrate in wafer test |
| CN112444730A (en) * | 2020-10-15 | 2021-03-05 | 绍兴网策科技有限公司 | Fool-proof method for multi-Site mode testing device and fool-proof method for testing machine |
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Effective date of registration: 20200526 Address after: 210000 24 / F, block B, Kechuang headquarters building, Kechuang Plaza, No. 320, pubin Avenue, Jiangpu street, Pukou District, Nanjing City, Jiangsu Province Patentee after: Nanjing Hongtai Semiconductor Technology Co.,Ltd. Address before: 200001, room 604, B District, No. 666, Huangpu District, Shanghai, Beijing East Road Patentee before: SHANGHAI MACROTEST SEMICONDUCTOR Inc. |
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| CP03 | Change of name, title or address |
Address after: 210000 floor 2, building 26, South Park, Jiangsu Kecheng science and Technology Industrial Park, No. 19, Lanhua Road, Pukou District, Nanjing, Jiangsu Province Patentee after: Nanjing Hongtai Semiconductor Technology Co.,Ltd. Address before: 24/F, Block B, Science and Technology Innovation Headquarters Building, No. 320, Pubin Avenue, Jiangpu Street, Pukou District, Nanjing City, Jiangsu Province, 210000 Patentee before: Nanjing Hongtai Semiconductor Technology Co.,Ltd. |