CN105470240B - The test circuit and method of silicon hole group in silicon hole and three dimensional integrated circuits - Google Patents
The test circuit and method of silicon hole group in silicon hole and three dimensional integrated circuits Download PDFInfo
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- CN105470240B CN105470240B CN201510817569.1A CN201510817569A CN105470240B CN 105470240 B CN105470240 B CN 105470240B CN 201510817569 A CN201510817569 A CN 201510817569A CN 105470240 B CN105470240 B CN 105470240B
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Abstract
This application involves the test circuit and method of silicon hole group in silicon hole and three dimensional integrated circuits, including：Driving source, it is connected with the input terminal of TSV, for providing pumping signal；Two circuit branch in parallel, it is connected with the output terminal of TSV, wherein a circuit branch includes inverter device, another circuit branch includes level triggers device and switching device, and switching device is used for the break-make for controlling circuit branch residing for level triggers device；Tertiary circuit branch, it is connected with the output terminal of two circuit branch in parallel, for the state that is turned on or off being currently at according to circuit branch, exports accordingly；Detection circuit branch, the signal for the output according to tertiary circuit branch show, and determine that TSV whether there is open circuit defect or circuit defect.The application is showed by analyzing the signal of two circuit branch output terminals, and to judge TSV defects, open circuit defect and circuit defect test can be covered using same set of test circuit by realizing.
Description
Technical field
This application involves ic test technique field, and in particular to the test of silicon hole in a kind of three dimensional integrated circuits
Method and test circuit.
Background technology
Silicon hole (TSV, Through Silicon Via) is realize three-dimensional (3D) integrated circuit interlayer interconnection a kind of group
Part, as shown in (a) of Fig. 1, TSV is usually made of metallic conductor and insulating protective layer.TSV is directly longitudinally worn in silicon materials
Cross, circuit of the connection on different layers, greatly reduce the interlayer interconnection length of three dimensional integrated circuits, so as to effectively improve
Circuit performance.
It is difficult to exempt from that some physical imperfections can be introduced in TSV manufacturing processes.The TSV defects of current industry common concern are main
Including open circuit defect and circuit defect, as shown in (a) and (b) of Fig. 1.Open circuit defect shown in (b) is mainly due to TSV in Fig. 1
Cavity, crackle in metallic conductor etc. are caused, and the main electricity of these defects shows as the increase of TSV resistance values, is even led when serious
Cause TSV open circuits.It is pin hole in TSV insulating layers, impurity etc. the main reason for circuit defect shown in (c) in Fig. 1, these defects
The leakage current that important electrical shows as TSV to substrate increases, and direct short-circuit between TSV and substrate is even resulted in when serious.
Since TSV is most important for reliable product manufacturing, in order to tackle TSV mass defects, there is an urgent need for strengthen
The research of TSV test methods.
The content of the invention
The main purpose of the application is to provide a kind of TSV testing schemes, opens a way for covering TSV in three dimensional integrated circuits
Defect and circuit defect.
According to the application's in a first aspect, the embodiment of the present application provides a kind of test circuit of silicon hole, including：
Driving source, it is connected with the input terminal of the silicon hole, for providing excitation pulse signal for the silicon hole；
Two circuit branch in parallel, it is connected with the output terminal of the silicon hole, wherein a circuit branch is included instead
Phase device, another circuit branch include level triggers device and switching device, and the switching device is used to control the level to touch
Send out the break-make of another circuit branch residing for device；
Tertiary circuit branch, it is connected with the output terminal of two circuit branch in parallel, for according to described another
State that what one circuit branch was currently at be turned on or off, exports accordingly；
Detection circuit branch, it is connected with the output terminal of the tertiary circuit branch, for according to the tertiary circuit
The signal performance of the output of branch, determines that the silicon hole whether there is open circuit defect or circuit defect.
In one embodiment, the detection circuit branch includes：
The first JK flip-flop being made of the first NAND gate and the second NAND gate, wherein the output of first NAND gate is
One input of second NAND gate, another input of second NAND gate are the output of the tertiary circuit branch,
The output of second NAND gate is an input of first NAND gate, another input of first NAND gate is warp
Cross the reset signal of NOT gate；
The second JK flip-flop being made of the first nor gate and the second nor gate, wherein the output of first nor gate is
One of second nor gate input, another input of second nor gate are reset signal, second nor gate
Output be one of first nor gate input, another input of first nor gate is the tertiary circuit branch
Output；
Nor gate, an input of the nor gate is the output of first JK flip-flop, another input is described
The output of second JK flip-flop, the nor gate export testing result.
In another embodiment, the tertiary circuit branch includes AND gate circuit；It is anti-that the inverter device includes high threshold
Phase device；The level triggers device realizes that the switching device is partly led including P-channel metal oxide using Schmidt trigger
Body field-effect transistor.
According to the second aspect of the application, the embodiment of the present application provides a kind of test method of silicon hole, including：
To the input terminal input stimulus pulse signal of the silicon hole；
The output terminal that two circuit branch in parallel are connected to the silicon hole is provided, wherein a circuit branch is including anti-phase
Device, another circuit branch include level triggers device and switching device, and the switching device controls the level triggers device
The break-make of residing another circuit branch；
The output terminal that tertiary circuit branch is connected to two circuit branch in parallel, the tertiary circuit branch are provided
The state that is turned on or off being currently at according to another circuit branch, exports accordingly；
The output terminal that detection circuit branch is connected to the tertiary circuit branch is provided, the detection circuit branch is according to institute
The signal performance of the output of tertiary circuit branch is stated, determines that the silicon hole whether there is open circuit defect or circuit defect.
According to the third aspect of the application, the embodiment of the present application provides a kind of test of silicon hole group in three dimensional integrated circuits
Circuit, including：
The test circuit of silicon hole as described above corresponding with each silicon hole in the silicon hole group, wherein, institute
The driving source for stating each silicon hole in silicon hole group is same or different, the corresponding detection electricity of each silicon hole
Road branch is same or different in the silicon hole group；
The driving source is serially connected with the corresponding multi-selection device of each silicon hole, the multi-selection device in the silicon hole group
Between the input terminal of corresponding silicon hole, for controlling corresponding silicon hole to enter test pattern or normal mode, when described
Multi-selection device controls corresponding silicon hole to enter test pattern, and the input of the corresponding silicon hole is believed for the output of the driving source
Number, when the multi-selection device controls corresponding silicon hole to enter normal mode, the input of the corresponding silicon hole is normal function
Signal；
Switch block corresponding with each silicon hole in the silicon hole group, the switch block are arranged at corresponding silicon
The output terminal of the tertiary circuit branch of the test circuit of through hole, for controlling corresponding silicon hole to enter test when the multi-selection device
Pattern, connects the switch block to obtain the test of corresponding silicon hole output.
According to the fourth aspect of the application, the embodiment of the present application provides a kind of test of silicon hole group in three dimensional integrated circuits
Method, is tested using the test circuit of silicon hole group in three dimensional integrated circuits as described above, to determine the silicon hole
Each silicon hole whether there is open circuit defect or circuit defect in group.
Output signal of the pumping signal after TSV is applied to discrepant two circuits of tool by the embodiment of the present application at the same time
Branch, is showed by the signal for analyzing two circuit branch output terminals, to judge TSV defects, so as to fulfill same set of survey is used
Examination circuit can cover open circuit defect and circuit defect test, suitable for before the binding of TSV and bind latter two stage test,
And then provide feasible automatic test approach to improve the yield rate of 3D integrated circuits.
Brief description of the drawings
Fig. 1 schematically shows TSV and its open circuit defect and circuit defect；
Fig. 2 schematically shows TSV circuit models and its open circuit defect circuit model and circuit defect circuit model；
Fig. 3 diagrammatically illustrates the block diagram of the single TSV test circuits of one embodiment of the application；
Fig. 4 diagrammatically illustrates a specific implementation circuit of embodiment illustrated in fig. 3；
Fig. 5 diagrammatically illustrate phase inverter path waveform, Schmitt trigger circuit waveform and with gate output terminal waveform；
Fig. 6 diagrammatically illustrates embodiment illustrated in fig. 3 and breaks the circuit defect test carried out during second circuit branch；
Fig. 7 diagrammatically illustrates the test circuit of TSV groups in the 3D integrated circuits of one embodiment of the application；
Fig. 8 diagrammatically illustrates the detection circuit branch involved in the embodiment of the present application；
Fig. 9 is diagrammatically illustrated under (a) TSV normal conditions and there are high threshold phase inverter during open circuit defect in (b) TSV
The simulation result of input/output signal change；
Figure 10 diagrammatically illustrates the emulation of relation between pulse width, TSV signals rise/fall time and offresistance
As a result；
Figure 11 diagrammatically illustrates TSV circuit defects test input/output signal simulated effect；
Figure 12 diagrammatically illustrates the relation between TSV output voltages and TSV short-circuit resistances；
(a) of Figure 13 diagrammatically illustrates the output signal for the JK flip-flop realized using NAND gate, and (b) is schematically shown
The output signal for the JK flip-flop realized using nor gate；
Figure 14 diagrammatically illustrates test accuracy and changes with NMOS tube width.
Embodiment
The characteristics of due to three dimensional integrated circuits technical process, the test of TSV need to be divided into (pre-bond) before binding and tie up
(post-bond) two stages carry out after fixed.In pre-bond test phases, TSV is usually blind hole form, and TSV usually can be with
Test probe contact is carried out, can also be aided in using some design for Measurability schemes.And in post-bond stages, the layer of chip
Between stacked interconnected completed, TSV has been embedded in stacked body, plays interlayer interconnection effect.At this time, the probe contact of TSV becomes
Must be very difficult, even may.
As shown in Fig. 2, wherein (a), (b), (c) respectively illustrate the circuit mould of TSV and its open circuit defect and circuit defect
Type schematic diagram.
As shown in (b) of Fig. 2, when open circuit defect is tested, to TSV input pulse signals.Due to the parasitic RC parameters in TSV
Very little, rising and falling time when signal is through TSV also very little.But if there are open circuit defect, the resistance increase of TSV, letter in TSV
Rising and falling time during number through TSV can also increase therewith, nonetheless, the signal rising and falling time of TSV output terminals
Still very little, it is difficult to directly measure., can be by elongating the signals of TSV output terminals in this regard, one of design philosophy of the application is
Rising and falling time, in order to measure and differentiate.
According to TSV circuit defects circuit model (i.e. c in Fig. 2), when circuit defect is more serious in TSV, short-circuit resistance
RshortSmaller, the level of TSV output terminals is determined by equation below (1).
Wherein, Vout_of_TSVAnd VIN_of_TSVThe respectively voltage of TSV output terminals and input terminal, R1 are the bulk resistor of TSV.
Analysis based on above-mentioned open-circuit defective circuits model and circuit defect circuit model, the core concept of the application
It is, using dual path testing scheme, output signal of the pumping signal after TSV to be applied to discrepant two roads of tool at the same time
In footpath, the signal by analyzing two path outputs is showed to judge TSV defects.So as to which the TSV testing schemes of the application can
For covering TSV open circuit defects and circuit defect, the TSV that the program can be used for pre-bond the and post-bond stages is surveyed
Examination scheme, in addition, the program can also have preferable low power consumption characteristic.
For the purpose, technical scheme and advantage of the application are more clearly understood, by specific embodiment and will tie below
Refer to the attached drawing is closed to be described further the application.For convenience of description, test of the application first to single TSV provides accordingly
Testing scheme, then, since 3D integrated circuits include multiple TSV (herein referred as TSV groups), individually test TSV be it is difficult and
It is time-consuming, therefore whether the application then provides a kind of while tests multiple TSV and open a way or the test circuit of short circuit again, from
And realize the test to silicon hole group in 3D integrated circuits.
As described in Figure 3, for one embodiment of the application TSV test circuits block diagram representation, wherein, driving source and TSV
Input terminal be connected, for providing pumping signal for TSV, the output terminal of TSV is connected to the first circuit branch and the of parallel connection
Two circuit branch, the first circuit branch include inverter device, and second circuit branch includes level triggers device and for controlling electricity
The switching device of the break-make of the second circuit branch residing for flat triggering device, the first circuit branch and second circuit branch in parallel
The output terminal on road is connected to tertiary circuit branch, which leads on-off according to what second circuit branch was currently at
Open state, exports accordingly, which is sent to detection circuit branch, by detection circuit branch according to tertiary circuit branch
Output signal performance, determine that TSV whether there is open circuit defect or circuit defect.When second circuit branch is currently at conducting
During state, the pulse width of the output terminal of tertiary circuit branch be the output terminal of TSV signal delay with the first and second two
The summation of the delay difference of the output of circuit branch, detection circuit branch judge the pulse width of the output terminal of tertiary circuit branch with
The pulse width of the input terminal of TSV whether in the reasonable scope, if in the reasonable scope, open circuit defect is not present in TSV, such as
Fruit exceeds zone of reasonableness, then there are open circuit defect by TSV；When second circuit branch is currently at off-state, the output terminal of TSV
Only exported by the inverter device of the first circuit branch to the input terminal of tertiary circuit branch, detection circuit branch judges the 3rd electricity
The level of the output terminal of road branch and the input terminal of TSV whether on the contrary, if on the contrary, if TSV circuit defect is not present, if phase
Together, then there are circuit defect by TSV.This is because in the case of there are circuit defect, since electric leakage increase causes TSV output terminals
Voltage declines, and when not reaching phase inverter threshold voltage, phase inverter does not work, i.e. the output of phase inverter is not anti-phase.
In embodiment illustrated in fig. 3 one in the specific implementation, tertiary circuit branch is AND gate circuit；First circuit branch it is anti-
Phase device is high threshold phase inverter；The level triggers device of second circuit branch is Schmidt trigger, and switching device is P-channel
Mos field effect transistor (i.e. PMOS tube).At this time, the test circuit to single TSV is as shown in figure 4, input
TSV output terminals are connected on two paths by pumping signal at the same time to TSV input terminals.It is anti-phase that high threshold is concatenated on one path
Device, Schmidt trigger is concatenated on a path and and connects metal-oxide-semiconductor.The output terminal in two paths is defeated with door respectively as one
Enter.TSV tests can be being carried out with gate output terminal using pulse-detecting circuit.
As shown in figure 4, when controlling PMOS tube connection Schmidt trigger path, in the pulse that the output with door observes
Width is the summation of TSV rising and falling times and two paths of signals difference in pulse width, can be represented by equation below (2).
TOUT_of_AND=TOUT_of_TSV+TST–TINV (2)
Wherein, TOUT_of_TSVTo be tested the signal edge of TSV output terminals, TSTFor the delay of Schmidt trigger, TINVIt is high threshold
The delay of value phase inverter, and TOUT_of_ANDFor the pulse width with gate output terminal.As it can be seen that the effect of embodiment illustrated in fig. 4 is suitable
In the rising and falling time for having elongated signal, easy to measure and differentiate.
The threshold voltage of high threshold phase inverter is higher, and output signal only can just be jumped when input signal reaches threshold voltage
Become.Ideally, output signal pulses width is equal to pulse width when incoming signal level is VDD.Phase inverter threshold value
Voltage is higher, and output signal pulses width is more similar to the pulse width that input signal reaches VDD.
Schmidt trigger is higher for the signal threshold value voltage of rising, relatively low for the signal threshold value voltage of decline.Reason
In the case of thinking, output signal pulses width is equal to the pulse width that incoming signal level is VDD and adds fall time.Schmidt touches
The threshold voltage for sending out device and high threshold phase inverter may be different.If the threshold voltage of Schmidt trigger is higher, can increase
Output pulse width, strengthens amplification effect；Conversely, a less pulse width may be produced.Ideally, it is defeated with door
Go out delay difference of the rise/fall time plus two paths that signal pulse width exports signal for TSV.Phase inverter path ripple
Shape, Schmitt trigger circuit waveform and with gate output terminal waveform respectively as shown in (a) in Fig. 5, (b), (c).
When circuit defect is tested, by controlling the signal of PMOS tube to disconnect Schmidt trigger path, TSV output letters
Number only pass through high threshold phase inverter path to export.As shown in Figure 6.It has been observed that when circuit defect is more serious, short-circuit resistance Rshort
Smaller, the level of TSV output terminals is determined by above-mentioned formula (1).Under this arrangement, due to high threshold phase inverter threshold voltage compared with
Height, if the voltage of TSV output pulses reaches threshold voltage, phase inverter output just has pulse signal, and otherwise output keeps high electricity
It is flat constant.
Based on the test circuit of above-mentioned single TSV, another embodiment of the application is additionally provided using the test circuit to list
The method that a TSV is tested, including：
To the input terminal input signal of TSV；
The output terminal that two circuit branch in parallel are connected to TSV is provided, wherein a circuit branch includes inverter device, separately
One circuit branch includes level triggers device and switching device, the circuit branch residing for switching device control level triggers device
Break-make；
The output terminal that tertiary circuit branch is connected to two circuit branch of the parallel connection is provided, tertiary circuit branch is according to electricity
The state that is turned on or off that circuit branch residing for flat triggering device is currently at, exports accordingly；
The output terminal that detection circuit branch is connected to tertiary circuit branch is provided, detection circuit branch is according to tertiary circuit branch
The signal performance of the output on road, determines that TSV whether there is open circuit defect or circuit defect.
The associated description for each step that the above method is related to may be referred to the related content in foregoing test circuit, herein not
Repeat.
In addition, the test circuit based on above-mentioned single TSV, one embodiment of the application is provided in 3D integrated circuits
The test circuit of TSV groups, it includes：It is multiple foregoing test circuits for single TSV, corresponding with each TSV in TSV groups
The multi-selection device being serially connected between driving source and the input terminal of corresponding TSV and be arranged at corresponding silicon hole test electricity
The switch block of the output terminal of the tertiary circuit branch on road.Wherein, multi-selection device be used for control corresponding TSV enter test pattern or
Normal mode, when multi-selection device controls corresponding silicon hole to enter test pattern, the input of the corresponding silicon hole is the excitation
The output signal in source, corresponding switch block connection at this time is exported with obtaining the test of corresponding silicon hole, when multi-selection device controls
Corresponding silicon hole enters normal mode, and the input of the corresponding silicon hole is normal function signal.
One in the specific implementation, the test circuit of TSV groups is as shown in Figure 7 in the 3D integrated circuits of the present embodiment.Shown in Fig. 7
It is that 4 TSV are shown by way of example, it should be appreciated that the quantity of TSV can be in TSV groups in the 3D integrated circuits of the present embodiment
Arbitrarily, the quantity adaptability of corresponding other components changes correspondingly.One group of TSV shares an exciting signal source and an inspection
Slowdown monitoring circuit branch.Exciting signal source can use oscillator or other circuits, and detection circuit branch can use the pulse for example shown in Fig. 8 to examine
Slowdown monitoring circuit is realized.In the input terminal increase alternative multi-selection device (Multiplexer) of each TSV, controlled by signal T.Work as T signal
For 1 when, into test pattern, the input signal of TSV is the output of signal source circuit.As T=0, in normal mode, TSV
Signal be normal function signal.Switched each with the increase of the output terminal of door, switch controlling signal uses S1~S4 tables in the figure 7
Show.When needing to test TSVi, Si can be connected and switch and close other switches, obtain the test output of TSVi.
Pulse-detecting circuit in the present embodiment is as shown in figure 8, the circuit is made of two JK flip-flops.Specifically, arteries and veins
Rushing detection circuit includes：The first JK flip-flop being made of the first NAND gate and the second NAND gate, wherein the first NAND gate is defeated
Go out for one of the second NAND gate input, another input of the second NAND gate for tertiary circuit branch output, second with it is non-
The output of door is an input of the first NAND gate, another input of the first NAND gate is the reset signal RST by NOT gate；
The second JK flip-flop being made of the first nor gate and the second nor gate, wherein the output of the first nor gate is the second nor gate
One input, another input of the second nor gate is reset signal, and the output of the second nor gate is one of the first nor gate
Input, another input of the first nor gate are the output of tertiary circuit branch；And nor gate, wherein the one of nor gate are defeated
It is the output of the second JK flip-flop to enter for the output of the first JK flip-flop, another input, and nor gate exports testing result.Such as figure
Shown in 8, the test result signal of TSV is inputted by IN, and testing result is exported by OUT.The function of pulse-detecting circuit can be by table 1 below
Explanation.
The function of 1 pulse-detecting circuit of table
As it can be seen from table 1 the pulse-detecting circuit being made of gate circuit can be used for realizing when reset signal is in height
During level, low level is exported, when reset signal is from high level saltus step to low level, low level is exported, when reset signal is in
During low level, export as from low transition to high level.
Based on the test circuit of TSV groups in above-mentioned 3D integrated circuits, another embodiment of the application, which additionally provides, uses the 3D
Method of the test circuit of TSV groups to being tested in integrated circuit, to determine that each TSV is with the presence or absence of open circuit in TSV groups
Defect or circuit defect.
The effect of the TSV testing schemes using the application is provided below by specific experiment.
Tested for TSV open circuit defects, Fig. 9 gives the emulation knot of the input/output signal change of high threshold phase inverter
Fruit.Simulated conditions are as follows：It is 2m Ω to take normal TSV resistance, and capacitance 242fF, a diameter of 30 microns, thickness is 1 micron, height
For 75 microns.Open circuit defect resistance RopenTake 500 ohm.It is 1ns in the TSV input terminals application cycle, width is the pulse of 500ps
Signal.
Fig. 9 shows that when TSV is normal, input-output wave shape almost overlaps, as shown in (a) of Fig. 9.Opened when existing in TSV
During the defect of road, there is ps grades of deviation in the rising edge and trailing edge of the input-output wave shape of TSV, as shown in (b) of Fig. 9.
Figure 10 is the relation analogous diagram between gate output terminal pulse width, TSV rise/fall times and offresistance.
Simulated conditions are as follows.Using TSMC 180nm technology libraries.The resistance value of offresistance is to take 0 Ω, 100 Ω, 300 Ω, 500 respectively
Ω、550Ω、600Ω、650Ω、700Ω、750Ω、800Ω、1kΩ、2kΩ。
Being tested for TSV circuit defects, Figure 11 is the simulated effect when test of TSV circuit defects is carried out using the application,
Wherein (a) and (b) respectively illustrate no circuit defect and have the simulated effect of the TSV of circuit defect.Simulated conditions are as follows：Without reason
The Rshort (i.e. TSV short-circuit resistances) of barrier TSV takes 1M Ω, and the Rshort with open defect TSV takes 1m Ω.Applied in TSV input terminals
It is 1ns to add the cycle, and width is the pulse signal of 500ps.
Figure 11 shows that, since partial pressure acts on, the output voltage of the TSV with circuit defect is decreased obviously, and can be down to high threshold
Below the threshold voltage of phase inverter.
Figure 12 furthermore present the relation between TSV output voltages and Rshort.As shown in Figure 11, TSV output voltages
It is increased monotonically with the increase of Rshort resistance, it is the good symptom of TSV circuit defects to illustrate TSV output voltages.
Figure 13 and Figure 14 illustrates the simulation result using pulse-detecting circuit, and wherein (a) of Figure 13 is using NAND gate
The output signal of the JK flip-flop of realization, (b) are the output signal for the JK flip-flop realized using nor gate, and Figure 14 shows survey
The schematic diagram that examination accuracy changes with NMOS tube width.
Experiment display above, using the TSV test circuits of the application, can cover open circuit defect, circuit defect and TSV two
End connection defect, and realizes on-line testing, the TSV test circuits and method of the application be applicable to TSV pre-bond and
Two stages of post-bond, and there is preferable low power consumption characteristic.
Above content is to combine specific embodiment further description made for the present invention, it is impossible to assert this hair
Bright specific implementation is confined to these explanations.For general technical staff of the technical field of the invention, do not taking off
On the premise of from present inventive concept, some simple deduction or replace can also be made.
Claims (9)
- A kind of 1. test circuit of silicon hole, it is characterised in that including：Driving source, it is connected with the input terminal of the silicon hole, for providing excitation pulse signal for the silicon hole；Two circuit branch in parallel, it is connected with the output terminal of the silicon hole, wherein a circuit branch includes phase inverter Part, another circuit branch include level triggers device and switching device, and the switching device is used to control the level trigger The break-make of another circuit branch residing for part；Tertiary circuit branch, it is connected with the output terminal of two circuit branch in parallel, for according to another electricity State that what road branch was currently at be turned on or off, exports accordingly；Detection circuit branch, it is connected with the output terminal of the tertiary circuit branch, for according to the tertiary circuit branch Output signal performance, determine that the silicon hole whether there is open circuit defect or circuit defect.
- 2. test circuit as claimed in claim 1, it is characterised in that another circuit branch is currently at conducting state When, the pulse width of the output terminal of the tertiary circuit branch is the signal delay of the output terminal of the silicon hole and described two The summation of the delay difference of the output of circuit branch, the detection circuit branch judge the arteries and veins of the output terminal of the tertiary circuit branch Whether in the reasonable scope width is rushed, if in the reasonable scope, open circuit defect is not present in the silicon hole, if beyond conjunction Scope is managed, then there are open circuit defect for the silicon hole；When another circuit branch is currently at off-state, the output terminal of the silicon hole is only defeated by the inverter device Go out to the input terminal of the tertiary circuit branch, the detection circuit branch judges output terminal and the institute of the tertiary circuit branch State the input terminal of silicon hole level whether on the contrary, if not on the contrary, if the silicon hole there are circuit defect, if on the contrary, Then circuit defect is not present in the silicon hole.
- 3. test circuit as claimed in claim 1, it is characterised in that the detection circuit branch includes：The first JK flip-flop being made of the first NAND gate and the second NAND gate, wherein the output of first NAND gate is described One input of the second NAND gate, another input of second NAND gate is the output of the tertiary circuit branch, described The output of second NAND gate is an input of first NAND gate, another input of first NAND gate is by non- The reset signal of door；The second JK flip-flop being made of the first nor gate and the second nor gate, wherein the output of first nor gate is described One of second nor gate input, another input of second nor gate are the reset signal, second nor gate Output be one of first nor gate input, another input of first nor gate is the tertiary circuit branch Output；Nor gate, an input of the nor gate is the output of first JK flip-flop, another input is described second The output of JK flip-flop, the nor gate export testing result.
- 4. test circuit as claimed in claim 1, it is characterised in that the tertiary circuit branch includes AND gate circuit；It is described Inverter device includes high threshold phase inverter；The level triggers device is using Schmidt trigger realization, the switching device bag Include P-channel metal-oxide-semiconductor field-effect transistor.
- A kind of 5. test method of silicon hole, it is characterised in that including：To the input terminal input stimulus pulse signal of the silicon hole；The output terminal that two circuit branch in parallel are connected to the silicon hole is provided, wherein a circuit branch includes phase inverter Part, another circuit branch include level triggers device and switching device, and the switching device controls the level triggers device institute The break-make of another circuit branch at place；Tertiary circuit branch is provided and is connected to the output terminals of two circuit branch in parallel, the tertiary circuit branch according to The state that is turned on or off that another circuit branch is currently at, exports accordingly；Detection circuit branch is provided and is connected to the output terminal of the tertiary circuit branch, the detection circuit branch is according to described the The signal performance of the output of three-circuit branch, determines that the silicon hole whether there is open circuit defect or circuit defect.
- 6. test method as claimed in claim 5, it is characterised in thatWhen circuit branch residing for switching device control level triggers device is currently at conducting state, the tertiary circuit branch Output terminal pulse width for the silicon hole the signal delay of output terminal and prolonging for the output of two circuit branch Summation poor late, the detection circuit branch judge the pulse width of the output terminal of the tertiary circuit branch and the silicon hole Input terminal pulse width whether in the reasonable scope, if in the reasonable scope, the silicon hole there is no open circuit lack Fall into, if exceeding zone of reasonableness, there are open circuit defect for the silicon hole；When circuit branch residing for switching device control level triggers device is currently at off-state, the output of the silicon hole End is only exported to the input terminal of the tertiary circuit branch by the inverter device, and the detection circuit branch judges described the The level of the input terminal of the output terminal of three-circuit branch and the silicon hole whether on the contrary, if not on the contrary, if the silicon hole There are circuit defect, if on the contrary, if the silicon hole circuit defect is not present.
- 7. test method as claimed in claim 5, it is characterised in that the tertiary circuit branch includes AND gate circuit；It is described Inverter device includes high threshold phase inverter；The level triggers device includes Schmidt trigger, and the switching device includes P ditches Road mos field effect transistor.
- A kind of 8. test circuit of silicon hole group in three dimensional integrated circuits, it is characterised in that including：The test such as claim 1-4 any one of them silicon holes corresponding with each silicon hole in the silicon hole group is electric Road, wherein, the driving source of each silicon hole is same or different in the silicon hole group, each silicon hole is corresponding The detection circuit branch is same or different in the silicon hole group；With the corresponding multi-selection device of each silicon hole in the silicon hole group, the multi-selection device be serially connected with the driving source with it is right Between the input terminal for the silicon hole answered, for controlling corresponding silicon hole to enter test pattern or normal mode, when the multiselect Device controls corresponding silicon hole to enter test pattern, and the input of the corresponding silicon hole is the output signal of the driving source, When the multi-selection device controls corresponding silicon hole to enter normal mode, the input of the corresponding silicon hole is believed for normal function Number；Switch block corresponding with each silicon hole in the silicon hole group, the switch block are arranged at corresponding silicon hole Test circuit tertiary circuit branch output terminal, for controlling corresponding silicon hole to enter test mould when the multi-selection device Formula, connects the switch block to obtain the test of corresponding silicon hole output.
- 9. the test method of silicon hole group in a kind of three dimensional integrated circuits, it is characterised in that use as claimed in claim 8 three The test circuit of silicon hole group is tested in dimension integrated circuit, to determine whether each silicon hole deposits in the silicon hole group In open circuit defect or circuit defect.
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| CN106771985A (en) * | 2017-02-20 | 2017-05-31 | 中国人民解放军国防科学技术大学 | A kind of weak short trouble test circuit and its method of testing |
| CN106959411A (en) * | 2017-03-29 | 2017-07-18 | 安徽云塔电子科技有限公司 | A kind of method of testing of integrated circuit and integrated circuit |
| CN108957167B (en) * | 2018-05-16 | 2020-09-18 | 桂林电子科技大学 | TSV fault testing device and method based on ring oscillator |
| CN109001614A (en) * | 2018-06-28 | 2018-12-14 | 西安理工大学 | A kind of 3D integrated circuit through silicon via fault detection system and detection method |
| CN110058113A (en) * | 2019-05-05 | 2019-07-26 | 哈尔滨工业大学 | Through silicon via test structure and method after a kind of binding for through silicon via leak current fault |
| CN111323694A (en) * | 2020-03-26 | 2020-06-23 | 安徽财经大学 | Silicon through hole open circuit fault test structure based on bridge structure |
| CN113495203B (en) * | 2020-04-03 | 2022-05-03 | 长鑫存储技术有限公司 | Test circuit and semiconductor test method |
| CN116794481A (en) * | 2022-03-14 | 2023-09-22 | 长鑫存储技术有限公司 | Through silicon via test structure and through silicon via short circuit test method |
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