CN111323694A - Silicon through hole open circuit fault test structure based on bridge structure - Google Patents

Silicon through hole open circuit fault test structure based on bridge structure Download PDF

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CN111323694A
CN111323694A CN202010220888.5A CN202010220888A CN111323694A CN 111323694 A CN111323694 A CN 111323694A CN 202010220888 A CN202010220888 A CN 202010220888A CN 111323694 A CN111323694 A CN 111323694A
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bridge
bridge structure
silicon
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circuit fault
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常郝
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Anhui University of Finance and Economics
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
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Abstract

The invention discloses a silicon through hole open-circuit fault test structure based on a bridge structure, which comprises an input end, a test end and a capture end, wherein the input end comprises a low-pass filter, the test end comprises a bridge structure consisting of 4 resistors, a PMOS (P-channel metal oxide semiconductor) tube and a reference capacitor, the ratio of the two resistors in the bridge arms of the bridge structure is equal, a silicon through hole to be tested is connected between the two bridge arms, the reference capacitor is connected between the bridge structure and the input end, the grid electrode of the PMOS tube is connected between the two resistors of one bridge arm of the bridge structure, and the source electrode of the PMOS tube is connected between the two resistors of the other bridge arm of the bridge structure. By adopting the bridge structure method provided by the invention, the influence of the additional resistance can be eliminated, and the bridge structure method is suitable for 10－6‑102And the measurement of the w resistance is greatly improved in test precision compared with the similar built-in self-test scheme.

Description

Silicon through hole open circuit fault test structure based on bridge structure
Technical Field
The invention relates to the technical field of wafer testing, in particular to a silicon through hole open-circuit fault testing structure based on a bridge structure.
Background
Shrinking transistor size is the primary method to ensure that the number of transistors per unit area increases, i.e., to continue moore's law. Moore's law continues more and more difficult as CMOS transistor fabrication processes evolve closer to the limits. Three-Dimensional Integrated Circuits (3D ICs) are currently introduced by the industry to continue moore's law. The 3D IC integrates a plurality of wafers (Die) in a vertical direction using Through Silicon Vias (TSVs), which greatly increases the number of transistors to be integrated, and is considered as an important technology for continuing moore's law.
TSVs are core components in 3D ICs, but are also sensitive cells that are susceptible to manufacturing defects. TSVs are the main components for signal transmission, power supply, and heat dissipation between layers of a 3D IC chip.
TSV interconnection faults between chips can be generally modeled as fixed faults, bridging faults, and tested using a boundary scan method, but the conventional test method is not sufficient for 3D ICs because the operating frequency of wafer interconnections in 3D ICs is very high and the end-to-end delay is only a few hundred picoseconds. The new type of failures caused by parameter defects (Parametric defects), such as small delay failures, resistive open failures, bridging failures, and leakage failures, have become new threats to the quality, yield, and reliability of 3D IC products.
In international research on TSV testing, representative methods are mainly divided into three types: 1. probe-based TSV testing techniques; 2. contactless TSV testing techniques; 3. TSV test techniques based on built-in self-test (BIST).
1. The problems with the probe test method are: 1) additional burden is imposed on the test equipment, such as customization, activation of the probe card; 2) the probe test needs to contact the back of the thinned wafer, and the implementation difficulty is high in practice; 3) probe contact forces on the TSV tips or solder balls may damage the TSVs resulting in reduced or even failure of the TSVs.
2. The challenges with the non-contact test method are: 1) the problems of signal coupling and crosstalk which are difficult to solve at present exist in a wireless transceiver and other active circuits; 2) wireless transceivers and antennas have large area and power consumption overhead; 3) in the pre-binding test and the post-binding test, the bandwidth configuration of the antenna and the transceiver needs to comprehensively consider factors such as cost, energy consumption and the like.
BIST technical research efforts mostly focus on testing for severe defects in TSVs, while for weak open, light leakage tests, the accuracy is not sufficient. The main disadvantages of the existing BIST approach are:
1) the BIST method is an indirect test method in nature and is not high in precision. Most of the existing BIST methods adopt indirect measurement, such as duty ratio, oscillation period of a ring oscillator, pulse disappearance, pulse width reduction and the like. The methods have good detection effects on complete open circuit faults and leakage faults, but have poor detection accuracy on incomplete open circuit faults and weak leakage faults.
2) The existing BIST methods cannot detect the resistance open-circuit fault at one end of the TSV deeply buried in the substrate because the TSV body connected with the test structure is nearly intact, and thus the resistance open-circuit fault does not obviously increase or decrease the capacitance of the TSV.
3) It is greatly influenced by Process, Voltage, and Temperature (PVT). The resolution of the BIST method is determined by a number of factors, typically in the tens of picoseconds range. For example, a ring oscillator with peak-to-peak jitter of 10ps cannot be used to detect TSV fault delays below 10 ps. This can cause PVT fluctuations to mask defects in the TSV if they have the same effect on the frequency of the ring oscillator.
4) The auxiliary correction circuit has a large area overhead. The BIST technique requires careful calibration or adjustment to facilitate accurate parameter measurement, but the test circuits used in the current BIST technique, such as voltage dividers or signal amplifiers, cannot be calibrated or adjusted in advance, and the test requirements of the micro-bump balls added to the TSVs at a later time are not taken into consideration, so that the BIST circuit itself is affected by process variations, which affect the accuracy of parameter testing. Two Phase Locked Loop (PLL) and Delay Locked Loop (DLL) Phase Locked Loop (PLL) have good control over process, supply voltage and temperature deviations due to an intrinsic feedback mechanism. However, BIST circuits occupy a relatively large die area, especially considering that there are typically thousands of TSVs per die, with TSV densities as high as 10000/mm2Therefore, the area overhead of the design for testability (correction circuit) cannot be ignored. The occupied area overhead of PLL and DLL is 0.024mm2And 7600um2。
Based on the above reasons, although the existing BIST method overcomes the limitation of test access, the test accuracy, the tolerance to PVT, and the reduction of testability design area overhead need to be further improved, whereas the resistance value of the TSV under an ideal condition is about 20mw, which is equivalent to a low-value resistance level, and the resistance open-circuit fault measured by the prior art is 1000w, which deviates from the normal value of the ideal TSV by 50000 times.
Disclosure of Invention
The invention aims to provide a through silicon via open-circuit fault test structure based on a bridge structure, so as to solve the problems in the background technology.
In order to achieve the purpose, the invention provides the following technical scheme:
a through silicon via open-circuit fault test structure based on a bridge structure comprises an input end, a test end and a capture end, wherein the input end comprises a low-pass filter;
the testing end comprises a bridge structure consisting of 4 resistors, a PMOS (P-channel metal oxide semiconductor) tube and a reference capacitor, the specific value of the two resistors in the bridge arms is equal, a silicon through hole to be tested is connected between the two bridge arms, the reference capacitor is connected between the bridge structure and the input end, the grid electrode of the PMOS tube is connected between the two resistors of one bridge arm of the bridge structure, and the source electrode of the PMOS tube is connected between the two resistors of the other bridge arm of the bridge structure.
As a further scheme of the invention: the capture end comprises an energy storage capacitor and an output buffer which is formed by connecting a plurality of phase inverters in series, and the energy storage capacitor is respectively connected with the source stage of the PMOS tube and the output buffer.
As a further scheme of the invention: in the output buffer, a plurality of groups of capacitors are connected in a phase inverter chain.
As a further scheme of the invention: the low-pass filter comprises a filter resistor and a filter capacitor, and is connected with a pseudo-sinusoidal signal generated by the ring oscillator.
As a further scheme of the invention: the ring oscillator generates a pseudo-sine wave with a frequency of 2 GHz.
As a further scheme of the invention: the reference capacitor is a capacitor with a metal insulation layer semiconductor structure.
Compared with the prior art, the invention has the beneficial effects that: by adopting the bridge structure method provided by the invention, the influence of the additional resistance can be eliminated, and the bridge structure method is suitable for 10－6-102And the measurement of the w resistance is greatly improved in test precision compared with the similar built-in self-test scheme.
Drawings
Fig. 1 is a schematic diagram of the structure of the present invention.
Fig. 2 is a voltage waveform diagram of the energy storage capacitor of the present invention.
Fig. 3 is a schematic diagram of the structure of the output buffer of the present invention.
FIG. 4 is a voltage waveform diagram of the gate and source of the PMOS transistor of the present invention.
FIG. 5 is a graph of the through-silicon via capacitance versus delay time in the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, in an embodiment of the present invention, a through silicon via open-circuit fault testing structure based on a bridge structure includes an input terminal 1, a testing terminal 2, and a capture terminal 3, where the input terminal 1 includes a low-pass filter, and the low-pass filter includes a filter resistor RfilterAnd a filter capacitor CfilterWherein R isfilter＝4kw，CfilterA low-pass filter is connected with a pseudo-sine signal generated by a ring oscillator constructed by 7 inverters, the frequency of the oscillation signal is relatively high in order to make the capacitance in the filter as small as possible, the frequency of the pseudo-sine wave generated by the ring oscillator is 2GHz, and the oscillation signal is used as an alternating current source of a bridge circuit after being filtered by the low-pass filter;
the test terminal 2 comprises 4 resistors: r1、R2、R3And R41 reference capacitor CstandardOne PMOS tube g and 1 TSV to be tested, wherein A1、C1Contact resistance at two points and R1、R2The parasitic resistance of the conducting wire is respectively connected with the R with larger resistance value1、R2The resistors are connected in series, so that the influence of contact resistance and wire parasitic resistance can be ignored; a. the2、C2Contact resistance of junction and R3、R4The parasitic resistance of the conducting wire is incorporated into the R with higher resistance value3、R4In (1). A. the2、C2Connected by thick wires, assume A2、C2Parasitic resistance of inter-conductor, A2、C2The sum of the contact resistances of the junctions is r. Contact resistance of D Point whether incorporating R3、R4Or incorporated into the galvanometer, the effect on the measurement results is negligible. The reference capacitance CstandardThe Metal Insulator Semiconductor (MIS) capacitor is realized by adopting a Metal MIS structure, the insulating layer is not pressurized and is not conductive, and no interface state exists at the interface between the insulating layer and the semiconductor.
By R1And R2Are all equal to I1Through R3And R4Are all equal to I2Through RTSVAnd RstandardAre also equal to each other and are I3When the bridge is balanced, the current in the galvanometer is IgThe potentials at the two points 0 and B, D are equal.
The capture terminal 3 comprises an energy storage capacitor CaAnd an output buffer composed of multiple inverters, the energy storage capacitor CaA source connected to a PMOS transistor g, via a PMOS transistor pair C when g is onaAnd charging is carried out to realize the energy storage function. CaSet to 5fF when passing CaIs higher than the threshold of the connected buffer, the output will flip from low to high, and the waveform changes as shown in fig. 2.
Output buffer for detecting CaVoltage level above, due to energy-storage capacitor CaIs charged by pseudo-sine signal of source stage of PMOS tube, CaThe voltage on is an oscillating signal of small amplitude. When the average voltage is approximately equal to the buffer threshold voltage, the output buffer amplifies the oscillating signal, which results in a longer flip period. To make the output result flip quickly, as shown in fig. 3, an inverter chain is addedSeveral sets of capacitors are added to speed up the flipping process.
The working principle of the invention is to use 4 resistors R1、R2、R3、R4Form a bridge circuit and make R3、R4Each following R1、R2The same proportion of change is made, the influence of the additional resistance r can be eliminated when the bridge is balanced, and the accurate measurement of the low-value resistance of the same level as the TSV is realized.
The PMOS transistor g functions as a comparator, functioning as a galvanometer, which detects whether the middle point of the two arms is balanced. g grid potential VgAnd source potential VsThe difference is used as a criterion to determine whether the bridge circuit is balanced. When the bridge circuit is balanced, the amplitude and the phase of the middle point of the two bridge arms are equal, but the bridge circuit has an amplitude difference delta to achieve balance, because g is a PMOS (P-channel metal oxide semiconductor) tube and can only be used for determining VgAnd VsWhether the voltage difference is greater than the amplitude difference Δ of the PMOS threshold voltage.
In that
Figure BDA0002426027590000071
Under the conditions, the following formula holds:
Figure BDA0002426027590000072
considering that the galvanometer is implemented by a PMOS transistor, the PMOS transistor has a threshold voltage D, and therefore:
Figure BDA0002426027590000073
in consideration of the ac power supply, the formula (2) is equivalent to the following formula:
Figure BDA0002426027590000081
in which the impedance generated by the capacitor
Figure BDA0002426027590000082
j represents a phase difference of 90 degrees.
Wherein R is1＝4kw，R2＝20kw，R3＝12kw，R460kw are the resistance of the TSV arm and the resistance of the reference arm, respectively; cstandard70fF is the reference capacitance, CxIs the TSV capacitance to be measured, Δ ═ Vth,p/Vdd。
From equation (3), it can be seen that Δ is a complex number, but since the phase difference between the two legs is small, only the real part of Δ needs to be considered, and the imaginary part does not need to be considered. Due to the voltage difference Δ, the capacitance on the two arms is different from that of a common ac bridge. If the bridge circuit is unbalanced, e.g. the voltage difference is larger than delta, the comparator PMOS will be turned on. Assuming that the TSV capacitance is 60fF, the gate V of the PMOS transistor g of the comparatorgSource electrode VsThe voltage waveforms are shown in fig. 4, and thus are used to explain the operation of the bridge circuit. V in pseudo-sine wave periodgLess than VsPart, when the voltage difference reaches VthWhen so, the PMOS is turned on.
When the circuit is powered on, the test is started, and the NMOS is controlled by a reset signal and is used as a pair CaA discharge is performed, called reset NMOS. Applying a reset signal at the beginning of the test procedure to remove the energy storage capacitor CaOf the charge of (1). The reset NMOS should be larger than the comparator PMOS to ensure a successful reset. After the reset signal goes low, if there is a defect in the TSV, charge will accumulate to CaIn (1).
There is a delay time from the reset signal reset going low to the output going high, which is used to measure the TSV capacitance. This delay time is significantly dependent on the TSV and the reference capacitance CstandardThe difference in capacitance between. The relationship between delay time and TSV capacitance is shown in fig. 5. Therefore, when the TSV has large defects and is far away from the standard value, the response time of the test circuit is short, and the capacitance of the TSV cannot be changed too much. If the TSV capacitance fluctuates less than its standard value, the circuit response time increases to a longer delay time. Thus, this feature is used to enable the circuit to efficiently detect large openings with high accuracyPath defects and less capacitance fluctuation.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.

Claims (6)

1. The utility model provides a through-silicon via opens a way fault test structure based on bridge structure, includes input, test end and catches the end, its characterized in that: the input end comprises a low-pass filter; the testing end comprises a bridge structure consisting of 4 resistors, a PMOS (P-channel metal oxide semiconductor) tube and a reference capacitor, the specific value of the two resistors in the bridge arms is equal, a silicon through hole to be tested is connected between the two bridge arms, the reference capacitor is connected between the bridge structure and the input end, the grid electrode of the PMOS tube is connected between the two resistors of one bridge arm of the bridge structure, and the source electrode of the PMOS tube is connected between the two resistors of the other bridge arm of the bridge structure.
2. The open-circuit fault test structure of silicon through holes based on bridge structure as claimed in claim 1, wherein: the capture end comprises an energy storage capacitor and an output buffer which is formed by connecting a plurality of phase inverters in series, and the energy storage capacitor is respectively connected with the source stage of the PMOS tube and the output buffer.
3. The open-circuit fault test structure of silicon through holes based on bridge structure as claimed in claim 2, characterized in that: in the output buffer, a plurality of groups of capacitors are connected in a phase inverter chain.
4. The open-circuit fault test structure of silicon through holes based on bridge structure as claimed in claim 1, wherein: the low-pass filter comprises a filter resistor and a filter capacitor, and is connected with a pseudo-sinusoidal signal generated by the ring oscillator.
5. The open-circuit fault test structure for silicon through holes based on bridge structure as claimed in claim 4, wherein: the ring oscillator generates a pseudo-sine wave with a frequency of 2 GHz.
6. The open-circuit fault test structure of silicon through holes based on bridge structure as claimed in claim 1, wherein: the reference capacitor is a capacitor with a metal insulation layer semiconductor structure.
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Application publication date: 20200623