US20110102006A1 - Circuit and method for testing semiconductor apparatus - Google Patents

Circuit and method for testing semiconductor apparatus Download PDF

Info

Publication number
US20110102006A1
US20110102006A1 US12/651,066 US65106609A US2011102006A1 US 20110102006 A1 US20110102006 A1 US 20110102006A1 US 65106609 A US65106609 A US 65106609A US 2011102006 A1 US2011102006 A1 US 2011102006A1
Authority
US
United States
Prior art keywords
tsv
tsvs
signal
test
enabled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12/651,066
Inventor
Min Seok CHOI
Jong Chern Lee
Sang Jin Byeon
Young Jun KU
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Assigned to HYNIX SEMICONDUCTOR INC. reassignment HYNIX SEMICONDUCTOR INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BYEON, SANG JIN, CHOI, MIN SEOK, KU, YOUNG JUN, LEE, JONG CHERN
Publication of US20110102006A1 publication Critical patent/US20110102006A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's
    • G01R31/318513—Test of Multi-Chip-Moduls
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Definitions

  • Various embodiments of the present disclosure generally relate to a semiconductor apparatus, and more particularly, to a circuit and a method for testing a semiconductor apparatus.
  • a three-dimensional (3D) semiconductor apparatus comprising a plurality of stacked chips.
  • the stacked chips provide a structure that enables the 3D semiconductor apparatus to be packaged in a single package.
  • a through-silicon via (TSV) type semiconductor apparatus has been developed in which silicon vias are formed to pass through the plurality of stacked chips so that all of the chips are electrically connected to one another.
  • the 3D semiconductor apparatus has the plurality of TSVs such that the plurality of stacked chips can commonly receive various signals.
  • the plurality of stacked chips can commonly receive address signals, test signals, input/output line signals and command signals through the TSVs.
  • the defects can include voids which are produced due to incomplete filling of a conductive material in the TSVs, bump contact fails which result due to warpage of the chips or migration of a bump material, and cracks of the TSVs themselves.
  • TSVs electrically connect the plurality of chips, if a TSV creates an open circuit due to an occurrence of a defect, the TSV cannot function properly. Therefore, a defective TSV must be replaced with a functional TSV.
  • Various aspects of the present invention comprise a circuit and a method for testing a semiconductor apparatus which can determine whether a TSV is connected.
  • a circuit for testing a semiconductor apparatus comprises a test voltage applying unit configured to apply a test voltage to a first end of a through-silicon via (TSV) in response to a test mode signal; and a detecting unit configured to be connected to a second end of the TSV and detect a current outputted from the second end of the TSV.
  • TSV through-silicon via
  • a method of testing a semiconductor apparatus comprising applying a current to a TSV during a testing operation; and comparing an amount of the current flowing through the TSV with a reference value.
  • a circuit for testing a semiconductor apparatus comprises a test voltage applying unit configured to apply a test voltage to a first end of a TSV in response to a test mode signal; and a detection unit configured to be connected to a second end of the TSV, compare a voltage outputted from the second end of the TSV with a reference voltage, and generate a detection signal.
  • a circuit for testing a semiconductor apparatus comprises a test voltage applying section configured to apply a test voltage to a plurality of TSVs in response to a test mode signal; and a determining section configured to be sequentially connected to one of the plurality of TSVs in response to the test mode signal.
  • a circuit for testing a semiconductor apparatus comprises a test voltage applying section configured to apply a test voltage to first and second TSVs in response to a test mode signal; and a determining section configured to be connected to the first and second TSVs in response to the test mode signal.
  • FIGS. 1A and 1B are diagrams schematically illustrating a configuration of a circuit for testing a semiconductor apparatus according to one embodiment of the present invention.
  • FIG. 2 is a diagram schematically illustrating a configuration of a circuit for testing a semiconductor apparatus according to one embodiment of the present invention.
  • FIG. 3 is a diagram illustrating the configuration of a determining section of the semiconductor apparatus shown in FIG. 2 .
  • FIG. 4 is a timing diagram showing an operation of the test circuit shown in FIG. 2 .
  • FIGS. 1A and 1B are diagrams schematically illustrating a configuration of a circuit for testing a semiconductor apparatus according to one embodiment of the present invention.
  • a test circuit comprises a test voltage applying unit 10 , a through-silicon via (TSV), and a detecting unit 20 .
  • the test voltage applying unit 10 applies a test voltage Vtest to the TSV in response to a test mode signal TM.
  • the test mode signal TM comprises a signal that is inputted to test the semiconductor apparatus.
  • a testing operation may begin. Accordingly, if the test mode signal TM is enabled and the testing operation is started, the test voltage applying unit 10 applies the test voltage Vtest to the TSV.
  • the test voltage applying unit 10 may comprise, for example, a metal oxide semiconductor (MOS) transistor. It is to be noted that the test voltage applying unit 10 may comprise a p-type metal oxide semiconductor (PMOS) transistor P 1 in FIG. 1A or an n-type metal oxide semiconductor (NMOS) transistor N 1 in FIG. 1B . In FIG. 1A , the PMOS transistor P 1 has a gate which receives an inverted signal TMb of the test mode signal TM, a source terminal to which the test voltage Vtest is applied, and a drain terminal which is connected to a first end of the TSV. In FIG.
  • MOS metal oxide semiconductor
  • the NMOS transistor N 1 has a gate which receives the test mode signal TM, a drain terminal to which the test voltage Vtest is applied, and a source terminal which is connected to the first end of the TSV. Therefore, if the test mode signal TM is enabled to a high level, the test voltage applying unit 10 may apply the test voltage Vtest to the first end of the TSV.
  • the detecting unit 20 is connected to a second end of the TSV. Since the detecting unit 20 is connected to the second end of the TSV, the detecting unit 20 can detect a current that flows through the TSV or a voltage that is outputted from the second end of the TSV.
  • a pad which is provided with the semiconductor apparatus may be used as the detecting unit 20 .
  • the detecting unit 20 may comprise a differential amplifier. In the case where the detecting unit 20 comprises a pad, the pad may receive current that flows through the TSV. An amount of the current that flows through the TSV may be measured by test equipment or through probe detection. Thus, by comparing the amount of current flowing through the TSV and a reference value, a determination may be made regarding whether the TSV is properly connected.
  • the detecting unit 20 may amplify a difference between the voltage outputted from the second end of the TSV and a reference voltage, and generate a detection signal. Since the test voltage Vtest is applied to the first end of the TSV and if the test mode signal TM is enabled, the detecting unit 20 may compare the voltage outputted from the second end of the TSV with the reference voltage and generate the detection signal. If the level of the voltage outputted from the second end of the TSV is higher than the level of the reference voltage, a determination regarding whether the TSV is properly connected can be determined by the detection signal because the detection signal has been enabled. Because the detection signal has information regarding proper or improper connection or disconnection of the TSV, the detection signal may be used for various purposes in a semiconductor apparatus, such as, for example, for repair.
  • the reference value and the reference voltage can be changed depending on the level of the test voltage Vtest and a desired level.
  • the test voltage Vtest may comprise, for example, an external voltage.
  • the reference value and the reference voltage may be appropriately set in consideration of the threshold voltage of the MOS transistor comprising the test voltage applying unit 10 and the conductivity of the TSV.
  • the reference value may be set to one half of a maximum amount of current capable of flowing when the test voltage Vtest is applied, and the reference voltage may be set to one half of the test voltage Vtest.
  • test mode signal TM If the test mode signal TM is enabled and the test voltage Vtest is applied to the first end of the TSV, a current flows through the TSV.
  • the detecting unit 20 is applied with the current or voltage outputted from the second end of the TSV. If an amount of current outputted from the second end of the TSV is greater than the reference value, the TSV may be determined as being properly connected, and if the amount of current is less than the reference value, the TSV may be determined as being improperly connected or disconnected.
  • the TSV may be determined as being properly connected. Conversely, if the level of the voltage outputted from the second end of the TSV is lower than the level of the reference voltage so that the detection signal is disabled, the TSV may be determined as being improperly connected or disconnected.
  • the circuit for testing a semiconductor apparatus in accordance with the embodiment of the present invention, whether the TSV of the semiconductor apparatus is open or short-circuited may be tested in a simple and convenient manner.
  • the semiconductor apparatus comprises a plurality of TSVs, it is difficult and time-consuming to individually check the connections of the TSVs. Therefore, a method for simultaneously testing whether a plurality of TSVs is open or short-circuited is required.
  • FIG. 2 is a diagram schematically illustrating a configuration of a circuit for testing a semiconductor apparatus in accordance with one embodiment of the present invention.
  • a test circuit comprises a test voltage applying section 100 , a plurality of TSVs designated by TSV 1 , TSV 2 , TSV 3 . . . , and a determining section 200 .
  • the test voltage applying section 100 applies a test voltage Vtest to the plurality of respective TSVs TSV 1 , TSV 2 , TSV 3 . . . , in response to a test mode signal TM. If the test mode signal TM is enabled at a start of a testing operation for a semiconductor apparatus, the test voltage applying section 100 applies the test voltage Vtest to the plurality of respective TSVs TSV 1 , TSV 2 , TSV 3 , . . . , In FIG. 2 , the test voltage applying section 100 may comprise PMOS transistors which are respectively connected to first ends of the respective TSVs TSV 1 , TSV 2 , TSV 3 , . . . . Of course, the test voltage applying section 100 may comprise NMOS transistors as shown in FIG. 1 .
  • the test voltage applying section 100 comprises first through third PMOS transistors P 11 , P 12 and P 13 .
  • the first PMOS transistor P 11 has a gate which receives an inverted signal TMb of the test mode signal TM, a source terminal which receives the test voltage Vtest, and a drain terminal which is connected to the first end of the first TSV TSV 1 .
  • the second PMOS transistor P 12 has a gate which receives the inverted signal TMb of the test mode signal TM, a source terminal which receives the test voltage Vtest, and a drain terminal which is connected to the first end of the second TSV TSV 2 .
  • the third PMOS transistor P 13 has a gate which receives the inverted signal TMb of the test mode signal TM, a source terminal which receives the test voltage Vtest, and a drain terminal which is connected to the first end of the third TSV TSV 3 .
  • the determining section 200 may be sequentially connected to respective second ends of the first through third TSVs TSV 1 , TSV 2 and TSV 3 for a predetermined interval.
  • the determining section 200 detects currents or voltages outputted from the second ends of the first through third TSVs TSV 1 , TSV 2 and TSV 3 .
  • the predetermined interval may be periodic or random.
  • the determining section 200 receives the test mode signal TM, a clock signal CLK and a reset signal RST and detects the currents or voltages outputted through the first through third TSVs TSV 1 , TSV 2 and TSV 3 .
  • the predetermined interval may correspond to, for example, one period of the clock signal CLK.
  • the determining section 200 may be connected sequentially to one of the first through third TSVs TSV 1 , TSV 2 and TSV 3 . In other words, intervals during which the determining section 200 is connected to the respective first through third TSVs TSV 1 , TSV 2 and TSV 3 do not overlap with one another.
  • the reset signal RST is enabled
  • the determining section 200 is initialized. If the test mode signal TM is enabled, the determining section 200 may be connected to the first TSV TSV 1 for one period of the clock signal CLK. The test mode signal TM may then be connected to the second TSV TSV 2 for one period of the clock signal CLK, and is thereafter connected to the third TSV TSV 3 for one period of the clock signal CLK. Therefore, connections of the determining section 200 with the respective first through third TSVs TSV 1 , TSV 2 and TSV 3 do not overlap with one another.
  • FIG. 3 is a diagram illustrating a configuration of the determining section 200 shown in FIG. 2 .
  • the determining section 200 comprises a selection signal generating unit 210 , a selecting unit 220 , and a detecting unit 230 .
  • the determining section 200 further comprises a pulse generating unit 240 which is configured to receive the test mode signal TM and generate a test pulse TM_pulse.
  • the pulse generating unit 240 comprises a general pulse generator which can generate the test pulse TM_pulse when the test mode signal TM is enabled.
  • the selection signal generating unit 210 receives the test pulse TM_pulse, the clock signal CLK and the reset signal RST.
  • the selection signal generating unit 210 is initialized in response to the reset signal RST, and generates first through third selection signals S 1 , S 2 and S 3 in response to the test pulse TM_pulse and the clock signal CLK.
  • the selection signal generating unit 210 generates the selection signals S 1 , S 2 and S 3 that are sequentially enabled, when the test pulse TM_pulse is inputted.
  • the selecting unit 220 connects the first through third TSVs TSV 1 , TSV 2 and TSV 3 to the detecting unit 230 in response to the selection signals S 1 , S 2 and S 3 . More specifically, the selecting unit 220 sequentially connects the first through third TSVs TSV 1 , TSV 2 and TSV 3 to the detecting unit 230 in response to the selection signals S 1 , S 2 and S 3 that are sequentially enabled.
  • the detecting unit 230 is sequentially connected to the first through third TSVs TSV 1 , TSV 2 and TSV 3 by the selecting unit 220 .
  • the detecting unit 230 detects currents or voltages outputted through the first through third TSVs TSV 1 , TSV 2 and TSV 3 .
  • the selection signal generating unit 210 comprises first through third flip-flops FF 1 , FF 2 and FF 3 .
  • the first through third flip-flops FF 1 , FF 2 and FF 3 are connected in series and respectively generate the selection signals S 1 , S 2 and S 3 .
  • the first flip-flop FF 1 generates the first selection signal S 1 in synchronization with the clock signal CLK when the test pulse TM_pulse is generated.
  • the second flip-flop FF 2 receives the first selection signal S 1 and generates the second selection signal S 2 in synchronization with the clock signal CLK.
  • the third flip-flop FF 3 receives the second selection signal S 2 and generates the third selection signal S 3 in synchronization with the clock signal CLK.
  • the second and third flip-flops FF 2 and FF 3 respectively receive outputs of the first and second flip-flops FF 1 and FF 2 , enabled intervals of the first through third selection signals S 1 , S 2 and S 3 do not overlap with one another and may be sequentially defined.
  • the selecting unit 220 comprises first through third pass gates PG 1 , PG 2 and PG 3 .
  • the first through third pass gates PG 1 , PG 2 and PG 3 are respectively connected to the second ends of the first through third TSVs TSV 1 , TSV 2 and TSV 3 and selectively transmit outputs of the second ends of the first through third TSVs. TSV 1 , TSV 2 and TSV 3 .
  • the first pass gate PG 1 connects the second end of the first TSV TSV 1 to the detecting unit 230 in response to the first selection signal S 1 and an inverted signal of the first selection signal S 1 that is inverted by a first inverter IV 1 .
  • the second pass gate PG 2 connects the second end of the second TSV TSV 2 to the detecting unit 230 in response to the second selection signal S 2 and an inverted signal of the second selection signal S 2 that is inverted by a second inverter IV 2 .
  • the third pass gate PG 3 connects the second end of the third TSV TSV 3 with the detecting unit 230 in response to the third selection signal S 3 and an inverted signal of the third selection signal S 3 that is inverted by a third inverter IV 3 .
  • the detecting unit 230 may comprise pads or differential amplifiers as shown in FIG. 1 .
  • the detecting unit 230 may be constructed in the same manner as the detecting unit 20 of FIG. 1 as described above.
  • the determining section 200 may be sequentially connected to the first through third TSVs TSV 1 , TSV 2 and TSV 3 , detect the currents or voltages outputted through the first through third TSVs TSV 1 , TSV 2 and TSV 3 , and determine at once whether the first through third TSVs are open or short-circuited.
  • FIG. 4 is a timing diagram showing operations of the test circuit shown in FIG. 2 .
  • the operations of the circuit for testing a semiconductor apparatus in accordance with the embodiment of the present invention are described below with reference to FIGS. 2-4 .
  • the determining section 200 is initialized. Thereafter, the test mode signal TM is enabled to start a testing operation for a semiconductor apparatus. If the test mode signal TM is enabled, the test voltage applying section 100 applies the test voltage Vtest to the first through third TSVs TSV 1 , TSV 2 and TSV 3 .
  • the pulse generating unit 240 If the test mode signal TM is enabled, the pulse generating unit 240 generates the test pulse TM_pulse.
  • the first flip-flop FF 1 of the selection signal generating section 210 latches the test pulse TM_pulse at the falling edge of the clock signal CLK and outputs the latched signal until the next falling edge of the clock signal CLK. Thus, the first flip-flop FF 1 generates the first selection signal S 1 that is enabled for one period of the clock signal CLK.
  • the second flip-flop FF 2 receives the first selection signal S 1 and generates the second selection signal S 2 that is enabled for one period of the clock signal CLK
  • the third flip-flop FF 3 receives the second selection signal S 2 and generates the third selection signal S 3 that is enabled for one period of the clock signal CLK.
  • the first pass gate PG 1 of the selecting unit 220 connects the first TSV TSV 1 to the detecting unit 230 in response to the first selection signal S 1 .
  • the second pass gate PG 2 of the selecting unit 220 connects the second TSV TSV 2 to the detecting unit 230 in response to the second selection signal S 2
  • the third pass gate PG 3 of the selecting unit 220 connects the third TSV TSV 3 to the detecting unit 230 in response to the third selection signal S 3 .
  • the outputs of the first through third pass gates PG 1 , PG 2 and PG 3 are the currents outputted through the first through third TSVs TSV 1 , TSV 2 and TSV 3 .
  • the detecting unit 230 When connected to the respective first through third TSVs TSV 1 , TSV 2 and TSV 3 , the detecting unit 230 detects currents having flowed through the first through third TSVs TSV 1 , TSV 2 and TSV 3 . Detecting intervals are shown in FIG. 4 . It is preferred that detection timing be set to when a predetermined time has lapsed after the first selection signal S 1 is enabled. As described above, if the first through third TSVs TSV 1 , TSV 2 and TSV 3 are connected to the detecting unit 230 , peak currents are produced. Therefore, it is desirable to detect an amount of a current flowing through the TSV after the peak current vanishes to determine whether the TSV is properly connected. FIG.
  • FIG 4 shows amounts of currents that are detected by the detecting unit 230 . Because the currents flowing through the first through third TSVs TSV 1 , TSV 2 and TSV 3 are detected by the detecting unit 230 , that is, amounts of currents greater than a reference value, a determination may be made that all of the first through third TSVs TSV 1 , TSV 2 and TSV 3 are properly connected. If a detected amount of current is less than the reference value, a determination may be made that the corresponding TSV with the detected amount of current less than the reference value is not properly connected. An improperly connected TSV may then be replaced with a repair TSV.
  • test circuit can detect a connection or disconnection of the TSVs in a precise and convenient manner. Also, in the present invention, a test time can be shortened and the reliability of the semiconductor apparatus improved.

Abstract

A circuit for testing a semiconductor apparatus includes a test voltage applying unit configured to apply a test voltage to a first end of a through-silicon via (TSV) in response to a test mode signal and a detecting unit configured to be connected to a second end of the TSV and detect a current outputted from the second end of the TSV.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • The present application claims priority under 35 U.S.C. §119(a) to Korean Application No. 10-2009-0103598, filed on Oct. 29, 2009, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety as if set forth in full.
    • BACKGROUND
  • 1. Technical Field
  • Various embodiments of the present disclosure generally relate to a semiconductor apparatus, and more particularly, to a circuit and a method for testing a semiconductor apparatus.
  • 2. Related Art
  • In order to increase the integration of a semiconductor apparatus, a three-dimensional (3D) semiconductor apparatus comprising a plurality of stacked chips has been developed. The stacked chips provide a structure that enables the 3D semiconductor apparatus to be packaged in a single package. Recently, a through-silicon via (TSV) type semiconductor apparatus has been developed in which silicon vias are formed to pass through the plurality of stacked chips so that all of the chips are electrically connected to one another.
  • The 3D semiconductor apparatus has the plurality of TSVs such that the plurality of stacked chips can commonly receive various signals. For example, in the case of a memory apparatus, the plurality of stacked chips can commonly receive address signals, test signals, input/output line signals and command signals through the TSVs.
  • Various defects, however, may occur in the TSVs. For example, the defects can include voids which are produced due to incomplete filling of a conductive material in the TSVs, bump contact fails which result due to warpage of the chips or migration of a bump material, and cracks of the TSVs themselves.
  • Since the TSVs electrically connect the plurality of chips, if a TSV creates an open circuit due to an occurrence of a defect, the TSV cannot function properly. Therefore, a defective TSV must be replaced with a functional TSV.
  • As a result, since proper connection of TSVs is important for reliable product manufacture, there is a need for a method of determining whether TSVs are properly connected.
    • SUMMARY OF THE INVENTION
  • Various aspects of the present invention comprise a circuit and a method for testing a semiconductor apparatus which can determine whether a TSV is connected.
  • In one aspect of the present invention, a circuit for testing a semiconductor apparatus comprises a test voltage applying unit configured to apply a test voltage to a first end of a through-silicon via (TSV) in response to a test mode signal; and a detecting unit configured to be connected to a second end of the TSV and detect a current outputted from the second end of the TSV.
  • In another aspect of the present invention, a method of testing a semiconductor apparatus comprising applying a current to a TSV during a testing operation; and comparing an amount of the current flowing through the TSV with a reference value.
  • In still another aspect of the present invention, a circuit for testing a semiconductor apparatus comprises a test voltage applying unit configured to apply a test voltage to a first end of a TSV in response to a test mode signal; and a detection unit configured to be connected to a second end of the TSV, compare a voltage outputted from the second end of the TSV with a reference voltage, and generate a detection signal.
  • In still another aspect of the present invention, a circuit for testing a semiconductor apparatus comprises a test voltage applying section configured to apply a test voltage to a plurality of TSVs in response to a test mode signal; and a determining section configured to be sequentially connected to one of the plurality of TSVs in response to the test mode signal.
  • In still another aspect of the present invention, a circuit for testing a semiconductor apparatus comprises a test voltage applying section configured to apply a test voltage to first and second TSVs in response to a test mode signal; and a determining section configured to be connected to the first and second TSVs in response to the test mode signal.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention. FIGS. 1A and 1B are diagrams schematically illustrating a configuration of a circuit for testing a semiconductor apparatus according to one embodiment of the present invention.
  • FIG. 2 is a diagram schematically illustrating a configuration of a circuit for testing a semiconductor apparatus according to one embodiment of the present invention.
  • FIG. 3 is a diagram illustrating the configuration of a determining section of the semiconductor apparatus shown in FIG. 2.
  • FIG. 4 is a timing diagram showing an operation of the test circuit shown in FIG. 2.
    •  DETAILED DESCRIPTION OF THE EMBODIMENTS
  • Advantages and characteristics of the present invention and a method for achieving them will be apparent with reference to embodiments described below with reference to the accompanying drawings. However, the present invention is not limited to the exemplary embodiments described below but may be implemented in various forms. Therefore, the exemplary embodiments are provided to enable those skilled in the art to thoroughly understand the teaching of the present invention and to completely inform the scope of the present invention and the exemplary embodiment is just defined by the scope of the appended claims. Throughout the specification, like elements refer to like reference numerals.
  • FIGS. 1A and 1B are diagrams schematically illustrating a configuration of a circuit for testing a semiconductor apparatus according to one embodiment of the present invention. Referring to FIGS. 1A and B, a test circuit comprises a test voltage applying unit 10, a through-silicon via (TSV), and a detecting unit 20. The test voltage applying unit 10 applies a test voltage Vtest to the TSV in response to a test mode signal TM. The test mode signal TM comprises a signal that is inputted to test the semiconductor apparatus. When the test mode signal TM is inputted, a testing operation may begin. Accordingly, if the test mode signal TM is enabled and the testing operation is started, the test voltage applying unit 10 applies the test voltage Vtest to the TSV.
  • The test voltage applying unit 10 may comprise, for example, a metal oxide semiconductor (MOS) transistor. It is to be noted that the test voltage applying unit 10 may comprise a p-type metal oxide semiconductor (PMOS) transistor P1 in FIG. 1A or an n-type metal oxide semiconductor (NMOS) transistor N1 in FIG. 1B. In FIG. 1A, the PMOS transistor P1 has a gate which receives an inverted signal TMb of the test mode signal TM, a source terminal to which the test voltage Vtest is applied, and a drain terminal which is connected to a first end of the TSV. In FIG. 1B, the NMOS transistor N1 has a gate which receives the test mode signal TM, a drain terminal to which the test voltage Vtest is applied, and a source terminal which is connected to the first end of the TSV. Therefore, if the test mode signal TM is enabled to a high level, the test voltage applying unit 10 may apply the test voltage Vtest to the first end of the TSV.
  • The detecting unit 20 is connected to a second end of the TSV. Since the detecting unit 20 is connected to the second end of the TSV, the detecting unit 20 can detect a current that flows through the TSV or a voltage that is outputted from the second end of the TSV. A pad which is provided with the semiconductor apparatus may be used as the detecting unit 20. Also, the detecting unit 20 may comprise a differential amplifier. In the case where the detecting unit 20 comprises a pad, the pad may receive current that flows through the TSV. An amount of the current that flows through the TSV may be measured by test equipment or through probe detection. Thus, by comparing the amount of current flowing through the TSV and a reference value, a determination may be made regarding whether the TSV is properly connected.
  • In a case where the detecting unit 20 comprises a differential amplifier, the detecting unit 20 may amplify a difference between the voltage outputted from the second end of the TSV and a reference voltage, and generate a detection signal. Since the test voltage Vtest is applied to the first end of the TSV and if the test mode signal TM is enabled, the detecting unit 20 may compare the voltage outputted from the second end of the TSV with the reference voltage and generate the detection signal. If the level of the voltage outputted from the second end of the TSV is higher than the level of the reference voltage, a determination regarding whether the TSV is properly connected can be determined by the detection signal because the detection signal has been enabled. Because the detection signal has information regarding proper or improper connection or disconnection of the TSV, the detection signal may be used for various purposes in a semiconductor apparatus, such as, for example, for repair.
  • The reference value and the reference voltage can be changed depending on the level of the test voltage Vtest and a desired level. The test voltage Vtest may comprise, for example, an external voltage. When the test voltage Vtest comprises an external voltage, the reference value and the reference voltage may be appropriately set in consideration of the threshold voltage of the MOS transistor comprising the test voltage applying unit 10 and the conductivity of the TSV. For example, the reference value may be set to one half of a maximum amount of current capable of flowing when the test voltage Vtest is applied, and the reference voltage may be set to one half of the test voltage Vtest.
  • Below is an exemplary operation of the circuit for testing a semiconductor apparatus in accordance with the embodiment of the present invention. If the test mode signal TM is enabled and the test voltage Vtest is applied to the first end of the TSV, a current flows through the TSV. The detecting unit 20 is applied with the current or voltage outputted from the second end of the TSV. If an amount of current outputted from the second end of the TSV is greater than the reference value, the TSV may be determined as being properly connected, and if the amount of current is less than the reference value, the TSV may be determined as being improperly connected or disconnected. Similarly, if the level of the voltage outputted from the second end of the TSV is higher than the level of the reference voltage so that the detection signal is enabled, the TSV may be determined as being properly connected. Conversely, if the level of the voltage outputted from the second end of the TSV is lower than the level of the reference voltage so that the detection signal is disabled, the TSV may be determined as being improperly connected or disconnected.
  • Accordingly, in the circuit for testing a semiconductor apparatus in accordance with the embodiment of the present invention, whether the TSV of the semiconductor apparatus is open or short-circuited may be tested in a simple and convenient manner. However, because the semiconductor apparatus comprises a plurality of TSVs, it is difficult and time-consuming to individually check the connections of the TSVs. Therefore, a method for simultaneously testing whether a plurality of TSVs is open or short-circuited is required.
  • FIG. 2 is a diagram schematically illustrating a configuration of a circuit for testing a semiconductor apparatus in accordance with one embodiment of the present invention. Referring to FIG. 2, a test circuit comprises a test voltage applying section 100, a plurality of TSVs designated by TSV1, TSV2, TSV3 . . . , and a determining section 200.
  • The test voltage applying section 100 applies a test voltage Vtest to the plurality of respective TSVs TSV1, TSV2, TSV3 . . . , in response to a test mode signal TM. If the test mode signal TM is enabled at a start of a testing operation for a semiconductor apparatus, the test voltage applying section 100 applies the test voltage Vtest to the plurality of respective TSVs TSV1, TSV2, TSV3, . . . , In FIG. 2, the test voltage applying section 100 may comprise PMOS transistors which are respectively connected to first ends of the respective TSVs TSV1, TSV2, TSV3, . . . . Of course, the test voltage applying section 100 may comprise NMOS transistors as shown in FIG. 1.
  • As shown in FIG. 2, it is to be understood that one of ordinary skill in the art can appreciate that the technical concept of the present invention can be applied in the same way even though the number of TSVs increases. In FIG. 2, the test voltage applying section 100 comprises first through third PMOS transistors P11, P12 and P13. The first PMOS transistor P11 has a gate which receives an inverted signal TMb of the test mode signal TM, a source terminal which receives the test voltage Vtest, and a drain terminal which is connected to the first end of the first TSV TSV1. The second PMOS transistor P12 has a gate which receives the inverted signal TMb of the test mode signal TM, a source terminal which receives the test voltage Vtest, and a drain terminal which is connected to the first end of the second TSV TSV2. The third PMOS transistor P13 has a gate which receives the inverted signal TMb of the test mode signal TM, a source terminal which receives the test voltage Vtest, and a drain terminal which is connected to the first end of the third TSV TSV3.
  • The determining section 200 may be sequentially connected to respective second ends of the first through third TSVs TSV1, TSV2 and TSV3 for a predetermined interval. When the determining section 200 is connected to the respective first through third TSVs TSV1, TSV2 and TSV3, the determining section 200 detects currents or voltages outputted from the second ends of the first through third TSVs TSV1, TSV2 and TSV3. The predetermined interval may be periodic or random. In FIG. 2, the determining section 200 receives the test mode signal TM, a clock signal CLK and a reset signal RST and detects the currents or voltages outputted through the first through third TSVs TSV1, TSV2 and TSV3. In the embodiment, since the determining section 200 uses the clock signal CLK, the predetermined interval may correspond to, for example, one period of the clock signal CLK.
  • The determining section 200 may be connected sequentially to one of the first through third TSVs TSV1, TSV2 and TSV3. In other words, intervals during which the determining section 200 is connected to the respective first through third TSVs TSV1, TSV2 and TSV3 do not overlap with one another. Before the testing operation is started, if the reset signal RST is enabled, the determining section 200 is initialized. If the test mode signal TM is enabled, the determining section 200 may be connected to the first TSV TSV1 for one period of the clock signal CLK. The test mode signal TM may then be connected to the second TSV TSV2 for one period of the clock signal CLK, and is thereafter connected to the third TSV TSV3 for one period of the clock signal CLK. Therefore, connections of the determining section 200 with the respective first through third TSVs TSV1, TSV2 and TSV3 do not overlap with one another.
  • FIG. 3 is a diagram illustrating a configuration of the determining section 200 shown in FIG. 2. Referring to FIG. 3, the determining section 200 comprises a selection signal generating unit 210, a selecting unit 220, and a detecting unit 230. The determining section 200 further comprises a pulse generating unit 240 which is configured to receive the test mode signal TM and generate a test pulse TM_pulse. The pulse generating unit 240 comprises a general pulse generator which can generate the test pulse TM_pulse when the test mode signal TM is enabled.
  • The selection signal generating unit 210 receives the test pulse TM_pulse, the clock signal CLK and the reset signal RST. The selection signal generating unit 210 is initialized in response to the reset signal RST, and generates first through third selection signals S1, S2 and S3 in response to the test pulse TM_pulse and the clock signal CLK. The selection signal generating unit 210 generates the selection signals S1, S2 and S3 that are sequentially enabled, when the test pulse TM_pulse is inputted.
  • The selecting unit 220 connects the first through third TSVs TSV1, TSV2 and TSV3 to the detecting unit 230 in response to the selection signals S1, S2 and S3. More specifically, the selecting unit 220 sequentially connects the first through third TSVs TSV1, TSV2 and TSV3 to the detecting unit 230 in response to the selection signals S1, S2 and S3 that are sequentially enabled.
  • The detecting unit 230 is sequentially connected to the first through third TSVs TSV1, TSV2 and TSV3 by the selecting unit 220. When the detecting unit 230 is connected to the first through third TSVs TSV1, TSV2 and TSV3, the detecting unit 230 detects currents or voltages outputted through the first through third TSVs TSV1, TSV2 and TSV3.
  • In FIG. 3, the selection signal generating unit 210 comprises first through third flip-flops FF1, FF2 and FF3. The first through third flip-flops FF1, FF2 and FF3 are connected in series and respectively generate the selection signals S1, S2 and S3. The first flip-flop FF1 generates the first selection signal S1 in synchronization with the clock signal CLK when the test pulse TM_pulse is generated. The second flip-flop FF2 receives the first selection signal S1 and generates the second selection signal S2 in synchronization with the clock signal CLK. The third flip-flop FF3 receives the second selection signal S2 and generates the third selection signal S3 in synchronization with the clock signal CLK. Since the second and third flip-flops FF2 and FF3 respectively receive outputs of the first and second flip-flops FF1 and FF2, enabled intervals of the first through third selection signals S1, S2 and S3 do not overlap with one another and may be sequentially defined.
  • The selecting unit 220 comprises first through third pass gates PG1, PG2 and PG3. The first through third pass gates PG1, PG2 and PG3 are respectively connected to the second ends of the first through third TSVs TSV1, TSV2 and TSV3 and selectively transmit outputs of the second ends of the first through third TSVs. TSV1, TSV2 and TSV3. The first pass gate PG1 connects the second end of the first TSV TSV1 to the detecting unit 230 in response to the first selection signal S1 and an inverted signal of the first selection signal S1 that is inverted by a first inverter IV1. The second pass gate PG2 connects the second end of the second TSV TSV2 to the detecting unit 230 in response to the second selection signal S2 and an inverted signal of the second selection signal S2 that is inverted by a second inverter IV2. The third pass gate PG3 connects the second end of the third TSV TSV3 with the detecting unit 230 in response to the third selection signal S3 and an inverted signal of the third selection signal S3 that is inverted by a third inverter IV3.
  • The detecting unit 230 may comprise pads or differential amplifiers as shown in FIG. 1. The detecting unit 230 may be constructed in the same manner as the detecting unit 20 of FIG. 1 as described above.
  • If the determining section 200 is configured as described above, and if the test mode signal TM is enabled, the determining section 200 may be sequentially connected to the first through third TSVs TSV1, TSV2 and TSV3, detect the currents or voltages outputted through the first through third TSVs TSV1, TSV2 and TSV3, and determine at once whether the first through third TSVs are open or short-circuited.
  • FIG. 4 is a timing diagram showing operations of the test circuit shown in FIG. 2. The operations of the circuit for testing a semiconductor apparatus in accordance with the embodiment of the present invention are described below with reference to FIGS. 2-4.
  • First, if the reset signal RST is enabled, the determining section 200 is initialized. Thereafter, the test mode signal TM is enabled to start a testing operation for a semiconductor apparatus. If the test mode signal TM is enabled, the test voltage applying section 100 applies the test voltage Vtest to the first through third TSVs TSV1, TSV2 and TSV3.
  • If the test mode signal TM is enabled, the pulse generating unit 240 generates the test pulse TM_pulse. The first flip-flop FF1 of the selection signal generating section 210 latches the test pulse TM_pulse at the falling edge of the clock signal CLK and outputs the latched signal until the next falling edge of the clock signal CLK. Thus, the first flip-flop FF1 generates the first selection signal S1 that is enabled for one period of the clock signal CLK. Similarly, the second flip-flop FF2 receives the first selection signal S1 and generates the second selection signal S2 that is enabled for one period of the clock signal CLK, and the third flip-flop FF3 receives the second selection signal S2 and generates the third selection signal S3 that is enabled for one period of the clock signal CLK.
  • The first pass gate PG1 of the selecting unit 220 connects the first TSV TSV1 to the detecting unit 230 in response to the first selection signal S1. Similarly, the second pass gate PG2 of the selecting unit 220 connects the second TSV TSV2 to the detecting unit 230 in response to the second selection signal S2, and the third pass gate PG3 of the selecting unit 220 connects the third TSV TSV3 to the detecting unit 230 in response to the third selection signal S3. As shown in FIG. 4, the outputs of the first through third pass gates PG1, PG2 and PG3 are the currents outputted through the first through third TSVs TSV1, TSV2 and TSV3. Peak currents exist in the waveforms of the currents. Since the TSVs filled with a conductive material serve like capacitors before the pass gates PG1, PG2 and PG3 are turned on, peaks are produced at the moments the pass gates PG1, PG2 and PG3 are turned on.
  • When connected to the respective first through third TSVs TSV1, TSV2 and TSV3, the detecting unit 230 detects currents having flowed through the first through third TSVs TSV1, TSV2 and TSV3. Detecting intervals are shown in FIG. 4. It is preferred that detection timing be set to when a predetermined time has lapsed after the first selection signal S1 is enabled. As described above, if the first through third TSVs TSV1, TSV2 and TSV3 are connected to the detecting unit 230, peak currents are produced. Therefore, it is desirable to detect an amount of a current flowing through the TSV after the peak current vanishes to determine whether the TSV is properly connected. FIG. 4 shows amounts of currents that are detected by the detecting unit 230. Because the currents flowing through the first through third TSVs TSV1, TSV2 and TSV3 are detected by the detecting unit 230, that is, amounts of currents greater than a reference value, a determination may be made that all of the first through third TSVs TSV1, TSV2 and TSV3 are properly connected. If a detected amount of current is less than the reference value, a determination may be made that the corresponding TSV with the detected amount of current less than the reference value is not properly connected. An improperly connected TSV may then be replaced with a repair TSV.
  • As is apparent from the above description, in the present invention, whether a plurality of TSVs formed in a semiconductor apparatus are properly connected or not can be simultaneously tested. The test circuit according to one aspect of the present invention can detect a connection or disconnection of the TSVs in a precise and convenient manner. Also, in the present invention, a test time can be shortened and the reliability of the semiconductor apparatus improved.
  • While certain embodiments have been described above, it will be understood to those skilled in the art that the embodiments described are by way of example only. Accordingly, the circuit and the method for testing a semiconductor apparatus described herein should not be limited based on the described embodiments. Rather, the circuit and the method described herein should only be limited in light of the claims that follow when taken in conjunction with the above description and accompanying drawings.

Claims (20)

1. A circuit for testing a semiconductor apparatus, comprising:
a test voltage applying unit configured to apply a test voltage to a first end of a through-silicon via (TSV) in response to a test mode signal; and
a detecting unit configured to be connected to a second end of the TSV and detect a current outputted from the second end of the TSV.
2. The circuit according to claim 1, wherein the test voltage applying unit applies the test voltage to the first end of the TSV when the test mode signal is enabled.
3. A method of testing a semiconductor apparatus, comprising:
applying a current to a through-silicon via (TSV) during testing operation; and
comparing an amount of the current flowing through the TSV with a reference value.
4. The method according to claim 3, wherein the reference value is substantially identical to or less than a predetermined amount of current.
5. A circuit for testing a semiconductor apparatus, comprising:
a test voltage applying unit configured to apply a test voltage to a first end of a TSV in response to a test mode signal; and
a detection unit configured to be connected to a second end of the TSV, compare a voltage outputted from the second end of the TSV with a reference voltage, and generate a detection signal.
6. The circuit according to claim 5, wherein the test voltage applying unit applies the test voltage to the TSV when the test mode signal is enabled.
7. A circuit for testing a semiconductor apparatus, comprising:
a test voltage applying section configured to apply a test voltage to a plurality of through-silicon vias (TSVs) in response to a test mode signal; and
a determining section configured to be sequentially connected to one of the plurality of TSVs in response to the test mode signal.
8. The circuit according to claim 7, wherein the test voltage applying section applies the test voltage to the plurality of TSVs when the test mode signal is enabled.
9. The circuit according to claim 7, wherein the determining diction comprises:
a selection signal generating unit configured to generate a plurality of selection signals that are synchronized with a clock signal when the test mode signal is enabled;
a selecting unit configured to receive the plurality of selection signals; and
a detecting unit, and
wherein the selecting unit connects the plurality of TSVs to the detecting unit in response to the plurality of selection signals.
10. The circuit according to claim 9, wherein the selection signal generating unit generates the plurality of selection signals such that enabled intervals of the plurality of selection signals do not overlap with one another.
11. The circuit according to claim 9, wherein the selection signal generating unit comprises a plurality of flip-flops; and
wherein a first flip-flop receives the test mode signal and the clock signal, and each of the plurality of flip-flops remaining receives the clock signal and an output of an immediately previous flip-flop.
12. The circuit according to claim 9, wherein the selecting unit comprises a plurality of pass gates which connect the plurality of TSVs with the detecting unit in response to the plurality of selection signals.
13. The circuit according to claim 9, wherein the detecting unit detects a current outputted from each of the plurality of TSVs after a predetermined time when a corresponding selection signal is enabled.
14. A circuit for testing a semiconductor apparatus, comprising:
to a test voltage applying section configured to apply a test voltage to first and second through-silicon vias (TSVs) in response to a test mode signal; and
a determining section configured to be connected to the first and second TSVs in response to the test mode signal.
15. The circuit according to claim 14, wherein the test voltage applying section applies the test voltage to the first and second TSVs when the test mode signal is enabled.
16. The circuit according to claim 14, wherein intervals, during which the determining section is connected to the respective first and second TSVs, do not overlap with each other.
17. The circuit according to claim 14, wherein the determining section comprises:
a selection signal generating unit configured to generate first and second selection signals that are synchronized with a clock signal when the test mode signal is enabled;
a first selecting unit;
a second selecting unit; and
a detecting unit, and
wherein the first selecting unit connects the first TSV to the detecting unit when the first selection signal is enabled, and the second selecting unit connects the second TSV to the detecting unit when the second selection signal is enabled.
18. The circuit according to claim 17, wherein intervals of the first and second selection signals do not overlap with each other.
19. The circuit according to claim 17, wherein the selection signal generating unit comprises:
a first flip-flop configured to receive the test mode signal and the clock signal and generate the first selection signal; and
a second flip-flop configured to receive the clock signal and the first selection signal and generate the second selection signal.
20. The circuit according to claim 17, wherein the detecting unit detects a current outputted from the first TSV after a predetermined time when the first selection signal is enabled, and detects a current outputted from the second TSV after the predetermined time when the second selection signal is enabled.
US12/651,066 2009-10-29 2009-12-31 Circuit and method for testing semiconductor apparatus Abandoned US20110102006A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2009-0103598 2009-10-29
KR1020090103598A KR101094916B1 (en) 2009-10-29 2009-10-29 Test circuit and method for semiconductor apparatus

Publications (1)

Publication Number Publication Date
US20110102006A1 true US20110102006A1 (en) 2011-05-05

Family

ID=43924726

Family Applications (1)

Application Number Title Priority Date Filing Date
US12/651,066 Abandoned US20110102006A1 (en) 2009-10-29 2009-12-31 Circuit and method for testing semiconductor apparatus

Country Status (3)

Country Link
US (1) US20110102006A1 (en)
KR (1) KR101094916B1 (en)
CN (1) CN102053207A (en)

Cited By (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120242367A1 (en) * 2011-03-22 2012-09-27 Taiwan Semiconductor Manufacturing Co., Ltd. Circuits and methods for testing through-silicon vias
US20120274348A1 (en) * 2011-04-27 2012-11-01 Hynix Semiconductor Inc. Test circuit and method of semiconductor integrated circuit
US20130006557A1 (en) * 2011-06-29 2013-01-03 Duke University METHOD AND ARCHITECTURE FOR PRE-BOND PROBING OF TSVs IN 3D STACKED INTEGRATED CIRCUITS
WO2013040285A2 (en) * 2011-09-15 2013-03-21 International Business Machines Corporation Leakage measurement of through silicon vias
US20130093455A1 (en) * 2011-10-18 2013-04-18 Texas Instruments Incorporated Tsv testing method and apparatus
CN103063976A (en) * 2012-12-28 2013-04-24 中国科学院深圳先进技术研究院 Method and system of fault detection of silicon through holes by using bisection method
US20130230932A1 (en) * 2012-03-02 2013-09-05 Venkatraghavan Bringivijayaraghavan Through-substrate via (tsv) testing
WO2014003793A1 (en) * 2012-06-29 2014-01-03 Intel Corporation Charge sharing testing of through-body-vias
US20140014957A1 (en) * 2012-07-12 2014-01-16 SK Hynix Inc. Semiconductor device including a structure for screening connectivity of a tsv
US20140043057A1 (en) * 2012-08-08 2014-02-13 SK Hynix Inc. Semiconductor apparatus and test method thereof
US8704225B2 (en) * 2011-12-16 2014-04-22 SK Hynix Inc. Semiconductor integrated circuit
CN103794598A (en) * 2014-02-28 2014-05-14 上海集成电路研发中心有限公司 Through-silicon-via test map, through-silicon-via test structure, manufacturing method and measuring method
US8806400B1 (en) 2013-01-21 2014-08-12 Qualcomm Incorporated System and method of testing through-silicon vias of a semiconductor die
US20140225624A1 (en) * 2013-02-14 2014-08-14 Duke University Non-invasive pre-bond tsv test using ring oscillators and multiple voltage levels
US20140368224A1 (en) * 2013-06-18 2014-12-18 SK Hynix Inc. Test circuit and method for semiconductor device
US20150123698A1 (en) * 2011-04-27 2015-05-07 SK Hynix Inc. Test circuit and method of semiconductor integrated circuit
US20150293168A1 (en) * 2014-04-15 2015-10-15 SK Hynix Inc. Semiconductor device
US20160163607A1 (en) * 2014-12-05 2016-06-09 SK Hynix Inc. Semiconductor device, semiconductor system and method of testing semiconductor device
US9383403B2 (en) 2012-03-20 2016-07-05 Texas Instruments Incorporated TSVs connected to ground and combined stimulus and testing leads
US9471540B2 (en) 2013-01-03 2016-10-18 International Business Machines Corporation Detecting TSV defects in 3D packaging
US20160364309A1 (en) * 2015-06-12 2016-12-15 SK Hynix Inc. Input/output (i/o) line test device and method for controlling the same
US9570196B2 (en) 2011-09-01 2017-02-14 Rambus Inc. Testing through-silicon-vias
KR101747191B1 (en) 2011-01-14 2017-06-14 에스케이하이닉스 주식회사 Semiconductor Apparatus
US20180226307A1 (en) * 2017-01-31 2018-08-09 Stmicroelectronics S.R.L. SYSTEM AND METHOD FOR ELECTRICAL TESTING OF THROUGH SILICON VIAS (TSVs)
WO2020093946A1 (en) * 2018-11-09 2020-05-14 Changxin Memory Technologies, Inc. Through-silicon via detecting circuit, detecting methods and integrated circuit thereof
US10775426B2 (en) 2010-02-16 2020-09-15 Stmicroelectronics S.R.L. System and method for electrical testing of through silicon vias (TSVs)
US10796974B2 (en) * 2011-12-19 2020-10-06 Texas Instruments Incorporated Scan testable through silicon VIAs

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103165577B (en) * 2011-12-08 2016-08-31 中芯国际集成电路制造(上海)有限公司 Semiconductor detection structure and detection method
CN103187398B (en) * 2011-12-30 2015-12-16 中芯国际集成电路制造(上海)有限公司 Silicon through hole detection architecture and detection method
KR101902938B1 (en) * 2012-02-14 2018-11-13 에스케이하이닉스 주식회사 Semiconductor integrated circuit
KR101891163B1 (en) 2012-04-04 2018-08-24 에스케이하이닉스 주식회사 Test circuit and semiconductor apparatus including the same
KR102124966B1 (en) 2013-08-30 2020-06-22 에스케이하이닉스 주식회사 Semiconductor device and operating method of the same
KR101524409B1 (en) * 2014-06-13 2015-05-29 호서대학교 산학협력단 3D IC tester
CN105445653B (en) * 2014-09-29 2019-11-08 恩智浦美国有限公司 Integrated circuit with low power scan trigger
KR102373541B1 (en) * 2015-08-31 2022-03-11 삼성전자주식회사 Semiconductor apparatus, stacked semiconductor apparatus and test method thereof
CN105470240B (en) * 2015-11-23 2018-04-17 北京大学深圳研究生院 The test circuit and method of silicon hole group in silicon hole and three dimensional integrated circuits
KR20200056639A (en) 2018-11-15 2020-05-25 에스케이하이닉스 주식회사 Stacked semiconductor device and test method thereof
KR20210006815A (en) 2019-07-09 2021-01-19 에스케이하이닉스 주식회사 Semiconductor device including test circuit
CN111812480B (en) * 2020-07-21 2023-06-06 盐城东山精密制造有限公司 Detection method for metal migration resistance of LED particles
US11698409B2 (en) 2021-07-22 2023-07-11 Changxin Memory Technologies, Inc. Test method and system for testing connectivity of semiconductor structure
CN113702811A (en) * 2021-09-02 2021-11-26 西安紫光国芯半导体有限公司 Chip, detection method thereof and chip system

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6680484B1 (en) * 2002-10-22 2004-01-20 Texas Instruments Incorporated Space efficient interconnect test multi-structure
US6784685B2 (en) * 2001-07-31 2004-08-31 Xilinx, Inc. Testing vias and contacts in an integrated circuit
US20070285104A1 (en) * 2004-09-02 2007-12-13 Francisco Cano Semiconductor Device Testing
US20090032928A1 (en) * 2007-07-31 2009-02-05 Siliconware Precision Industries Co., Ltd. Multi-chip stack structure having through silicon via and method for fabrication the same
US20090135638A1 (en) * 2007-11-22 2009-05-28 Yuui Shimizu Semiconductor memory device capable of identifying a plurality of memory chips stacked in the same package
US7541203B1 (en) * 2008-05-13 2009-06-02 International Business Machines Corporation Conductive adhesive for thinned silicon wafers with through silicon vias
US20090168545A1 (en) * 2007-12-27 2009-07-02 Sung Kun Park Semiconductor Device and Method of Fabricating the Same
US7598523B2 (en) * 2007-03-19 2009-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Test structures for stacking dies having through-silicon vias
US20100013512A1 (en) * 2008-07-15 2010-01-21 Micron Technology, Inc. Apparatus and methods for through substrate via test

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003014819A (en) 2001-07-03 2003-01-15 Matsushita Electric Ind Co Ltd Semiconductor wiring board, semiconductor device, test method therefor and mounting method therefor
JP2004264057A (en) 2003-02-12 2004-09-24 Sharp Corp Boundary scan controller, semiconductor device, and method for identifying and controlling semiconductor circuit chip of semiconductor device

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6784685B2 (en) * 2001-07-31 2004-08-31 Xilinx, Inc. Testing vias and contacts in an integrated circuit
US6680484B1 (en) * 2002-10-22 2004-01-20 Texas Instruments Incorporated Space efficient interconnect test multi-structure
US20070285104A1 (en) * 2004-09-02 2007-12-13 Francisco Cano Semiconductor Device Testing
US7598523B2 (en) * 2007-03-19 2009-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Test structures for stacking dies having through-silicon vias
US20090032928A1 (en) * 2007-07-31 2009-02-05 Siliconware Precision Industries Co., Ltd. Multi-chip stack structure having through silicon via and method for fabrication the same
US20090135638A1 (en) * 2007-11-22 2009-05-28 Yuui Shimizu Semiconductor memory device capable of identifying a plurality of memory chips stacked in the same package
US20090168545A1 (en) * 2007-12-27 2009-07-02 Sung Kun Park Semiconductor Device and Method of Fabricating the Same
US7541203B1 (en) * 2008-05-13 2009-06-02 International Business Machines Corporation Conductive adhesive for thinned silicon wafers with through silicon vias
US20100013512A1 (en) * 2008-07-15 2010-01-21 Micron Technology, Inc. Apparatus and methods for through substrate via test

Cited By (66)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10775426B2 (en) 2010-02-16 2020-09-15 Stmicroelectronics S.R.L. System and method for electrical testing of through silicon vias (TSVs)
KR101747191B1 (en) 2011-01-14 2017-06-14 에스케이하이닉스 주식회사 Semiconductor Apparatus
US20120242367A1 (en) * 2011-03-22 2012-09-27 Taiwan Semiconductor Manufacturing Co., Ltd. Circuits and methods for testing through-silicon vias
US8436639B2 (en) * 2011-03-22 2013-05-07 Taiwan Semiconductor Manufacturing Co., Ltd. Circuits and methods for testing through-silicon vias
US20120274348A1 (en) * 2011-04-27 2012-11-01 Hynix Semiconductor Inc. Test circuit and method of semiconductor integrated circuit
US20150123698A1 (en) * 2011-04-27 2015-05-07 SK Hynix Inc. Test circuit and method of semiconductor integrated circuit
US9322868B2 (en) * 2011-04-27 2016-04-26 SK Hynix Inc. Test circuit and method of semiconductor integrated circuit
US20130006557A1 (en) * 2011-06-29 2013-01-03 Duke University METHOD AND ARCHITECTURE FOR PRE-BOND PROBING OF TSVs IN 3D STACKED INTEGRATED CIRCUITS
US8775108B2 (en) * 2011-06-29 2014-07-08 Duke University Method and architecture for pre-bond probing of TSVs in 3D stacked integrated circuits
US11600349B2 (en) 2011-09-01 2023-03-07 Rambus Inc. Testing through-silicon-vias
US10262750B2 (en) 2011-09-01 2019-04-16 Rambus Inc. Testing through-silicon-vias
US9570196B2 (en) 2011-09-01 2017-02-14 Rambus Inc. Testing through-silicon-vias
US11004530B2 (en) 2011-09-01 2021-05-11 Rambus Inc. Testing through-silicon-vias
WO2013040285A3 (en) * 2011-09-15 2013-05-10 International Business Machines Corporation Leakage measurement of through silicon vias
US8692246B2 (en) 2011-09-15 2014-04-08 International Business Machines Corporation Leakage measurement structure having through silicon vias
GB2508122B (en) * 2011-09-15 2014-10-29 Ibm Leakage measurement of through silicon vias
GB2508122A (en) * 2011-09-15 2014-05-21 Ibm Leakage measurement of through silicon vias
WO2013040285A2 (en) * 2011-09-15 2013-03-21 International Business Machines Corporation Leakage measurement of through silicon vias
US10324125B2 (en) 2011-10-18 2019-06-18 Texas Instruments Incorporated TSV testing method and apparatus
US9835678B2 (en) 2011-10-18 2017-12-05 Texas Instruments Incorporated Through substrate via scan cell with comparator mux, and flip-flop
US11835573B2 (en) 2011-10-18 2023-12-05 Texas Instruments Incorporated TSV testing method and apparatus
US20130093455A1 (en) * 2011-10-18 2013-04-18 Texas Instruments Incorporated Tsv testing method and apparatus
US11237206B2 (en) 2011-10-18 2022-02-01 Texas Instruments Incorporated TSV testing method and apparatus
US9081064B2 (en) * 2011-10-18 2015-07-14 Texas Instruments Incorporated IC scan cell coupled to TSV top and bottom contacts
US10969423B2 (en) 2011-10-18 2021-04-06 Texas Instruments Incorporated Switch coupling functional circuitry to via, scan cell contacting via
US9362188B2 (en) * 2011-10-18 2016-06-07 Texas Instruments Incorporated TSV scan cell comparator coupled to voltage reference and response
US8704225B2 (en) * 2011-12-16 2014-04-22 SK Hynix Inc. Semiconductor integrated circuit
US11302591B2 (en) * 2011-12-19 2022-04-12 Texas Instruments Incorporated Scan testable through silicon VIAs
US10796974B2 (en) * 2011-12-19 2020-10-06 Texas Instruments Incorporated Scan testable through silicon VIAs
US9157960B2 (en) * 2012-03-02 2015-10-13 Micron Technology, Inc. Through-substrate via (TSV) testing
US20160027706A1 (en) * 2012-03-02 2016-01-28 Micron Technology, Inc. Through-substrate via (tsv) testing
US9929064B2 (en) * 2012-03-02 2018-03-27 Micron Technology, Inc. Through-substrate via (TSV) testing
US20130230932A1 (en) * 2012-03-02 2013-09-05 Venkatraghavan Bringivijayaraghavan Through-substrate via (tsv) testing
US10901034B2 (en) 2012-03-20 2021-01-26 Texas Instruments Incorporated TSVS, test circuits, scan cells, comparators, electrical source, and resistor
US9880222B2 (en) 2012-03-20 2018-01-30 Texas Instruments Incorporated Testing TSV with current/voltage source, resistor, comparator, and scan cell
US9383403B2 (en) 2012-03-20 2016-07-05 Texas Instruments Incorporated TSVs connected to ground and combined stimulus and testing leads
US11467210B2 (en) 2012-03-20 2022-10-11 Texas Instruments Incorporated TSV testing using test circuits and grounding means
US10605866B2 (en) 2012-03-20 2020-03-31 Texas Instruments Incorporated IC TSV scan cells with sensed and reference voltage inputs
US10267856B2 (en) 2012-03-20 2019-04-23 Texas Instruments Incorporated TSV first ends connected to test stimulus and response signals
US11644503B2 (en) 2012-03-20 2023-05-09 Texas Instruments Incorporated TSV testing using test circuits and grounding means
US9513330B2 (en) 2012-06-29 2016-12-06 Intel Corporation Charge sharing testing of through-body-vias
WO2014003793A1 (en) * 2012-06-29 2014-01-03 Intel Corporation Charge sharing testing of through-body-vias
KR101965906B1 (en) 2012-07-12 2019-04-04 에스케이하이닉스 주식회사 Semiconductor device
US9281262B2 (en) * 2012-07-12 2016-03-08 Sk Hynix Semiconductor device including a structure for screening connectivity of a TSV
US20140014957A1 (en) * 2012-07-12 2014-01-16 SK Hynix Inc. Semiconductor device including a structure for screening connectivity of a tsv
KR20140008866A (en) * 2012-07-12 2014-01-22 에스케이하이닉스 주식회사 Semiconductor device
US9188626B2 (en) * 2012-08-08 2015-11-17 SK Hynix Inc. Semiconductor apparatus and test method thereof
US20140043057A1 (en) * 2012-08-08 2014-02-13 SK Hynix Inc. Semiconductor apparatus and test method thereof
CN103063976A (en) * 2012-12-28 2013-04-24 中国科学院深圳先进技术研究院 Method and system of fault detection of silicon through holes by using bisection method
US9471540B2 (en) 2013-01-03 2016-10-18 International Business Machines Corporation Detecting TSV defects in 3D packaging
US8806400B1 (en) 2013-01-21 2014-08-12 Qualcomm Incorporated System and method of testing through-silicon vias of a semiconductor die
US9482720B2 (en) * 2013-02-14 2016-11-01 Duke University Non-invasive pre-bond TSV test using ring oscillators and multiple voltage levels
US20140225624A1 (en) * 2013-02-14 2014-08-14 Duke University Non-invasive pre-bond tsv test using ring oscillators and multiple voltage levels
US10444279B2 (en) 2013-02-14 2019-10-15 Duke University Non-invasive pre-bond TSV test using ring oscillators and multiple voltage levels
US9702931B2 (en) * 2013-06-18 2017-07-11 SK Hynix Inc. Test circuit and method for semiconductor device
US20140368224A1 (en) * 2013-06-18 2014-12-18 SK Hynix Inc. Test circuit and method for semiconductor device
CN103794598A (en) * 2014-02-28 2014-05-14 上海集成电路研发中心有限公司 Through-silicon-via test map, through-silicon-via test structure, manufacturing method and measuring method
US9607925B2 (en) * 2014-04-15 2017-03-28 SK Hynix Inc. Semiconductor device for verifying operation of through silicon vias
US20150293168A1 (en) * 2014-04-15 2015-10-15 SK Hynix Inc. Semiconductor device
US20160163607A1 (en) * 2014-12-05 2016-06-09 SK Hynix Inc. Semiconductor device, semiconductor system and method of testing semiconductor device
US20160364309A1 (en) * 2015-06-12 2016-12-15 SK Hynix Inc. Input/output (i/o) line test device and method for controlling the same
US9959184B2 (en) * 2015-06-12 2018-05-01 SK Hynix Inc. Input/output (I/O) line test device and method for controlling the same
US20180226307A1 (en) * 2017-01-31 2018-08-09 Stmicroelectronics S.R.L. SYSTEM AND METHOD FOR ELECTRICAL TESTING OF THROUGH SILICON VIAS (TSVs)
WO2020093946A1 (en) * 2018-11-09 2020-05-14 Changxin Memory Technologies, Inc. Through-silicon via detecting circuit, detecting methods and integrated circuit thereof
US20210239751A1 (en) * 2018-11-09 2021-08-05 Changxin Memory Technologies, Inc. Through-silicon via detecting circuit, detecting methods and integrated circuit thereof
US11614481B2 (en) * 2018-11-09 2023-03-28 Changxin Memory Technologies, Inc. Through-silicon via detecting circuit, detecting methods and integrated circuit thereof

Also Published As

Publication number Publication date
KR101094916B1 (en) 2011-12-15
KR20110046894A (en) 2011-05-06
CN102053207A (en) 2011-05-11

Similar Documents

Publication Publication Date Title
US20110102006A1 (en) Circuit and method for testing semiconductor apparatus
US9671457B2 (en) 3D IC testing apparatus
US9208898B2 (en) Semiconductor device and operating method of semiconductor device
US11327109B2 (en) Stacked semiconductor device and test method thereof
US9588174B1 (en) Method for testing through silicon vias in 3D integrated circuits
US20070200571A1 (en) Verifying individual probe contact using shared tester channels
US20120274348A1 (en) Test circuit and method of semiconductor integrated circuit
US20140266291A1 (en) Method, device and system for automatic detection of defects in tsv vias
US9607925B2 (en) Semiconductor device for verifying operation of through silicon vias
US11476169B2 (en) Semiconductor chips including through electrodes and methods of testing the through electrodes
KR20150073635A (en) Stack chip and testing method thereof
US20140347088A1 (en) Method and Circuit Of Pulse-Vanishing Test
US9043662B2 (en) Double data rate memory physical interface high speed testing using self checking loopback
TW201346296A (en) System and method for testing off-chip driver impedance
US20150123698A1 (en) Test circuit and method of semiconductor integrated circuit
US9720041B2 (en) Scan-based test architecture for interconnects in stacked designs
Rodríguez-Montañés et al. Post-bond test of Through-Silicon Vias with open defects
TWI569022B (en) Test system
US20140062523A1 (en) Semiconductor apparatus and test method thereof
US20130153899A1 (en) Semiconductor device having plural semiconductor chips
TWI447413B (en) Test interface of circuit and test method therefor
US20140043057A1 (en) Semiconductor apparatus and test method thereof
US9761288B2 (en) Memory circuit and stack type memory system including the same
TWI809160B (en) Method for wafer-level testing and system for testing semiconductor device
US20160299190A1 (en) Semiconductor apparatus and test method thereof

Legal Events

Date Code Title Description
AS Assignment

Owner name: HYNIX SEMICONDUCTOR INC., KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHOI, MIN SEOK;LEE, JONG CHERN;BYEON, SANG JIN;AND OTHERS;SIGNING DATES FROM 20091220 TO 20100222;REEL/FRAME:024880/0469

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION