KR101524409B1 - 3D IC tester - Google Patents

Abstract

The present invention relates to a 3D IC tester which can recognize minute signal delay from outside easily, does not require complex on-chip or signal analysis process, and can detect TSV which is failed in Pre-bond phase or has a high probability of failure preliminarily and includes an on-chip TSV tester (OTT) mounted to each laminated dicing of a through silicon via (TSV), wherein the OTT comprises: D flip-flop connected to an output terminal of the TSV to receive output signals of the TSV as input signals; a lifting edge reference cluck to detect lifting or dropping edge of input signals inputted to the TSV, and being delayed based on the lifting edge detected; and a cluck generator to generate dropping edge reference cluck which is a delayed cluck based on the dropping edge, generate D flip-flop which is a logical add (OR) of the lifting edge reference cluck and the dropping edge reference cluck and provide it to D flip-flop.

Description

A three-dimensional semiconductor test apparatus (3D IC tester)

The present invention relates to a three-dimensional semiconductor test apparatus, and more particularly, to a test apparatus for a three-dimensional semiconductor, which can easily recognize whether a fine signal is delayed from the outside and does not require a complicated on-chip circuit or signal analysis process, And more particularly, to a three-dimensional semiconductor test apparatus capable of detecting a TSV having a high probability of occurrence or failure.

A three-dimensional semiconductor is a new type of semiconductor fabrication technology in which a die (chip) is stacked up and down. The stacked dies are connected by a wire bonding method or a through silicon via (TSV) method as shown in FIG. 1. The method using a TSV having excellent electrical characteristics and without limitation of lamination is mainly used Has come.

Since the size of the available silicon area increases in proportion to the number of layers in the three-dimensional semiconductor, it is possible to design an ultra-high density, and by using the TSV as a connection line, the length of the connection line between the circuits can be reduced, Reduction of components and reduction of power consumption. In addition, most of the remaining processes except TSV formation and die laminating can be economically effective because existing semiconductor processes can be recycled.

To test these 3D semiconductors, complicated and many steps are required compared to 2D semiconductors, and the efficiency of detecting faults in the initial stage has a large ripple effect on the total production cost. If the defective die is stacked without being detected beforehand, it is necessary to discard all of the stacked layers, so that the loss increases exponentially.

However, in the past, in many cases, it is difficult to grasp the voids generated in the inside by performing only the apparent inspection such as destructive inspection and laser inspection from an external inspection machine, and since expensive inspection equipment must be provided, .

Therefore, it has become necessary to develop a three-dimensional semiconductor test apparatus which can secure reliability, does not go through a complicated signal analysis process, and has a low manufacturing cost.

KR10-0338194 (registration number) 2002.05.14

An object of the present invention is to provide a test apparatus for a three-dimensional semiconductor which can easily recognize from outside by using a D flip-flop output signal whether or not a fine signal is delayed.

It is another object of the present invention to provide a test apparatus for a three-dimensional semiconductor which does not require a complicated on-chip circuit or a signal analysis process.

Another object of the present invention is to provide a test apparatus for a three-dimensional semiconductor in which a failure has occurred in the pre-bond step and a TSV having a high failure probability can be detected in advance.

The present invention comprises OTT (On-chip TSV Tester: on-chip silicon through-hole via tester) mounted on each stacked layer of a TSV (Through Silicon Via) A D flip flop connected to an output terminal of the TSV and receiving an output signal of the TSV as an input signal; Generates a rising edge reference clock which is a delayed clock based on the detected rising edge and a falling edge reference clock which is a delayed clock based on the falling edge, And a clock generator for generating a D flip-flop clock which is a logical sum of the rising edge reference clock and the falling edge reference clock and providing the D flip-flop clock to the D flip-flop.

The clock generator of the present invention changes the delay time of the D flip-flop clock until the output signal of the D flip-flop is periodically repeated with the same width as the input signal of the TSV, The time obtained by subtracting the set-up time of the D flip-flop from the D flip-flop clock delay time at that time is set to a value obtained by multiplying the time of the TSV The final delay time.

In addition, the present invention further includes an analyzer for receiving a final delay time of the clock generator, an output signal of the D flip-flop, and an input signal input to the TSV, for each TSV.

In addition, the analyzing apparatus of the present invention compares the final delay time inputted for each of the TSVs, and judges that the TSV having a delay time that is more delayed than the no-fault state is a defect.

The analyzer of the present invention compares the output signal of the D flip-flop according to the output signal of each TSV to compare the output signal of the D flip-flop with the output of the D flip- A fast or slow TSV is judged to be defective.

The analyzing apparatus of the present invention is characterized in that when the output signal of the D flip-flop is faster than the output of the D flip-flop in accordance with the output of the TSV in a non-fault state, It is judged to be a pinhole defect as early as possible.

In the present invention, the D flip-flop 110 is disposed at the TSV signal output terminal and the input signal of the TSV is delayed and used as the trigger signal of the D flip-flop 110, There is an effect that can be easily recognized from the outside using a signal.

Further, since the present invention does not require a complicated on-chip circuit or a signal analysis process, the present invention can be implemented through a simple scan structure.

Further, the present invention has an effect that the test cost can be greatly reduced since a TSV having a failure or a high failure probability can be detected in advance at the pre-bonding step.

1 is a view illustrating a method of stacking a 3D semiconductor.
2 is an illustration of a TSV equivalent circuit of a three-dimensional semiconductor test apparatus according to an embodiment of the present invention.
3 is a TSV simulation circuit of a test apparatus for a three-dimensional semiconductor according to an embodiment of the present invention.
4 is a simulation result of an output signal at the time of rising of an input signal to the equivalent circuit of FIG.
5 is a simulation result of an output signal when the input signal falls to the equivalent circuit of FIG.
6 is a TSV failure detection circuit of a three-dimensional semiconductor test apparatus according to an embodiment of the present invention.
7 is a graph showing a clock generation method for a D flip-flop of a test device for a three-dimensional semiconductor according to an embodiment of the present invention.
FIG. 8 is a graph showing a variation of a TSV monitor signal according to a D flip-flop delay time of a three-dimensional semiconductor test apparatus according to an embodiment of the present invention.
9 is a graph showing a change in a TSV monitor signal according to a change in a D flip-flop delay time of a three-dimensional semiconductor test apparatus according to an embodiment of the present invention.
10 is a block diagram of an OTT of a test device for a three-dimensional semiconductor according to an embodiment of the present invention.
11 is a block diagram showing a pre-bonded TSV test method of a test apparatus for a three-dimensional semiconductor according to an embodiment of the present invention.
FIG. 12 is a timing chart showing an operation process of an OTT of a three-dimensional semiconductor test apparatus according to an embodiment of the present invention; FIG.
13 is a block diagram showing a method of testing a post-bond TSV of a test apparatus for a three-dimensional semiconductor according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The present invention comprises OTT (On-chip TSV Tester: On-chip TSV 100) mounted on each stacked layer of TSV (Through Silicon Via) A D flip flop 110 connected to an output terminal of the TSV, a clock generator 120 generating a clock signal of the D flip flop 110 by delaying an input signal of the TSV, And a clock selector for selecting a clock of the flop (110). In addition, the present invention further includes an analyzing apparatus for receiving the output signal of the D flip-flop 110 and the input signal inputted to the TSV for each TSV.

First, prior to the description of each component of the present invention, the defect type of the TSV can be classified into a defect occurring in the process of forming the TSV and a defect occurring in the bonding process. Defects in TSV formation process are mainly caused by imperfect TSV frame formation and plating process. Voids filled in the voids or unintentional pinch-off formed in the plating when the inside of the TSV is plated with a conductor such as copper increase the resistance of the TSV and occasionally cause an open failure . On the other hand, the defects generated in the bonding process are defects that occur when insulating between the TSV and the wafer is performed using silicon dioxide (SiO ₂ ). For example, pin-holes causing short defects are generated. There is a defect. Also, defects are generated in the difference in thermal expansion of copper, silicon, and silicon dioxide used in the TSV process. This nonuniform application of dielectric materials, contamination due to impurities, and bridging problems due to insulator defects can all be modeled as resistive shorts, which degrade the voltage level with signal delay. Also, even if there is no failure during TSV formation, TSV malfunction may occur due to mechanical wear or deterioration of IV characteristics during wafer thinning process.

In other words, the failure of TSV can be summarized mainly as two types of resistive failure and capacitive failure, and this resistive failure and capacitive failure cause a temporal error of the transmission signal.

Generally, for this resistive failure and capacitive failure, modeling of the RLCG transmission line equivalent circuit type is preferable, but in some cases, it can be simplified to the RC model shown in FIG.

According to Fig. 2, Fig. 2 (a) shows a non-fault condition and acts like a capacitor due to the insulating layer between the TSV conductor and the substrate.

However, as shown in FIG. 2 (b), if a void is generated in the TSV, the resistance component increases, and the two capacitors are connected in parallel to each other before and after the void position.

On the other hand, when a leakage current is generated due to a pinhole defect, which is a fine defect in the insulating layer, as shown in FIG. 2 (c), the same operation as a resistance is connected between the TSV and the substrate.

In order to simulate the state of no-fault, void defect, and pinhole defect of the TSV, first, each TSV is set to a TSV equivalent circuit as shown in FIG. 4 shows the output signals of the respective TSVs when the input signal rises from 0 V to 1.2 V, and FIG. 5 shows the output signals of the respective TSVs when the input signal falls from 1.2 V to 0 V. FIG. 4 and 5, Vin represents an input signal, Vout0 represents an output signal of a non-faulting TSV, Vout10 represents an output signal of a TSV in which a void defect occurs, and Vout20 represents an output signal of a TSV in which a pinhole defect occurs. The resistance value was set to 3 KΩ and the capacitance was set to 59 fF. The position where the void is generated is assumed to be the center of the TSV, and x = 0.5 is set.

For void defects, the reduced capacitance results in faster charge / discharge times compared to non-faulted TSVs. In Fig. 4, the rise time of Vout10 is faster than Vout0, and in Fig. 5, it can be seen that the fall time of Vout10 is faster than Vout0.

However, in the case of a pinhole defect, the added resistor R _L increases the charge time of the capacitor but reduces the discharge time. In FIG. 4, the rise time of Vout20 is slower than Vout0, but it can be seen that the fall time of Vout20 is faster than Vout0 in FIG.

From the charging / discharging time characteristic of the void defect and the pinhole defect, in the present invention, a TSV failure detecting circuit as shown in Fig. 6 is constructed in order to discriminate the failure of the TSV. The TSV failure detection circuit of the present invention adds a D flip flop 110 to the TSV output terminal and generates a clock for controlling the D flip flop 110 using the input signal of the TSV. The D flip-flop 110 receives a signal output from the TSV at each clock rising edge and outputs the signal as a final TSV monitor signal. The clock signal of the D flip-flop 110 is input to the input signal edge of the TSV Standards.

A clock signal clk0 delayed by a predetermined time is generated based on a rising edge of the input signal Vin and a clock signal clk1 delayed by a predetermined time is generated based on a falling edge of the input signal Vin. A D flip-flop clock dffclk, which is an OR clock of the rising edge reference clock clk0 and the falling edge reference clock clk1, is generated and input to the D flip-flop 110 as a clock signal, Flop 110 to process the input data after a certain period of time on the basis of the rising and falling edges of the input signal Vin.

The TSV monitor signal that is finally output according to the delay time from the input signal edge to the flip-flop clock (dffclk) differs depending on whether the TSV is faulty or defective.

8, the TSV monitor signal of each TSV output signal (Voutx0: x is 10 digits of Vout10 and Vout20) is represented by Voutx1 (x is 10 digits of Vout10 and Vout20). 8 (a), the D flip-flop clock dffclk generated by the rising edge reference clock clk0 is delayed from the latest Vout20 among the TSV output signals Vout0, Vout10, and Vout20 of FIG. 4 When the time difference between Vout20 and the D flip-flop clock dffclk is smaller than the setup time of the flip-flop in the same or larger state, the output signal Vout21 of the flip-flop is different from the output signal of Vout0 and Vout10. That is, when a clock of the D flip-flop 110 is generated after the change of Voutx0, a change of Voutx1 occurs. When the time of Voutx0 changes and the clock of the D flip-flop 110 is simultaneously generated, or Voutx0 changes The D flip-flop 110 does not recognize a change in Voutx0 (setup time violation) when the interval between the D flip-flop 110 and the D flip-flop 110 is shorter than the setup time of the D flip- The output signal without periodicity is generated.

8 (b), the time difference between the D flip-flop clock dffclk by the falling edge reference clock clk1 and the latest Vout0 among the output signals of Fig. 5 is smaller than the set-up time of the flip-flop The final output signal Vout1 for Vout0 is different from the final output signals Vout11 and Vout21 for Vout10 and Vout20.

9 shows a result of changing the delay time of the D flip-flop clock dffclk in units of 5 ps in order to observe the change of the flip-flop output signal when the input signal rises. It can be confirmed through the TSV monitor signal Vout21 whether an abnormality of the TSV output signal Vout20 in which a pinhole defect has occurred can be confirmed and that the waveform can be subdivided according to the D flip-flop clock dffclk delay time. Thus, it is only necessary to check whether the output signal of each D flip-flop 110 is periodic and the width thereof is the same as the TSV input signal while delaying the D flip-flop clock dffclk with respect to the edge of the input signal. If a stable periodic signal is detected, the time obtained by subtracting the D flip-flop 110 setup time from the D flip-flop clock delay time at that time becomes the final delay time of the corresponding TSV signal. If the last delay time of the TSV generated when the input signal rises or falls is grouped, the type and degree of the generated defect can be predicted.

In other words, if the charge / discharge time of the void defect is higher than that of the normal state VTS output signal and the discharge time is faster than that of the pinhole defect, the following prediction can be made . In the rising edge reference clock clk0, the pinhole defect rises at a later timing than normal. Therefore, in the case of the pinhole defect, the rising edge reference clock clk0 does not change at the normal delay time. Therefore, in the case of a pinhole defect, the rising edge reference clock clk0 must be delayed more than the normal time to obtain the periodicity of the output signal, and the final delay time is increased. Therefore, when the delay time is longer than that of the normal D flip-flop clock dffclk, it can be regarded as a pinhole defect.

 In addition, even if the output signal of the D flip-flop 110 has a periodicity, when comparing the signals, an output signal that precedes both the rising and falling edges as compared to the non-fault state is a void defect, falling back at the rising edge, The output signal can be identified by a pinhole defect, and the degree of the defect can be predicted through the degree of the leading or lagging of the signal.

As described above, whether or not the TSV is malfunctioning can be confirmed through the periodicity of the signal output from the D flip-flop 110, and the type and degree of the TSV defect can be predicted through mutual comparison of the signals.

In order to test a defect of the TSV according to the above-described principle, the present invention comprises a D flip-flop 110 connected to the output terminal of the TSV, and a clock signal of the D flip-flop 110 by delaying the input signal of the TSV And an OTT 100 including a clock selector 120 for selecting an input signal of the TSV and a clock selector for selecting a clock of the D flip-flop. The present invention further includes an analyzing device connected to the OTT 100 from the outside, so that the final delay time generated by the clock generator 120, the output signal from the D flip-flop 110, the output from the TSV Signal and the like, and analyze the TSV by the above-described method.

In other words, the OTT 100 is an on-chip circuit inserted one by one for each TSV as shown in FIG. 11, and if the OTT 100 is inserted for each TSV, the circuit area increases, but the period of each TSV input / There is an advantage that an abnormality of a signal can be easily confirmed. Also, OTT 100 according to TSV can reduce the number of external input / output signals by connecting each flip-flop in series like a scan structure.

The input / output signals of the OTT 100 are shown in FIG. 10, which is summarized as follows.

set and clr are initialization signals of the D flip-flop 110, set sets the output of the D flip-flop 110 to 1, and clr makes the output of the D flip-flop 110 zero.

tsv_in is a signal input via the TSV and an output signal of the side TSV and dff_in is a signal output from the D flip flop 110 of the OTT 100 in the preceding stage which does not pass the TSV, Out of the output of the D flip-flop 110 of FIG.

dclk_in is a clock dffclk for the D flip-flop 110 generated in the OTT 100 of the previous stage and tclk is a clock used for shifting out the value of the D flip- It is used for synchronization when connecting to an external device such as an automatic checker.

mode is an OTT 100 operation mode in which a test mode in which a signal output from TSV is stored in an OTT 100 D flip-flop 110 and a test mode in which data stored in a D flip- 100 to the D flip-flop 110 in the shift mode.

dly_ctrl is a signal for controlling the delay of the edge of the D flip-flop clock with respect to the edge of the input signal in order to make the clock (dffclk) for the D flip-flop 110. It is also possible to designate a direct delay time However, it is also possible to select one of the predetermined delay times.

out indicates an output signal of the OTT 100 in the test mode and a TSV monitor signal of each OTT 100 in the shift mode.

dclk_out represents a clock for the D flip-flop 110 and is connected to the dclk_in terminal of the OTT 100 in the subsequent stage.

11, the set, clr, tclk, mode, and dly_ctrl signals, which are not sensitive to the signal delay, are jointly used do.

FIG. 12 shows a timing chart of a test procedure for the rising of an input signal using the OTT 100. In FIG.

12, when the test mode (mode = 0) is set and the clr signal is activated, the D flip-flop 110 of all the OTTs 100 is initialized to zero.

Then, when the set signal is activated, the D flip-flop 110 outputs 1 (OTT (100) 1_out). The D flip-flop clock generator 120 generates a clock delayed by the amount specified by the dly_ctrl (OTT (100) 1_dclk_out) based on a time point when the set signal changes to 1. OTT 100 1_out signal is delayed (OTT 100 2_tsv_in) by 2 blocks of OTT 100 while passing through TSV and input OTT 100 2_tsv_in is delayed by OTT 100 1_dclk_out (= OTT 100 2_dclk_in) Is stored in the D flip-flop 110 of the OTT (100) When the storage is completed, the test mode is switched to the shift mode (mode = 1), and the D flip-flop 110 of each OTT 100 sequentially transmits the data stored on the basis of the tclk to the D flip- do.

Although the above-described configuration shows and describes the connection of the OTT 100 circuit in the pre-bond test step, as shown in FIG. 13, the OTT 100 circuit of the present invention can also be utilized in the post-bond test step.

13, the post-bond test can be performed by connecting the TSV output value of the upper die to the D flip flop 110 of the OTT 100 of the lower die and synchronizing the input signals of the upper and lower dies.

Therefore, according to the present invention having the above-described configuration, the D flip-flop 110 is disposed at the output terminal of the TSV signal, and the input signal of the TSV is delayed and used as the trigger signal of the D flip- There is an effect that it can be easily recognized from the outside by using the D flip-flop 110 output signal.

Further, since the present invention does not require a complicated on-chip circuit or a signal analysis process, the present invention can be implemented through a simple scan structure.

Further, the present invention has an effect that the test cost can be greatly reduced since a TSV having a failure or a high failure probability can be detected in advance at the pre-bonding step.

100: OTT
110: D flip flop
120: clock generator

Claims (6)

OTT (On-chip TSV Tester: On-chip Silicon Through Via Tester) mounted on each lamination layer of TSV (Through Silicon Via);
And,
In the OTT,
A D flip flop connected to an output terminal of the TSV and receiving an output signal of the TSV as an input signal;
Generates a rising edge reference clock which is a delayed clock based on the detected rising edge and a falling edge reference clock which is a delayed clock based on the falling edge, A clock generator for generating a D flip-flop clock which is a logical sum of the rising edge reference clock and the falling edge reference clock and providing the D flip-flop clock to the D flip-flop;
And a third semiconductor device. The method according to claim 1,
Wherein the clock generator changes the delay time of the D flip-flop clock until the output signal of the D flip-flop is periodically repeated with a width equal to the input signal of the TSV, and the output signal of the D flip- If a stable periodic signal having the same width as the input signal of the TSV and periodically repeated is confirmed, the time obtained by subtracting the setup time of the D flip-flop from the D flip-flop clock delay time at that time is set as the final delay time of the TSV Test device for three-dimensional semiconductor. 3. The method of claim 2,
Wherein the analyzer is further configured to receive a final delay time of the clock generator, an output signal of the D flip-flop, and an output signal of the TSV for each TSV. The method of claim 3,
Wherein the analysis device compares the input final delay time for each TSV and determines a TSV having a delay time that is more delayed than the no-fault condition as a defect. The method of claim 3,
The analyzer compares the output signal of the D flip-flop according to the output signal of each TSV to determine whether the output signal of the D flip-flop is faster or slower than the output of the D flip- Is judged to be defective. 6. The method of claim 5,
When the output signal of the D flip-flop is higher than the output of the D flip-flop in response to the output of the TSV in a non-fault state, the output signal of the D flip- A three-dimensional semiconductor test apparatus to judge.

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