CN104270146A - Phase frequency detector for detecting catastrophic faults on phase-locked loop sheet - Google Patents
Phase frequency detector for detecting catastrophic faults on phase-locked loop sheet Download PDFInfo
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Abstract
The invention discloses a phase frequency detector for detecting catastrophic faults on a phase-locked loop sheet. The phase frequency detector comprises a clock generating unit, a periodical sampling unit, a charging and discharging control unit and a phase frequency detecting unit, wherein the clock generating unit generates two clock control signals from a reference signal, and a test control signal outside the sheet is not needed any more, so that input control pins are saved; according to the periodical sampling unit, the different periodical delays are completed through a trigger D to generate a charging test signal and a discharging test signal, so that charging and discharging test signal resources outside the sheet are saved; the charging and discharging control unit controls the circuit working state and the test flow, so that the test work can be automatically completed on the sheet; the phase frequency detecting unit completes frequency discrimination and phase discrimination of a reference signal value and a test signal value. The all-digital phase frequency detector for detecting catastrophic faults on the phase-locked loop sheet has the advantages of being automatic in test and low in cost.
Description
Technical field
The present invention relates to a kind of phase frequency detector that bust detects in phase-locked ring plate, belong to the on-chip testing technology of phase-locked loop circuit.
Background technology
Phase-locked loop (PLL) is widely used in frequency synthesis, phase demodulating, clock distribution and time recovery, is the requisite part of radio communication, optical fiber link and microcomputer, needs correct verification.But due to closed loop feedback and the mixed signal characteristic of phase-locked loop, become one of circuit of the most difficult test, become a difficult problem urgently to be resolved hurrily in the test at the international level to it, therefore, the on-chip testing scheme of research phase-locked loop circuit is significant.
PLL fault testing method mainly levies the fault caused by defect existed in the structure to circuit, and the fault hidden in phase-locked loop circuit often affects the performance of phase-locked loop.Can judge that whether phase-locked loop is qualified fast by whether there is fault in testing circuit.And usually can utilize the circuit structure existed in phase-locked loop due to testing circuit, therefore general test cost is lower.During batch testing, bust detects a kind of effective ways becoming fast and low-cost phase locked loop.
On the sheet of phase-locked loop, fault testing method must resolve following problem: 1, on sheet, self-inspection and Output rusults are convenient to viewing; Without the need to the great number testing expense that the high-end tester in outside produces, complete self-inspection by means of only on-chip testing, to reduce the cost of test.2, less to the performance impact of phase-locked loop; The test circuit of extra interpolation can affect the normal work of qualified phase-locked loop on the one hand on the impact of existing phase-locked loop circuit performance, also can reduce the accuracy rate of test on the other hand.3, the problem of analog node difficulty loading, tries not to open loop, tries not to open loop in analog node.4, digital test circuit and test export, more reliable to ensure the result of testing.5, in the testing time, reach balance between testing cost and test accuracy rate; Phase-locked loop is as mixed signal circuit unique in most of SOC (system on a chip), its testing time, testing cost, is directly converted to the production cost of electronic product, and its test accuracy rate also may affect the performance of whole electronic product, therefore must coordinate between three.
And traditional phase frequency detector being applied to phase-locked loop, can only when phase-locked loop normally works the phase difference of reference signal detection and feedback signal or difference on the frequency.For meeting the bust test of phase-locked loop, increasing Test Engineer starts to pay close attention to the research that can be applied to the phase frequency detector that phase-locked loop bust detects to having digital, automatic test, low cost.First, phase frequency detector, as the numerical portion of phase-locked loop circuit, makes improvements the performance impact of phase-locked loop less; Secondly, there is the phase frequency detector of digital test characteristic, make test result more reliable; Again, the test of test automatically can reduce the testing time; Finally, the test of low cost is applicable to the batch testing of phase-locked loop very much.Therefore, research is applicable to that phase-locked loop bust detects, and has digital, automatic test, the phase frequency detector of low cost has great Research Significance.
Summary of the invention
Goal of the invention: in order to overcome the deficiencies in the prior art, the invention provides a kind of phase frequency detector that bust detects in phase-locked ring plate, there is the feature of digital, automatic test, low cost, automatically can complete the charge-discharge test of phase-locked loop, complete the detection of the bust to phase-locked loop.
Technical scheme: for achieving the above object, the technical solution used in the present invention is:
A kind of phase frequency detector that bust detects in phase-locked ring plate, time difference between Reference Signal and test signal is converted to digital signal and exports and automatically can carry out charge-discharge test to phase-locked loop, specifically comprises clock generating unit, periodic sampling unit, charge-discharge control unit and phase frequency probe unit:
Reference signal meets the reference clock input clk_ref of the input end of clock CLK of clock generating unit, the input end of clock CLK of periodic sampling unit and charge-discharge control unit simultaneously, test signal meets the test signal input clk_test of charge-discharge control unit, and commencing signal meets the testing and control input test of charge-discharge control unit;
The three frequency division clock output signal CLK1 of clock generating unit connects the reset terminal of periodic sampling unit! CLR, six frequency-dividing clock output signal CLK2 of clock generating unit meet the control signal input control of charge-discharge control unit;
The period 1 sampled output signal cycle0 of periodic sampling unit meets the period 1 signal input part cycle0 of charge-discharge control unit, sampled output signal cycle1 second round of periodic sampling unit meets signal input part cycle1 second round of charge-discharge control unit, and the period 3 sampled output signal cycle2 of periodic sampling unit meets the period 3 signal input part cycle2 of charge-discharge control unit;
First clock output signal clk_out1 of charge-discharge control unit meets the first signal input part ref of phase frequency probe unit, and the second clock output signal clk_out2 of charge-discharge control unit meets the secondary signal input var of phase frequency probe unit;
Phase frequency probe unit exports charging signals U and discharge signal D;
The clock signal produced by clock generating unit is automatic start-up period sampling unit and charge-discharge control unit respectively, thus in the output output of charge-discharge control unit, there is shifting to an earlier date or delay signal of different delayed time, input in this, as phase frequency probe unit produces discharge and recharge signal alternately, for detecting phase-locked loop bust.
Described clock generating unit comprises two parts:
Part I, produce three frequency division clock output signal CLK1: comprise the first trigger DFF1, the second trigger DFF2 and the 3rd trigger DFF3, reference signal connects the input end of clock of the first trigger DFF1, the second trigger DFF2 and the 3rd trigger DFF3 simultaneously, and input supply voltage Vdd connects the RESET input of the first trigger DFF1, the second trigger DFF2 and the 3rd trigger DFF3 simultaneously; The D1 of the first trigger DFF1 input termination the 3rd trigger DFF3 /Q3 output, the Q1 of the first trigger DFF1 exports the D2 input of termination second trigger DFF2, the first trigger DFF1 /Q1 output is unsettled; The Q2 of the second trigger DFF2 exports the D3 input of termination the 3rd trigger DFF3, the second trigger DFF2 /Q2 output is unsettled; The Q3 output of the 3rd trigger DFF3 exports three frequency division clock output signal CLK1;
Part II, produce six frequency-dividing clock output signal CLK2: comprise the 4th trigger DFF4, 5th trigger DFF5, 6th trigger DFF6, 7th trigger DFF7, 8th trigger DFF8 and the 9th trigger DFF9, reference signal meets the 4th trigger DFF4 simultaneously, 5th trigger DFF5, 6th trigger DFF6, 7th trigger DFF7, 8th trigger DFF8 and the 9th trigger DFF9 input end of clock, input supply voltage Vdd meets the 4th trigger DFF4 simultaneously, 5th trigger DFF5, 6th trigger DFF6, 7th trigger DFF7, the RESET input of 8th trigger DFF8 and the 9th trigger DFF9, the D4 of the 4th trigger DFF4 input termination the 9th trigger DFF9 /Q9 output, the Q4 of the 4th trigger DFF4 exports the D5 input of termination the 5th trigger DFF5, the 4th trigger DFF4 /Q4 output is unsettled, the Q5 of the 5th trigger DFF5 exports the D6 input of termination the 6th trigger DFF6, the 5th trigger DFF5 /Q5 output is unsettled, the Q6 of the 6th trigger DFF6 exports the D7 input of termination the 7th trigger DFF7, the 6th trigger DFF6 /Q6 output is unsettled, the Q7 of the 7th trigger DFF7 exports the D8 input of termination the 8th trigger DFF8, the 7th trigger DFF7 /Q7 output is unsettled, the Q8 of the 8th trigger DFF8 exports the D9 input of termination the 9th trigger DFF9, the 8th trigger DFF8 /Q8 output is unsettled, the Q9 output of the 9th trigger DFF9 exports six frequency-dividing clock output signal CLK2.
Described periodic sampling unit comprises the tenth trigger DFF10, the 11 trigger DFF11 and the 12 trigger DFF12, reference signal connects the input end of clock of the tenth trigger DFF10, the 11 trigger DFF11 and the 12 trigger DFF12 simultaneously, and three frequency division clock output signal CLK1 connects the RESET input of the tenth trigger DFF10, the 11 trigger DFF11 and the 12 trigger DFF12 simultaneously; The D10 of the tenth trigger DFF10 inputs termination input supply voltage Vdd, the Q10 of the tenth trigger DFF10 exports the D11 input of termination the 11 trigger DFF11, simultaneously the Q10 output of the tenth trigger DFF10 export period 1 sampled output signal cycle0, the tenth trigger DFF9 /Q9 output is unsettled; The Q11 of the 11 trigger DFF11 exports the D12 input of termination the 12 trigger DFF12, and the Q11 output of the 11 trigger DFF11 exports sampled output signal cycle1 second round simultaneously, the 11 trigger DFF11 /Q11 output is unsettled; The Q12 output of the 12 trigger DFF12 export period 3 sampled output signal cycle2, the 12 trigger DFF12 /Q12 output is unsettled.
Described charge-discharge control unit comprises three multiselect switches be made up of full-digital circuit, the structure of three multiselect switches is identical, each multiselect switch comprises a not gate NOT and three NAND gate NAND, reseting input signal connects the input of not gate NOT, signal A and the output of not gate NOT are connected two inputs of the first NAND gate NAND1 respectively, reseting input signal and signal B are connected two inputs of the second NAND gate NAND2 respectively, the output of the first NAND gate NAND1 and the output of the second NAND gate NAND2 are connected two inputs of the 3rd NAND gate NAND3 respectively, the output output signal out of the 3rd NAND gate NAND3, the input of tracer signal A is A input, B signal input part is B input, reset signal input is set input, out signal output part is output out,
Another name three multiselect switches are divided to be the A1 input that the first multiselect switch MUX1, the second multiselect switch MUX2 and the 3rd multiselect switch MUX3: period 1 sampled output signal cycle0 meet the first multiselect switch MUX1, period 3 sampled output signal cycle2 connects the B1 input of the first multiselect switch MUX1, six frequency-dividing clock output signal CLK2 connect the set1 input of the first multiselect switch MUX1, and the output out1 of the first multiselect switch MUX1 connects the B2 input of the second multiselect switch; Reference signal connects the A2 input of the second multiselect switch MUX2, and commencing signal connects the set2 input of the second multiselect switch MUX2, and the output out2 of the second multiselect switch MUX2 exports the first clock output signal clk_out1; Test signal connects the A3 input of the 3rd multiselect switch MUX3, second round, sampled output signal cycle1 connect the B3 input of the 3rd multiselect switch MUX3, commencing signal connects the set3 input of the 3rd multiselect switch MUX3, and the output out3 of the 3rd multiselect switch MUX3 exports second clock output signal clk_out2.
Described phase frequency probe unit is conventional phase frequency detector, for detecting phase place, the difference on the frequency of the first clock output signal clk_out1 and second clock output signal clk_out2, thus obtains corresponding discharge and recharge signal; The input of phase frequency probe unit meets the first clock output signal clk_out1 and second clock output signal clk_out2 respectively, and output exports charging signals U and discharge signal D.
Beneficial effect: the phase frequency detector that bust detects in phase-locked ring plate provided by the invention, there is the feature of digital, automatic test, low cost: first, by clock generating unit Reference Signal frequency division produce three frequency division clock signal can automatically control cycle sampling time, six fractional frequency signals select Test input signal automatically, thus automatically control the process of charge-discharge test, therefore this phase frequency detector has the feature of test automatically; Secondly, clock generating unit, periodic sampling unit, charge-discharge control unit and phase frequency probe unit are all made up of full-digital circuit, and therefore this phase frequency detector has digital feature, make the result of test more reliable; Finally, because whole circuit only needs several d type flip flop and multiselect switch, and without the need to external clock test signal, the bust for phase-locked loop detects, and hardware spending and area overhead are all less, and therefore this phase frequency detector has the feature of low cost.
Accompanying drawing explanation
Fig. 1 is the phase frequency detector structured flowchart detected for phase-locked loop bust of the present invention;
Fig. 2 is the phase frequency detector structure principle chart detected for phase-locked loop bust of the present invention,
Fig. 3 is the test flow chart detected for phase-locked loop bust of the present invention;
Fig. 4 is that wherein 4 (a) is normal mode, 4 (b) test pattern based on the sequential chart detected for phase-locked loop bust of the present invention.
Fig. 5 is that wherein 5 (a) is phase-locked loop to be measured, and 5 (b) is the impact on phase lock loop lock on time to be measured based on the test result detected for phase-locked loop bust of the present invention.
Embodiment
Below in conjunction with accompanying drawing, the present invention is further described.
Be a kind of phase frequency detector that bust detects in phase-locked ring plate as shown in Figure 1 and Figure 2, time difference between Reference Signal and test signal is converted to digital signal and exports and automatically can carry out charge-discharge test to phase-locked loop, specifically comprise clock generating unit, periodic sampling unit, charge-discharge control unit and phase frequency probe unit, concrete syndeton is as follows:
Reference signal meets the reference clock input clk_ref of the input end of clock CLK of clock generating unit, the input end of clock CLK of periodic sampling unit and charge-discharge control unit simultaneously, test signal meets the test signal input clk_test of charge-discharge control unit, and commencing signal meets the testing and control input test of charge-discharge control unit;
The three frequency division clock output signal CLK1 of clock generating unit connects the reset terminal of periodic sampling unit! CLR, six frequency-dividing clock output signal CLK2 of clock generating unit meet the control signal input control of charge-discharge control unit;
The period 1 sampled output signal cycle0 of periodic sampling unit meets the period 1 signal input part cycle0 of charge-discharge control unit, sampled output signal cycle1 second round of periodic sampling unit meets signal input part cycle1 second round of charge-discharge control unit, and the period 3 sampled output signal cycle2 of periodic sampling unit meets the period 3 signal input part cycle2 of charge-discharge control unit;
First clock output signal clk_out1 of charge-discharge control unit meets the first signal input part ref of phase frequency probe unit, and the second clock output signal clk_out2 of charge-discharge control unit meets the secondary signal input var of phase frequency probe unit;
Phase frequency probe unit exports charging signals U and discharge signal D;
The clock signal produced by clock generating unit is automatic start-up period sampling unit and charge-discharge control unit respectively, thus in the output output of charge-discharge control unit, there is shifting to an earlier date or delay signal of different delayed time, input in this, as phase frequency probe unit produces discharge and recharge signal alternately, for detecting phase-locked loop bust.
Particular circuit configurations below with regard to unit provides explanation.
Described clock generating unit comprises two parts, major function provides control clock signal for periodic sampling unit and charge-discharge control unit: Part I is for generation of three frequency division clock output signal CLK1, and Part II is for generation of six frequency-dividing clocks output signal CLK2.
Part I, produce three frequency division clock output signal CLK1: comprise the first trigger DFF1, the second trigger DFF2 and the 3rd trigger DFF3, reference signal connects the input end of clock of the first trigger DFF1, the second trigger DFF2 and the 3rd trigger DFF3 simultaneously, and input supply voltage Vdd connects the RESET input of the first trigger DFF1, the second trigger DFF2 and the 3rd trigger DFF3 simultaneously; The D1 of the first trigger DFF1 input termination the 3rd trigger DFF3 /Q3 output, the Q1 of the first trigger DFF1 exports the D2 input of termination second trigger DFF2, the first trigger DFF1 /Q1 output is unsettled; The Q2 of the second trigger DFF2 exports the D3 input of termination the 3rd trigger DFF3, the second trigger DFF2 /Q2 output is unsettled; The Q3 output of the 3rd trigger DFF3 exports three frequency division clock output signal CLK1.
Part II, produce six frequency-dividing clock output signal CLK2: comprise the 4th trigger DFF4, 5th trigger DFF5, 6th trigger DFF6, 7th trigger DFF7, 8th trigger DFF8 and the 9th trigger DFF9, reference signal meets the 4th trigger DFF4 simultaneously, 5th trigger DFF5, 6th trigger DFF6, 7th trigger DFF7, 8th trigger DFF8 and the 9th trigger DFF9 input end of clock, input supply voltage Vdd meets the 4th trigger DFF4 simultaneously, 5th trigger DFF5, 6th trigger DFF6, 7th trigger DFF7, the RESET input of 8th trigger DFF8 and the 9th trigger DFF9, the D4 of the 4th trigger DFF4 input termination the 9th trigger DFF9 /Q9 output, the Q4 of the 4th trigger DFF4 exports the D5 input of termination the 5th trigger DFF5, the 4th trigger DFF4 /Q4 output is unsettled, the Q5 of the 5th trigger DFF5 exports the D6 input of termination the 6th trigger DFF6, the 5th trigger DFF5 /Q5 output is unsettled, the Q6 of the 6th trigger DFF6 exports the D7 input of termination the 7th trigger DFF7, the 6th trigger DFF6 /Q6 output is unsettled, the Q7 of the 7th trigger DFF7 exports the D8 input of termination the 8th trigger DFF8, the 7th trigger DFF7 /Q7 output is unsettled, the Q8 of the 8th trigger DFF8 exports the D9 input of termination the 9th trigger DFF9, the 8th trigger DFF8 /Q8 output is unsettled, the Q9 output of the 9th trigger DFF9 exports six frequency-dividing clock output signal CLK2.
Described periodic sampling unit gathers the rising edge of the rising edge clock of reference signal, the rising edge of the reference signal of a reference signal clock cycle of time delay, the reference signal of two reference signal clock cycle of time delay respectively, thus provides three input signals with different delayed time for charge-discharge control unit; Comprise the tenth trigger DFF10, the 11 trigger DFF11 and the 12 trigger DFF12, reference signal connects the input end of clock of the tenth trigger DFF10, the 11 trigger DFF11 and the 12 trigger DFF12 simultaneously, and three frequency division clock output signal CLK1 connects the RESET input of the tenth trigger DFF10, the 11 trigger DFF11 and the 12 trigger DFF12 simultaneously; The D10 of the tenth trigger DFF10 inputs termination input supply voltage Vdd, the Q10 of the tenth trigger DFF10 exports the D11 input of termination the 11 trigger DFF11, the Q10 output of the tenth trigger DFF10 exports period 1 sampled output signal cycle0 (the rising edge clock signal cycle0 of reference signal) simultaneously, the tenth trigger DFF9 /Q9 output is unsettled; The Q11 of the 11 trigger DFF11 exports the D12 input of termination the 12 trigger DFF12, the Q11 output of the 11 trigger DFF11 exports sampled output signal cycle1 second round (having prolonged the reference signal rising edge cycle1 of a reference signal clock cycle) simultaneously, the 11 trigger DFF11 /Q11 output is unsettled; The Q12 output of the 12 trigger DFF12 exports period 3 sampled output signal cycle2 (having prolonged the reference signal rising edge cycle2 of two reference signal clock cycle), the 12 trigger DFF12 /Q12 output is unsettled.
Described charge-discharge control unit is under the effect of six sub-frequency clock signal CLK2, every six clock cycle alternately by period 1 sampled output signal cycle0, second round sampled output signal cycle1 or period 3 sampled output signal cycle2 and period 1 sampled output signal cycle1, thus provide two input signals with delayed time delay or advance time-delay for phase frequency detecting unit.Comprise three multiselect switches be made up of full-digital circuit, the structure of three multiselect switches is identical, each multiselect switch comprises a not gate NOT and three NAND gate NAND, reseting input signal connects the input of not gate NOT, signal A and the output of not gate NOT are connected two inputs of the first NAND gate NAND1 respectively, reseting input signal and signal B are connected two inputs of the second NAND gate NAND2 respectively, the output of the first NAND gate NAND1 and the output of the second NAND gate NAND2 are connected two inputs of the 3rd NAND gate NAND3 respectively, the output output signal out of the 3rd NAND gate NAND3, the input of tracer signal A is A input, B signal input part is B input, reset signal input is set input, out signal output part is output out.
Another name three multiselect switches are divided to be the A1 input that the first multiselect switch MUX1, the second multiselect switch MUX2 and the 3rd multiselect switch MUX3: period 1 sampled output signal cycle0 meet the first multiselect switch MUX1, period 3 sampled output signal cycle2 connects the B1 input of the first multiselect switch MUX1, six frequency-dividing clock output signal CLK2 connect the set1 input of the first multiselect switch MUX1, and the output out1 of the first multiselect switch MUX1 connects the B2 input of the second multiselect switch; Reference signal connects the A2 input of the second multiselect switch MUX2, and commencing signal connects the set2 input of the second multiselect switch MUX2, and the output out2 of the second multiselect switch MUX2 exports the first clock output signal clk_out1; Test signal connects the A3 input of the 3rd multiselect switch MUX3, second round, sampled output signal cycle1 connect the B3 input of the 3rd multiselect switch MUX3, commencing signal connects the set3 input of the 3rd multiselect switch MUX3, and the output out3 of the 3rd multiselect switch MUX3 exports second clock output signal clk_out2.
Described phase frequency probe unit is conventional phase frequency detector, for detecting phase place, the difference on the frequency of the first clock output signal clk_out1 and second clock output signal clk_out2, thus obtains corresponding discharge and recharge signal; The input of phase frequency probe unit meets the first clock output signal clk_out1 and second clock output signal clk_out2 respectively, and output exports charging signals U and discharge signal D.
Just the operation principle of unit of the present invention is illustrated below.
The clock signal clk 1 produced by clock generating unit and CLK2 respectively every three reference signal clock-reset one-period sampling units provide two input signals with the time difference and every four reference signal clock cycle start charge-discharge control unit select to have different delayed time in advance or delayed test signal, input in this, as phase frequency probe unit produces discharge and recharge signal alternately, for the detection to phase-locked loop bust.
The Part I of clock generating unit, the three frequency division clock signal clk 1 producing reference signal, as the reset signal of periodic sampling unit, comprises the first trigger DFF1, the second trigger DFF2 and the 3rd trigger DFF3.Namely every three reference signal clock cycle reset once to periodic sampling unit, the rising edge of next three frequency division clock, and periodic sampling unit restarts sampling again, thus constantly for subsequent conditioning circuit provides test signal to export.
The Part II of clock generating unit, the six sub-frequency clock signal CLK2 producing reference signal, as the control signal of charge-discharge control unit, comprise the 4th trigger DFF4, the 5th trigger DFF5, the 6th trigger DFF6, the 7th trigger DFF7, the 8th trigger DFF8 and the 9th trigger DFF9.Namely every six reference signal clock cycle start charge-discharge control unit once, and the rising edge of next six frequency-dividing clocks, charge-discharge control unit carries out discharge and recharge according to the phase frequency difference of input signal.
Periodic sampling unit comprises the tenth trigger DFF10, the 11 trigger DFF11 and the 12 trigger DFF12; Sampling exports the rising edge cycle0 of reference signal respectively, the rising edge cycle1 of the reference signal of a reference signal clock cycle of time delay, the time delay reference signal rising edge cycle1 of two reference signal clock cycle.
Charge-discharge control unit comprises the first multiselect switch MUX1, the second multiselect switch MUX2 and the 3rd multiselect switch MUX3.During charging, select period 1 input signal cycle0 and period 3 input signal cycle1.Period 1 input signal cycle0 carries the previous reference signal clock cycle than input signal cycle1 second round.During electric discharge, select period 3 input signal cycle2 and second round input signal cycle1.The period 3 input signal cycle2 reference signal clock cycle more delayed than input signal cycle1 second round.Charge-discharge control unit is controlled by six divided output signal CLK2 of clock generating unit, and every six reference signal clock cycle TRY ANOTHER SELECTION the input signal of phase frequency probe unit.
Phase frequency probe unit is identical with conventional tri-state phase frequency detector structure, outputs signal phase place and the difference on the frequency of clk1_out and second output signal clk2_out, thus obtain corresponding discharge and recharge signal as detection first.
The phase frequency detector of this case has two kinds of mode of operations.During normal mode of operation, the phase frequency between phase frequency detecting unit detection reference signal and pll feedback signal is poor, provides the clock signal of system.During test pattern, produce two clock signals automatic cycle sampling unit and charge-discharge control unit respectively by clock generating unit, to produce the discharge and recharge signal with out of phase difference on the frequency, thus the bust realizing phase-locked loop detects.
Below in conjunction with accompanying drawing and embodiment, the present invention is described in further detail.
Fig. 1 is the phase frequency detector structured flowchart detected for phase-locked loop bust of the present invention.Fig. 2 is the phase frequency detector structure principle chart detected for phase-locked loop bust of the present invention.Fig. 3 is the test flow chart detected for phase-locked loop bust of the present invention.Fig. 4 is based on the sequential chart during test for the detection of phase-locked loop bust of the present invention.Fig. 5 is based on the test result detected for phase-locked loop bust of the present invention.Table 1 is the test result detected for phase-locked loop bust of the present invention.
The failure measure of table 1 new type digital phase locking loop built-in of the present invention self-testing structure
As can be seen from Fig. 1, Fig. 2, phase frequency detector for the detection of phase-locked loop bust of the present invention is full-digital circuit, and only needs several trigger and variable connector, and the bust for phase-locked loop detects, this phase frequency detector structure has digital, the feature of low cost.
The phase frequency detector detected for phase-locked loop bust of the present invention, automatically can complete the charge-discharge test of phase-locked loop, thus detect the bust of phase-locked loop as seen from Figure 3.Therefore this phase frequency detector structure has the feature of test automatically.
As seen from Figure 4, the phase frequency detector detected for phase-locked loop bust of the present invention, during normal mode, phase frequency detecting unit is input signal is reference signal and feedback signal, outputs signal as the more and more less discharge and recharge signal of phase frequency difference.During test pattern, input signal is the periodic sampling signal with different advance time-delay or delayed time delay, and input signal is the discharge and recharge signal of rule alternately.
As seen from Figure 5, the phase frequency detector detected for phase-locked loop bust of the present invention is less to the performance impact of phase-locked loop to be measured.Use the phase frequency detector detected for phase-locked loop bust of the present invention, and under not using two kinds of situations, the locking time of phase-locked loop to be measured is respectively 1.08us and 0.89us.
As can be seen from Table 1, the phase frequency detector detected for phase-locked loop bust of the present invention, when carrying out bust to phase-locked loop to be measured and detecting, total fault coverage is 98.75%, and fault coverage is higher.
The above is only the preferred embodiment of the present invention; be noted that for those skilled in the art; under the premise without departing from the principles of the invention, can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (5)
1. the phase frequency detector that bust detects in phase-locked ring plate, it is characterized in that: the time difference between Reference Signal and test signal is converted to digital signal and exports and automatically can carry out charge-discharge test to phase-locked loop, specifically comprises clock generating unit, periodic sampling unit, charge-discharge control unit and phase frequency probe unit:
Reference signal meets the reference clock input clk_ref of the input end of clock CLK of clock generating unit, the input end of clock CLK of periodic sampling unit and charge-discharge control unit simultaneously, test signal meets the test signal input clk_test of charge-discharge control unit, and commencing signal meets the testing and control input test of charge-discharge control unit;
The three frequency division clock output signal CLK1 of clock generating unit connects the reset terminal of periodic sampling unit! CLR, six frequency-dividing clock output signal CLK2 of clock generating unit meet the control signal input control of charge-discharge control unit;
The period 1 sampled output signal cycle0 of periodic sampling unit meets the period 1 signal input part cycle0 of charge-discharge control unit, sampled output signal cycle1 second round of periodic sampling unit meets signal input part cycle1 second round of charge-discharge control unit, and the period 3 sampled output signal cycle2 of periodic sampling unit meets the period 3 signal input part cycle2 of charge-discharge control unit;
First clock output signal clk_out1 of charge-discharge control unit meets the first signal input part ref of phase frequency probe unit, and the second clock output signal clk_out2 of charge-discharge control unit meets the secondary signal input var of phase frequency probe unit;
Phase frequency probe unit exports charging signals U and discharge signal D;
The clock signal produced by clock generating unit is automatic start-up period sampling unit and charge-discharge control unit respectively, thus in the output output of charge-discharge control unit, there is shifting to an earlier date or delay signal of different delayed time, input in this, as phase frequency probe unit produces discharge and recharge signal alternately, for detecting phase-locked loop bust.
2. the phase frequency detector that bust detects in phase-locked ring plate according to claim 1, is characterized in that: described clock generating unit comprises two parts:
Part I, produce three frequency division clock output signal CLK1: comprise the first trigger DFF1, the second trigger DFF2 and the 3rd trigger DFF3, reference signal connects the input end of clock of the first trigger DFF1, the second trigger DFF2 and the 3rd trigger DFF3 simultaneously, and input supply voltage Vdd connects the RESET input of the first trigger DFF1, the second trigger DFF2 and the 3rd trigger DFF3 simultaneously; The D1 of the first trigger DFF1 input termination the 3rd trigger DFF3 /Q3 output, the Q1 of the first trigger DFF1 exports the D2 input of termination second trigger DFF2, the first trigger DFF1 /Q1 output is unsettled; The Q2 of the second trigger DFF2 exports the D3 input of termination the 3rd trigger DFF3, the second trigger DFF2 /Q2 output is unsettled; The Q3 output of the 3rd trigger DFF3 exports three frequency division clock output signal CLK1;
Part II, produce six frequency-dividing clock output signal CLK2: comprise the 4th trigger DFF4, 5th trigger DFF5, 6th trigger DFF6, 7th trigger DFF7, 8th trigger DFF8 and the 9th trigger DFF9, reference signal meets the 4th trigger DFF4 simultaneously, 5th trigger DFF5, 6th trigger DFF6, 7th trigger DFF7, 8th trigger DFF8 and the 9th trigger DFF9 input end of clock, input supply voltage Vdd meets the 4th trigger DFF4 simultaneously, 5th trigger DFF5, 6th trigger DFF6, 7th trigger DFF7, the RESET input of 8th trigger DFF8 and the 9th trigger DFF9, the D4 of the 4th trigger DFF4 input termination the 9th trigger DFF9 /Q9 output, the Q4 of the 4th trigger DFF4 exports the D5 input of termination the 5th trigger DFF5, the 4th trigger DFF4 /Q4 output is unsettled, the Q5 of the 5th trigger DFF5 exports the D6 input of termination the 6th trigger DFF6, the 5th trigger DFF5 /Q5 output is unsettled, the Q6 of the 6th trigger DFF6 exports the D7 input of termination the 7th trigger DFF7, the 6th trigger DFF6 /Q6 output is unsettled, the Q7 of the 7th trigger DFF7 exports the D8 input of termination the 8th trigger DFF8, the 7th trigger DFF7 /Q7 output is unsettled, the Q8 of the 8th trigger DFF8 exports the D9 input of termination the 9th trigger DFF9, the 8th trigger DFF8 /Q8 output is unsettled, the Q9 output of the 9th trigger DFF9 exports six frequency-dividing clock output signal CLK2.
3. the phase frequency detector that bust detects in phase-locked ring plate according to claim 1, it is characterized in that: described periodic sampling unit comprises the tenth trigger DFF10, the 11 trigger DFF11 and the 12 trigger DFF12, reference signal connects the input end of clock of the tenth trigger DFF10, the 11 trigger DFF11 and the 12 trigger DFF12 simultaneously, and three frequency division clock output signal CLK1 connects the RESET input of the tenth trigger DFF10, the 11 trigger DFF11 and the 12 trigger DFF12 simultaneously; The D10 of the tenth trigger DFF10 inputs termination input supply voltage Vdd, the Q10 of the tenth trigger DFF10 exports the D11 input of termination the 11 trigger DFF11, simultaneously the Q10 output of the tenth trigger DFF10 export period 1 sampled output signal cycle0, the tenth trigger DFF9 /Q9 output is unsettled; The Q11 of the 11 trigger DFF11 exports the D12 input of termination the 12 trigger DFF12, and the Q11 output of the 11 trigger DFF11 exports sampled output signal cycle1 second round simultaneously, the 11 trigger DFF11 /Q11 output is unsettled; The Q12 output of the 12 trigger DFF12 export period 3 sampled output signal cycle2, the 12 trigger DFF12 /Q12 output is unsettled.
4. the phase frequency detector that bust detects in phase-locked ring plate according to claim 1, it is characterized in that: described charge-discharge control unit comprises three multiselect switches be made up of full-digital circuit, the structure of three multiselect switches is identical, each multiselect switch comprises a not gate NOT and three NAND gate NAND, reseting input signal connects the input of not gate NOT, signal A and the output of not gate NOT are connected two inputs of the first NAND gate NAND1 respectively, reseting input signal and signal B are connected two inputs of the second NAND gate NAND2 respectively, the output of the first NAND gate NAND1 and the output of the second NAND gate NAND2 are connected two inputs of the 3rd NAND gate NAND3 respectively, the output output signal out of the 3rd NAND gate NAND3, the input of tracer signal A is A input, B signal input part is B input, reset signal input is set input, out signal output part is output out,
Another name three multiselect switches are divided to be the A1 input that the first multiselect switch MUX1, the second multiselect switch MUX2 and the 3rd multiselect switch MUX3: period 1 sampled output signal cycle0 meet the first multiselect switch MUX1, period 3 sampled output signal cycle2 connects the B1 input of the first multiselect switch MUX1, six frequency-dividing clock output signal CLK2 connect the set1 input of the first multiselect switch MUX1, and the output out1 of the first multiselect switch MUX1 connects the B2 input of the second multiselect switch; Reference signal connects the A2 input of the second multiselect switch MUX2, and commencing signal connects the set2 input of the second multiselect switch MUX2, and the output out2 of the second multiselect switch MUX2 exports the first clock output signal clk_out1; Test signal connects the A3 input of the 3rd multiselect switch MUX3, second round, sampled output signal cycle1 connect the B3 input of the 3rd multiselect switch MUX3, commencing signal connects the set3 input of the 3rd multiselect switch MUX3, and the output out3 of the 3rd multiselect switch MUX3 exports second clock output signal clk_out2.
5. the phase frequency detector that bust detects in phase-locked ring plate according to claim 1, it is characterized in that: described phase frequency probe unit is phase frequency detector, for detecting phase place, the difference on the frequency of the first clock output signal clk_out1 and second clock output signal clk_out2, thus obtain corresponding discharge and recharge signal; The input of phase frequency probe unit meets the first clock output signal clk_out1 and second clock output signal clk_out2 respectively, and output exports charging signals U and discharge signal D.
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| CN1756080A (en) * | 2004-09-28 | 2006-04-05 | 富士通株式会社 | Semiconductor integrated circuit |
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| CN1756080A (en) * | 2004-09-28 | 2006-04-05 | 富士通株式会社 | Semiconductor integrated circuit |
| CN1763552A (en) * | 2004-10-21 | 2006-04-26 | 扬智科技股份有限公司 | Jitter signal circuit device of phase-locked loop for built-in self-test and method thereof |
| US20070280032A1 (en) * | 2006-05-25 | 2007-12-06 | Micron Technology, Inc. | Built-in system and method for testing integrated circuit timing parameters |
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