CN104297583A - DSP based power quality testing system - Google Patents
DSP based power quality testing system Download PDFInfo
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- CN104297583A CN104297583A CN201410395307.6A CN201410395307A CN104297583A CN 104297583 A CN104297583 A CN 104297583A CN 201410395307 A CN201410395307 A CN 201410395307A CN 104297583 A CN104297583 A CN 104297583A
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Abstract
The invention discloses a DSP based power quality testing system. The system comprises a voltage transformer, a current transformer, a signal conditioning circuit and a DSP minimum system which are connected to a power grid, wherein the voltage transformer and the current transformer are connected with the signal conditioning circuit, an A/D sampling circuit and a frequency capturing circuit are connected between the signal conditioning circuit and the DSP minimum system, the DSP minimum system is connected to a CPLD (complex programmable logic device) internal logic circuit, the CPLD internal logic circuit is connected to an LCD (liquid crystal display), a real-time clock, a GPRS module and an RS232/485 interface. The DSP based power quality testing system is more reasonable in hardware structure design and only uses a single CPU, and most of logic circuits at the periphery are realized inside a CPLD, thereby greatly reducing the hardware structure of the system. In addition, software design and development are enabled to be simplified by adopting the hardware structure of the system.
Description
Technical field
The present invention relates to the quality test of electric energy, refer to a kind of electric energy quality test system based on DSP particularly.
Background technology
Along with the development of national economy and the continuous progress of science and technology, electric energy become human society purposes the most widely, indispensable important energy source, the requirement of all trades and professions to the quality of power supply is also more and more higher.But along with the fast development of Power Electronic Technique and widespread use, especially nonlinear-load comes into operation in a large number, makes the harmonic pollution of electric system more and more serious.
Owing to having the electrical feature such as non-linear, impact and imbalance in power system load, as: the loads such as steel-making, steel rolling, chemical industry, electric railroad, power electronic equipment, make the voltage of electrical network, current waveform distorts, harmonic content strengthens, voltage produces fluctuation and the electric pollution problem such as flickering, voltage dip and three-phase imbalance, has had a strong impact on power supply quality.Statistical data according to advanced industrial country's power department shows, and frequent electric operational accident, equipment for power transmission and distribution and the electrical equipment damage accident occurred, its main cause is electric pollution.Electric pollution causes the production of electric energy, the efficiency of transmission and use reduces, and makes device of overheating of electrical, vibration and insulation damages, causes relay protection and aut.eq. misoperation, make electric energy measuring equipment occur deviation.Advanced industrial country pays much attention to for electric pollution problem in recent years, establishes complete detection supervision and management system.In China, although macroeconomy and technical merit are also relatively backward, in part developed area, power quality problem is more outstanding.And due to a variety of causes, in the index such as maintenance level of power supply reliability and grid voltage magnitudes, China is also in relatively backward state.How to improve and to ensure the quality of power supply, having become one of domestic and international electrical field important topic in the urgent need to address.
Summary of the invention
The object of the invention is overcome above-mentioned the deficiencies in the prior art and provide a kind of electric energy quality test system based on DSP, and this test system hardware structure is simple, and only need develop the test that DSP program can complete the quality of power supply.
The technical scheme realizing the object of the invention employing is: a kind of electric energy quality test system based on DSP, this system comprises: be connected to voltage transformer (VT) summation current transformer in electrical network, signal conditioning circuit and DSP minimum system, described voltage transformer (VT) summation current transformer is connected with described signal conditioning circuit respectively, A/D sample circuit and frequency acquisition circuit is connected between described signal conditioning circuit and DSP minimum system, described DSP minimum system is connected with CPLD internal logic circuit, described CPLD internal logic circuit is connected with LCD display, real-time clock, GPRS module and RS232/485 interface.
In technique scheme, described DSP minimum system is TMS320F2812 chip.
Further, described based in the electric energy quality test system of DSP, described TMS320F2812 chip is connected with FLASH, SRAM, SD card and key cell.
Further, described based in the electric energy quality test system of DSP, described TMS320F2812 chip is connected with TPS767D318 power supply chip.
The present invention has the following advantages:
1. Design of Hardware Architecture is more tending towards reasonable.Only use single cpu (TMS320F2812 chip), the logical circuit of the peripheral overwhelming majority all realizes in CPLD, reduces the hardware configuration of system widely.
2. Software for Design exploitation simplifies.Adopt the hardware structure of DSP+CPLD of the present invention, exploitation DSP program is only needed when Software for Design, if adopt dual-cpu structure design, need to design program respectively to DSP and MCU and will consider the problems such as working in coordination between dual processors, collaborative work, exchanges data, this is higher to the requirement of Software for Design, too increases the difficulty of design and extends cycle of exploitation.
3., from the reasonable employment of resource, take full advantage of the internal resource of DSP and abundant Peripheral Interface, and inevitably there is certain wasting of resources in dual-cpu structure, such as, may cause the idle of the resources such as CPU timer internal, serial ports, I/O port.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of the electric energy quality test system that the present invention is based on DSP.
Fig. 2 is the workflow diagram of the electric energy quality test system that the present invention is based on DSP.
Fig. 3 is the workflow diagram of A/D sample circuit in the present invention.
Fig. 4 is FFT calculation process schematic diagram in the present invention.
Fig. 5 is the flow for displaying figure of LCD display.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
As shown in Figure 1, the electric energy quality test system that the present invention is based on DSP comprises: be connected to voltage transformer (VT) summation current transformer in electrical network, signal conditioning circuit and DSP minimum system, described voltage transformer (VT) summation current transformer is connected with described signal conditioning circuit respectively, A/D sample circuit and frequency acquisition circuit is connected between described signal conditioning circuit and DSP minimum system, described DSP minimum system is connected with CPLD internal logic circuit, and described CPLD internal logic circuit is connected with LCD display, real-time clock, GPRS module and RS232/485 interface.
DSP minimum system in the present embodiment is the most basic system that DSP can normally be worked, DSP minimum system in this electric energy quality test system is for core with TMS320F2812 chip, DSP minimum system also comprises power circuit, reset circuit, clock circuit, specific as follows:
1, power circuit, all chips that power circuit is whole system provide power management.Power circuit not only meet each functional module use the level demand of chip, also have chipsets all on enough power driven systems.I/O level due to TMS320F2812 is 3.3V, and core operational voltage is 1.8V, so need to power with two kinds of level.Power circuit of the present invention uses the TPS767D318 power supply chip of TI company to power to DSP, TPS767D318 power supply chip is two-way low voltage difference feed regulator isolator, there are two electric pressure converters inside, two-way changing voltage can be exported simultaneously, be respectively 3.3V and 1.8V, and the maximum output current of chip all can reach about lA, the requirement of instinct quality test system can be met completely.
2, reset circuit, TMS320F2812 inside carries reset circuit, is resetted by interface XRS low level.The present invention adopts button hand-reset, very convenient in debug process.
3, clock circuit, phaselocked loop is that a kind of being used for controls crystal oscillator and make it keep constant circuit relative to reference signal, uses more extensive in digital communication systems.Phaselocked loop on current microprocessor or the integrated sheet of DSP, Main Function is by the real-time configuration On-Chip peripheral clock of software, improves dirigibility and the reliability of system.In addition, owing to adopting software programmable phaselocked loop, so system processor sheet allows lower frequency of operation outward, and in sheet through phaselocked loop for microprocessor provides higher system clock.This design can effectively reduce dependence and the electromagnetic interference (EMI) that system external establishes clock, improves the reliability of system start-up and operation, reduces system to the designing requirement of hardware.
On the sheet of TMS320F2812 processor, crystal oscillator and phase-locked loop module provide clock signal for kernel and peripheral hardware, and the low power mode of operation of control device.On sheet, crystal oscillator module allows to make in two ways for device provides clock, namely adopts internal oscillator or external clock reference.If use internal oscillator, must connect a quartz crystal between these two pins of X1/XCLKIN and X2, be generally 30MHz.If employing external clock, the clock signal of input directly can be received on X1/XCLKIN pin, and X2 is unsettled, does not use internal oscillator.
The present invention adopts an active crystal oscillator, supply voltage 3.3V, and clock frequency is 30MHz, as the clock frequency of DSP after PLL frequency multiplication.
4, external memory storage expansion, memory interface is responsible for CPU being accessed the same storer of memory logic control module, peripheral hardware and other interfaces and is coupled together.Memory interface comprises independently data and program bus, and therefore in one-period, CPU can simultaneously access program storer and data-carrier store.This interface also comprises the various control signals (as reading and writing signal etc.) of memory access needs, be mapped to 5 independently storage spaces by the external interface (XINTF) of the data transmission TMS320F2812 processor of these signal control stores or peripheral hardware, be respectively Zone0, Zonel, Zone2, Zone6 and Zone7.When accessing corresponding storage space, a chip selection signal can be produced.Each space independently can arrange access and wait for, selects, sets up and the retention time, XREADY signal can also be used to control the access of peripheral hardware simultaneously.When carrying out three-phase alternating current parameter processing, because method comparison is complicated, need mass data computing, simultaneity factor needs to store some important parameters, in order to meet the needs of system to large storage space, native system utilizes Zone2 to extend the FLASH chip MBM29LV800 of one piece of 512Kxl6bit, for depositing the parameter such as intermediate data a large amount of in DSP signal processing and voltage, electric current, power, harmonic wave.In program debug process, because program code is comparatively large, DSP inner space is inadequate, and system conveniently utilizes Zone6 to extend the SRAM of 128Kxl6bit, for the debugging of program code.
5, signal conditioning circuit, three-phase ac signal needed to carry out anti-aliasing low-pass filtering before AD conversion; Main Function is the HFS of filter out signal.According to sampling thheorem sample frequency. the twice of sampled signal highest frequency must be more than or equal to, so just can not produce aliasing.In order to reach this purpose, to design a low-pass filter in circuit, carry out pre-service to sampled signal, HFS frequency component being greater than 0.5f filters.
6, frequency acquisition circuit, when using FFT to calculate each harmonic, in order to improve computational accuracy as much as possible and reduce spectrum leakage error, need to carry out synchronized sampling, the degree of accuracy of therefore frequency measurement will directly have influence on the size of error calculated.Conventional method is by input signal after shaping, then realizes synchronized sampling by frequency multiplication of phase locked loop to the pulse sequence signal discretize produced.But adopt and can increase the input of hardware and the complexity of hardware system in this way, because dsp chip used in the present invention has porch capturing function, therefore can be easy to the accurate measurement and the synchronous sampling by software that utilize this functional realiey frequency.AC signal, after anti-aliasing low-pass filtering, is kept signal by a voltage follower circuit, then gives Schmidt trigger shaping and obtains square wave.DSP internal event manager has 6 capturing units, corresponding one of each capturing unit catches input pin, by the setting to capturing unit control register, can configure and catch pin and detect rising edge, negative edge, rise and fall along the change of three kinds of level, utilize general purpose timer as the time base detected, the first-in first-out register that user can read capturing unit determines to catch for twice the time of saltus step, i.e. signal period T, thus determines the frequency of lock-on signal.
Three, synchronous sampling by software
Calculate sampling period Ts according to sampling number (256 point) after calculating signal period T, with Ts, signal is sampled.
1, A/D sample circuit, a kind of high speed, hyperchannel, 14 modulus conversion chip MAXl25 that the present embodiment A/D sample circuit adopts MAXIM company to release, this chip internal with one 14, switching time is the gradual approaching of 3ps. number conversion circuit (ADC), the RAM that 4x is 14, can preserve 4 tunnel sampled datas.Also have 4 sample/hold circuits in sheet, l analog input (have 8 analog input channels, 4 is a group, is divided into A and B two groups) is selected in corresponding one 2 of the input of each sample/hold circuit, exports and selects 1 switch to A/D converter through 4.Native system is synchronous acquisition A phase voltage, electric current first, this 4 road signal of B phase voltage, electric current, after EOC, MAXl25 produces a look-at-me to DSP, DSP reads 4 tunnel sampled value con current control words to MAXl25, makes that it selects C phase voltage, electric current is sampled.Wherein the data of the asking transmission of MAXl25 and DSP is controlled by CPLD.
2, real time clock circuit, the present invention uses real-time clock SD2000 as external clock chip, this built-in chip type crystal oscillator, supports 12C bus interface, can ensure that clock accuracy is scholar 4ppm (at 1 DEG C, 25 soil), and namely error is less than 2 minutes year; Internal battery, serial NVSRAM, wherein built-in disposable battery can to ensure that under outside power-down conditions built-in rechargeable battery can ensure that under a full condition internal operation clock time (can completely fill 200 times) more than more than 1 year to clock more than 5 years serviceable life; Built-in serial NVSRAM is Nonvolatile sram, and erasable number of times can reach 10,000,000,000 times.Due to its internal non-volatile SRAM, therefore can be used as depositing of power down protection and initializes configuration information, in addition can also store more than 50 power down and upper electrographic recording.
3, liquid crystal display circuit, LCD that the present invention selects display is by the OCMl60x128 dot matrix LCD module of T6963 chip controls, can display graphics and a whole screen 10x8 Chinese character, character and image blend can also be shown, powerful.This module adopts single supply (+5V) power supply, does not need other voltages external, brings great convenience to hardware design.OCMl60 × 128 dot matrix LCD module includes controller T6963, its maximum feature has unique hardware initialization function, parameter required for display driver is arranged by pin level, and therefore the initialization of T6963 completes with regard to basic setup when powering on.In addition, it also has very strong software control ability, realizes module control by master cpu by the instruction of interface write Liquid Crystal Module.
Four, native system is the electric energy quality monitoring system based on DSP, its index of mainly monitoring has: three-phase voltage, current effective value, meritorious, reactive power, electric voltage frequency, tri-phase unbalance factor, each harmonic voltage, electric current containing ratio, power factor (PF), voltage, frequency departure, voltage fluctuation and flickering.Simultaneity factor has record and preserves power-off time, the human-computer interaction interface of LCD and keying, and the data of FLASH and SD card store, the functions such as UART serial communication and GPRS communication.The electric energy quality test system that the present invention is based on DSP carries out electric energy quality test flow process as shown in Figure 2, specifically comprises following process:
1, A/D sampling
Fig. 3 is A/D sampling process flow diagram: A/D sampling routine comprises the real-time calculating of sample frequency and these two parts of control of sampling process.According to the principle of FFT, the sample frequency error that directly can have influence on FFT result of calculation whether synchronous with periodic signal actual frequency.If asynchronous sampling, will spectrum leakage be produced, very large error can be caused like this in harmonic measure, so must strict guarantee sample frequency and actual frequency consistent.The realization of synchronized sampling has two kinds of methods to solve, and one is Hardware synchronous sampling, uses outside phaselocked loop real-time follow-up signal frequency; Second method is synchronous sampling by software, is calculated the frequency of signal by software in real time.Each cycle is sampled 256 points, and power frequency period is the clock frequency of 50Hz, DSP is 150MHz, so the periodic quantity precision of being caught by CAPl is higher.
2, as follows see Fig. 4, FFT process: the core of DSP program is fast fourier transform (FFT), and the quality of this program design is directly connected to the performance of whole system.The FFT library module that the present invention uses TI company to design for 2000 series DSP specially, this module is with entrance and exit parameter, easy to use, has good portability.After 256 point samplings terminate, successively invocation bit inverted rotor program, windowed function subroutine, 128 multiple FFT subroutines, be separated obtain 256 real FFT bear fruit program, be subordinate to width sequence.
3, LCD display routine, as shown in Figure 5, LCD program comprises two parts: bottom layer driving and interface display.The subroutines such as bottom layer driving mainly comprises write command, writes data, cls, time delay.Interface display program is mainly used to display measurement data, comprise current time, frequency, power factor (PF), three-phase voltage/electric current, three-phase meritorious/reactive power, positive sequence/negative sequence component, degree of unbalancedness, voltage/current total harmonic distortion, active electrical degree, idle electric degree, zero-sequence current and system operation time.The data-interface of LCD is connected by CPLD and DSP with control interface, and the address of data-interface is 0x2400, and the address of control interface is 0x2800, sends data and control command respectively by accessing different addresses to LCD.Because the data line that DSP extends out has 16, and the data bit of LCD only has 8, so we have only used the least-significant byte extending out data line when accessing LCD.
Because the clock period of DSP is 150MHz, and T6963 minimum settling time is l00ns, does not mate so can produce clock in read and write access.In order to make processor consistent with slow device speed, can be generally that DSP inserts waiting status by the method for hardware and software, the present invention adopts the method for software to realize the timing synchronization between the same LCD at a slow speed of DSP fast.
To those skilled in the art, obviously the invention is not restricted to the details of above-mentioned one exemplary embodiment, and when not deviating from spirit of the present invention or essential characteristic, the present invention can be realized in other specific forms.Therefore, no matter from which point, all should embodiment be regarded as exemplary, and be nonrestrictive, scope of the present invention is limited by claims instead of above-mentioned explanation, and all changes be therefore intended in the implication of the equivalency by dropping on claim and scope are included in the present invention.Any Reference numeral in claim should be considered as the claim involved by limiting.
The above; be only preferred embodiment of the present invention; not in order to limit the present invention, every above embodiment is done according to technical spirit of the present invention any trickle amendment, equivalently replace and improve, within the protection domain that all should be included in technical solution of the present invention.
Claims (4)
1. the electric energy quality test system based on DSP, it is characterized in that, comprise: be connected to voltage transformer (VT) summation current transformer in electrical network, signal conditioning circuit and DSP minimum system, described voltage transformer (VT) summation current transformer is connected with described signal conditioning circuit respectively, A/D sample circuit and frequency acquisition circuit is connected between described signal conditioning circuit and DSP minimum system, described DSP minimum system is connected with CPLD internal logic circuit, and described CPLD internal logic circuit is connected with LCD display, real-time clock, GPRS module and RS232/485 interface.
2. according to claim 1 based on the electric energy quality test system of DSP, it is characterized in that: described DSP minimum system is TMS320F2812 chip.
3. according to claim 2 based on the electric energy quality test system of DSP, it is characterized in that: described TMS320F2812 chip is connected with FLASH, SRAM, SD card and key cell.
4. according to claim 1 based on the electric energy quality test system of DSP, it is characterized in that: described TMS320F2812 chip is connected with TPS767D318 power supply chip.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105548786A (en) * | 2016-03-04 | 2016-05-04 | 国网山东省电力公司平原县供电公司 | Electric energy quality monitoring device |
| CN106124906A (en) * | 2016-08-01 | 2016-11-16 | 舒渝燕 | A kind of distributed power equipment on-line monitoring method |
| CN106291176A (en) * | 2016-08-01 | 2017-01-04 | 舒渝燕 | A kind of distributed power equipment on-line monitoring system |
| CN107609435A (en) * | 2017-09-21 | 2018-01-19 | 中国科学院长春光学精密机械与物理研究所 | A kind of SD read-write equipments based on DSP |
| CN107843781A (en) * | 2017-10-20 | 2018-03-27 | 国家电网公司 | Electric energy quality monitoring analysis system |
| CN110311418A (en) * | 2019-06-28 | 2019-10-08 | 盐城工学院 | The interconnected network frequency model predictive controller and control method of meter and power allocation factor |
-
2014
- 2014-08-12 CN CN201410395307.6A patent/CN104297583A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105548786A (en) * | 2016-03-04 | 2016-05-04 | 国网山东省电力公司平原县供电公司 | Electric energy quality monitoring device |
| CN106124906A (en) * | 2016-08-01 | 2016-11-16 | 舒渝燕 | A kind of distributed power equipment on-line monitoring method |
| CN106291176A (en) * | 2016-08-01 | 2017-01-04 | 舒渝燕 | A kind of distributed power equipment on-line monitoring system |
| CN107609435A (en) * | 2017-09-21 | 2018-01-19 | 中国科学院长春光学精密机械与物理研究所 | A kind of SD read-write equipments based on DSP |
| CN107843781A (en) * | 2017-10-20 | 2018-03-27 | 国家电网公司 | Electric energy quality monitoring analysis system |
| CN110311418A (en) * | 2019-06-28 | 2019-10-08 | 盐城工学院 | The interconnected network frequency model predictive controller and control method of meter and power allocation factor |
| CN110311418B (en) * | 2019-06-28 | 2023-10-03 | 盐城工学院 | Interconnected power grid frequency model prediction controller considering power distribution factors and control method |
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Application publication date: 20150121 |