CN104270146B - A kind of phase frequency detector for catastrophic failure detection on phaselocked loop piece - Google Patents
A kind of phase frequency detector for catastrophic failure detection on phaselocked loop piece Download PDFInfo
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Abstract
The invention discloses a kind of phase frequency detector for catastrophic failure detection on phaselocked loop piece, including clock generating unit, periodic sampling unit, charge-discharge control unit, phase frequency probe unit；Wherein clock generating unit, produces two clock control signals, it is no longer necessary to the test control signal outside piece from reference signal, saves input controlling switch；Periodic sampling unit, different cycles delays are completed using d type flip flop, to produce charging measurement and discharge test signal, the charge-discharge test signal resource outside piece are saved；Charge-discharge control unit, control circuit working state and testing process, enable to be automatically performed on test job piece；Phase frequency probe unit, is completed to reference signal and the frequency and phase discrimination of test signal volume.Provided by the present invention for phaselocked loop catastrophic failure detect phase frequency detector structure, with digital, automatic test, low cost the characteristics of.
Description
Technical field
The present invention relates to a kind of phase frequency detector for catastrophic failure detection on phaselocked loop piece, belong to phase-locked loop circuit
On-chip testing technology.
Background technology
Phaselocked loop (PLL) is widely used in frequency synthesis, phase demodulating, clock distribution and time recovery, is channel radio
Letter, optical fiber link and the essential part of microcomputer, need correct verification.However, due to phaselocked loop closed loop feedback and
Mixed signal characteristic, becomes one of the circuit for being most difficult to test, interior at the international level to its test to turn into one and urgently solve
Problem certainly, therefore, the on-chip testing scheme of research phase-locked loop circuit are significant.
PLL fault testing methods mainly levy the failure caused by defect present in structure to circuit, phase-locked loop circuit
In hide failure often influence the performance of phaselocked loop.By detecting that whether there is failure in circuit can quickly judge to lock phase
Whether ring is qualified.And because detection circuit can generally utilize the circuit structure existed in phaselocked loop, therefore general test
Cost is relatively low.During batch testing, catastrophic failure detection turns into a kind of effective ways that fast and low-cost tests phaselocked loop.
Fault testing method must resolve following problem on the piece of phaselocked loop：1st, self-inspection and output result is just on piece
In viewing；The great number testing expense produced without outside high-end tester, only completes self-inspection, to reduce survey by on-chip testing
The cost of examination.2nd, the performance impact to phaselocked loop is smaller；Shadow of the test circuit additionally added to existing phase-locked loop circuit performance
On the one hand ring can influence the normal work of qualified phaselocked loop, on the other hand can also reduce the accuracy rate of test.3rd, analog node is difficult
The problem of loading, try not to open loop, try not to open loop in analog node.4th, digital test circuit and test
Output, to ensure that the result of test is relatively reliable.5th, balance is reached between testing time, testing cost and test accuracy rate；
Phaselocked loop is converted directly into electricity as unique mixed signal circuit on most of on-chip systems, its testing time, testing cost
The production cost of sub- product, and be able to may also influence must between the performance of whole electronic product, therefore three for its test accuracy rate
It must coordinate.
And traditional phase frequency detector applied to phaselocked loop, can only be detected in phaselocked loop normal work reference signal and
The phase difference or difference on the frequency of feedback signal.To meet the catastrophic failure test of phaselocked loop, increasing Test Engineer
Begin to focus on and the frequency discrimination that can be applied to the detection of phaselocked loop catastrophic failure with digital, automatic test, low cost is reflected
The research of phase device.First, phase frequency detector makes improvements the performance to phaselocked loop as the numerical portion of phase-locked loop circuit
Influence is smaller；Secondly, the phase frequency detector with digital test characteristic so that test result is relatively reliable；Again, it is automatic to survey
The test of examination can be reduced the testing time；Finally, inexpensive test is especially suitable for the batch testing of phaselocked loop.Therefore, study
Detected suitable for phaselocked loop catastrophic failure, the phase frequency detector with digital, automatic test, low cost has great
Research Significance.
The content of the invention
Goal of the invention：In order to overcome the deficiencies in the prior art, the present invention provides a kind of for calamity on phaselocked loop piece
The phase frequency detector of difficulty fault detect, with digital, automatic test, low cost the characteristics of, phaselocked loop can be automatically performed
Charge-discharge test, complete the detection to the catastrophic failure of phaselocked loop.
Technical scheme：To achieve the above object, the technical solution adopted by the present invention is：
A kind of phase frequency detector for catastrophic failure detection on phaselocked loop piece, by between reference signal and test signal
Time difference be converted to data signal output and can automatically to phaselocked loop carry out charge-discharge test, specifically include clock generation singly
Member, periodic sampling unit, charge-discharge control unit and phase frequency probe unit：
Reference signal meets input end of clock CLK, the input end of clock CLK of periodic sampling unit of clock generating unit simultaneously
With the reference clock input clk_ref of charge-discharge control unit, the test signal that test signal connects charge-discharge control unit is defeated
Enter and hold clk_test, commencing signal meets the testing and control input test of charge-discharge control unit；
The three frequency division clock output signal CLK1 of clock generating unit connects the reset terminal of periodic sampling unit！CLR, clock production
Six frequency-dividing clock output signal CLK2 of raw unit meet the control signal input control of charge-discharge control unit；
The period 1 sampled output signal cycle0 of periodic sampling unit connects the period 1 letter of charge-discharge control unit
Number input cycle0, the second round sampled output signal cycle1 of periodic sampling unit connect the second of charge-discharge control unit
Periodic signal input cycle1, the period 3 sampled output signal cycle2 of periodic sampling unit connects charge-discharge control unit
Period 3 signal input part cycle2；
First clock output signal clk_out1 of charge-discharge control unit connects the first signal of phase frequency probe unit
Input ref, the second clock output signal clk_out2 of charge-discharge control unit connects the second letter of phase frequency probe unit
Number input var；
Phase frequency probe unit exports charging signals U and discharge signal D；
The clock signal difference automatic start periodic sampling unit and charge-discharge control unit produced by clock generating unit,
So as to the shifting to an earlier date or delay signal with different delayed time in the output of the output end of charge-discharge control unit, in this, as phase frequency
The input of probe unit produces alternate charge and discharge electric signal, for being detected to phaselocked loop catastrophic failure.
The clock generating unit includes two parts：
Part I, produces three frequency division clock output signal CLK1：Including the first trigger DFF1, the second trigger DFF2
With the 3rd trigger DFF3, reference signal meets the first trigger DFF1, the second trigger DFF2 and the 3rd trigger DFF3 simultaneously
Input end of clock, input supply voltage Vdd connects the first trigger DFF1, the second trigger DFF2 and the 3rd trigger simultaneously
DFF3 the RESET input；First trigger DFF1 the 3rd trigger DFF3 of D1 input terminations /Q3 output ends, the first triggering
Device DFF1 the second trigger DFF2 of Q1 output terminations D2 inputs, the first trigger DFF1 /Q1 output ends are hanging；Second
Trigger DFF2 the 3rd trigger DFF3 of Q2 output terminations D3 inputs, the second trigger DFF2 /Q2 output ends are hanging；
3rd trigger DFF3 Q3 output ends output three frequency division clock output signal CLK1；
Part II, produces six frequency-dividing clock output signal CLK2：Including the 4th trigger DFF4, the 5th trigger
DFF5, the 6th trigger DFF6, the 7th trigger DFF7, the 8th trigger DFF8 and the 9th trigger DFF9, reference signal are same
When connect the 4th trigger DFF4, the 5th trigger DFF5, the 6th trigger DFF6, the 7th trigger DFF7, the 8th trigger
DFF8 and the 9th trigger DFF9 input end of clock, input supply voltage Vdd connect the 4th trigger DFF4, the 5th trigger simultaneously
DFF5, the 6th trigger DFF6, the 7th trigger DFF7, the 8th trigger DFF8 and the 9th trigger DFF9 reset are inputted
End；4th trigger DFF4 the 9th trigger DFF9 of D4 input terminations /Q9 output ends, the 4th trigger DFF4 Q4 outputs
Terminate the 5th trigger DFF5 D5 inputs, the 4th trigger DFF4 /Q4 output ends are hanging；5th trigger DFF5 Q5
The 6th trigger DFF6 of output termination D6 inputs, the 5th trigger DFF5 /Q5 output ends are hanging；6th trigger DFF6
The 7th trigger DFF7 of Q6 output terminations D7 inputs, the 6th trigger DFF6 /Q6 output ends are hanging；7th trigger
DFF7 the 8th trigger DFF8 of Q7 output terminations D8 inputs, the 7th trigger DFF7 /Q7 output ends are hanging；8th touches
Send out device DFF8 the 9th trigger DFF9 of Q8 output terminations D9 inputs, the 8th trigger DFF8 /Q8 output ends are hanging；The
9 trigger DFF9 Q9 output ends export six frequency-dividing clock output signal CLK2.
The periodic sampling unit includes the tenth trigger DFF10, the 11st trigger DFF11 and the 12nd trigger
DFF12, reference signal simultaneously connect the tenth trigger DFF10, the 11st trigger DFF11 and the 12nd trigger DFF12 when
Clock input, three frequency division clock output signal CLK1 meets the tenth trigger DFF10, the 11st trigger DFF11 and the tenth simultaneously
Two trigger DFF12 the RESET input；Tenth trigger DFF10 D10 input termination input supply voltage Vdd, the tenth touches
Device DFF10 the 11st trigger DFF11 of Q10 output terminations D11 inputs are sent out, while the tenth trigger DFF10 Q10 is defeated
Go out end output period 1 sampled output signal cycle0, the 9th trigger DFF9 /Q9 output ends are hanging；11st trigger
DFF11 the 12nd trigger DFF12 of Q11 output terminations D12 inputs, while the 11st trigger DFF11 Q11 outputs
End output second round sampled output signal cycle1, the 11st trigger DFF11 /Q11 output ends are hanging；12nd triggering
Device DFF12 Q12 output ends output period 3 sampled output signal cycle2, the 12nd trigger DFF12 /Q12 outputs
End is hanging.
The charge-discharge control unit includes three multiselects being made up of full-digital circuit and switched, the knot of three multiselect switches
Structure is identical, and each multiselect switch includes a NOT gate NOT and three NAND gate NAND, and reseting input signal connects the defeated of NOT gate NOT
Enter end, signal A and NOT gate NOT output end connects the first NAND gate NAND1 two inputs respectively, reseting input signal and
Signal B connects the second NAND gate NAND2 two inputs, the first NAND gate NAND1 output end and the second NAND gate respectively
NAND2 output end connects the 3rd NAND gate NAND3 two inputs, the 3rd NAND gate NAND3 output end output respectively
Signal out, tracer signal A input are A inputs, and B signal input is B inputs, and reset signal input is that set is defeated
Enter end, out signal output parts are output end out；
Three multiselect switches are called the first multiselect switch MUX1, the second multiselect switch MUX2 and the 3rd multiselect switch respectively
MUX3：Period 1 sampled output signal cycle0 connects the A1 inputs that the first multiselect switchs MUX1, period 3 sampling output
Signal cycle2 connects the B1 inputs that the first multiselect switchs MUX1, and six frequency-dividing clock output signal CLK2 connect the first multiselect switch
MUX1 set1 inputs, the first multiselect switch MUX1 output end out1 connects the B2 inputs of the second multiselect switch；With reference to letter
The A2 inputs that the second multiselect switchs MUX2 number are connect, commencing signal connects the set2 inputs that the second multiselect switchs MUX2, more than second
Choosing switch MUX2 output end out2 exports the first clock output signal clk_out1；Test signal meets the 3rd multiselect switch MUX3
A3 inputs, second round sampled output signal cycle1 connects the B3 inputs that the 3rd multiselect switchs MUX3, and commencing signal connects
3rd multiselect switchs MUX3 set3 inputs, the 3rd multiselect switch MUX3 output end out3 output second clock output signals
clk_out2。
The phase frequency probe unit is conventional phase frequency detector, for detecting the first clock output signal clk_out1
Phase, difference on the frequency with second clock output signal clk_out2, so as to obtain corresponding charge and discharge electric signal；Phase frequency is detected
The input of unit meets the first clock output signal clk_out1 and second clock output signal clk_out2 respectively, and output end is defeated
Go out charging signals U and discharge signal D.
Beneficial effect：The phase frequency detector detected provided by the present invention for catastrophic failure on phaselocked loop piece, with complete
The characteristics of numeral, automatic test, low cost：First, reference signal is divided into the three frequency division clock produced by clock generating unit
Signal can automatically control the time of periodic sampling, and six fractional frequency signals automatically select Test input signal, filled so as to automatically control
The process of discharge test, therefore the phase frequency detector has the characteristics of testing automatically；Secondly, clock generating unit, periodic sampling
Unit, charge-discharge control unit and phase frequency probe unit are all made up of full-digital circuit, therefore the phase frequency detector
With it is digital the characteristics of so that the result of test is relatively reliable；Finally, due to whole circuit only need to several d type flip flops and
Multiselect is switched, and without external clock test signal, for the catastrophic failure detection of phaselocked loop, hardware spending and area
Expense is all less, thus the phase frequency detector have low cost the characteristics of.
Brief description of the drawings
Fig. 1 is used for the phase frequency detector structured flowchart of phaselocked loop catastrophic failure detection for the present invention's；
Fig. 2 is used for the phase frequency detector structure principle chart of phaselocked loop catastrophic failure detection for the present invention's,
Fig. 3 is used for the test flow chart of phaselocked loop catastrophic failure detection for the present invention's；
Fig. 4 is the timing diagram that phaselocked loop catastrophic failure is detected that is used for based on the present invention, wherein 4 (a) is normal mode,
4 (b) test pattern.
Fig. 5 is the test result that phaselocked loop catastrophic failure is detected that is used for based on the present invention, wherein 5 (a) is lock to be measured
Xiang Huan, 5 (b) is the influence to phase lock loop lock on time to be measured.
Embodiment
The present invention is further described below in conjunction with the accompanying drawings.
It is as shown in Figure 1 and Figure 2 a kind of phase frequency detector for catastrophic failure detection on phaselocked loop piece, will be with reference to letter
Time difference number between test signal is converted to data signal output and can be automatically to phaselocked loop progress charge-discharge test, specifically
Including clock generating unit, periodic sampling unit, charge-discharge control unit and phase frequency probe unit, specific attachment structure is such as
Under：
Reference signal meets input end of clock CLK, the input end of clock CLK of periodic sampling unit of clock generating unit simultaneously
With the reference clock input clk_ref of charge-discharge control unit, the test signal that test signal connects charge-discharge control unit is defeated
Enter and hold clk_test, commencing signal meets the testing and control input test of charge-discharge control unit；
The three frequency division clock output signal CLK1 of clock generating unit connects the reset terminal of periodic sampling unit！CLR, clock production
Six frequency-dividing clock output signal CLK2 of raw unit meet the control signal input control of charge-discharge control unit；
The period 1 sampled output signal cycle0 of periodic sampling unit connects the period 1 letter of charge-discharge control unit
Number input cycle0, the second round sampled output signal cycle1 of periodic sampling unit connect the second of charge-discharge control unit
Periodic signal input cycle1, the period 3 sampled output signal cycle2 of periodic sampling unit connects charge-discharge control unit
Period 3 signal input part cycle2；
First clock output signal clk_out1 of charge-discharge control unit connects the first signal of phase frequency probe unit
Input ref, the second clock output signal clk_out2 of charge-discharge control unit connects the second letter of phase frequency probe unit
Number input var；
Phase frequency probe unit exports charging signals U and discharge signal D；
The clock signal difference automatic start periodic sampling unit and charge-discharge control unit produced by clock generating unit,
So as to the shifting to an earlier date or delay signal with different delayed time in the output of the output end of charge-discharge control unit, in this, as phase frequency
The input of probe unit produces alternate charge and discharge electric signal, for being detected to phaselocked loop catastrophic failure.
The particular circuit configurations with regard to unit provide explanation below.
The clock generating unit includes two parts, and major function is that periodic sampling unit and charge-discharge control unit are provided
Control clock signal：Part I is used to produce three frequency division clock output signal CLK1, when Part II is used to produce six frequency dividings
Clock output signal CLK2.
Part I, produces three frequency division clock output signal CLK1：Including the first trigger DFF1, the second trigger DFF2
With the 3rd trigger DFF3, reference signal meets the first trigger DFF1, the second trigger DFF2 and the 3rd trigger DFF3 simultaneously
Input end of clock, input supply voltage Vdd connects the first trigger DFF1, the second trigger DFF2 and the 3rd trigger simultaneously
DFF3 the RESET input；First trigger DFF1 the 3rd trigger DFF3 of D1 input terminations /Q3 output ends, the first triggering
Device DFF1 the second trigger DFF2 of Q1 output terminations D2 inputs, the first trigger DFF1 /Q1 output ends are hanging；Second
Trigger DFF2 the 3rd trigger DFF3 of Q2 output terminations D3 inputs, the second trigger DFF2 /Q2 output ends are hanging；
3rd trigger DFF3 Q3 output ends output three frequency division clock output signal CLK1.
Part II, produces six frequency-dividing clock output signal CLK2：Including the 4th trigger DFF4, the 5th trigger
DFF5, the 6th trigger DFF6, the 7th trigger DFF7, the 8th trigger DFF8 and the 9th trigger DFF9, reference signal are same
When connect the 4th trigger DFF4, the 5th trigger DFF5, the 6th trigger DFF6, the 7th trigger DFF7, the 8th trigger
DFF8 and the 9th trigger DFF9 input end of clock, input supply voltage Vdd connect the 4th trigger DFF4, the 5th trigger simultaneously
DFF5, the 6th trigger DFF6, the 7th trigger DFF7, the 8th trigger DFF8 and the 9th trigger DFF9 reset are inputted
End；4th trigger DFF4 the 9th trigger DFF9 of D4 input terminations /Q9 output ends, the 4th trigger DFF4 Q4 outputs
Terminate the 5th trigger DFF5 D5 inputs, the 4th trigger DFF4 /Q4 output ends are hanging；5th trigger DFF5 Q5
The 6th trigger DFF6 of output termination D6 inputs, the 5th trigger DFF5 /Q5 output ends are hanging；6th trigger DFF6
The 7th trigger DFF7 of Q6 output terminations D7 inputs, the 6th trigger DFF6 /Q6 output ends are hanging；7th trigger
DFF7 the 8th trigger DFF8 of Q7 output terminations D8 inputs, the 7th trigger DFF7 /Q7 output ends are hanging；8th touches
Send out device DFF8 the 9th trigger DFF9 of Q8 output terminations D9 inputs, the 8th trigger DFF8 /Q8 output ends are hanging；The
9 trigger DFF9 Q9 output ends export six frequency-dividing clock output signal CLK2.
The periodic sampling unit gathers the rising edge clock of reference signal, has been delayed a reference signal clock week respectively
The rising edge of the rising edge of the reference signal of phase, the reference signal for the two reference signal clock cycle that have been delayed, so as to be charge and discharge
Electric control unit provides three input signals with different delayed time；Including the tenth trigger DFF10, the 11st trigger
DFF11 and the 12nd trigger DFF12, reference signal meets the tenth trigger DFF10, the 11st trigger DFF11 and simultaneously
12 trigger DFF12 input end of clock, three frequency division clock output signal CLK1 meets the tenth trigger DFF10, the tenth simultaneously
One trigger DFF11 and the 12nd trigger DFF12 the RESET input；Tenth trigger DFF10 D10 input termination inputs
Supply voltage Vdd, the tenth trigger DFF10 the 11st trigger DFF11 of Q10 output terminations D11 inputs, while the tenth
Trigger DFF10 Q10 output ends output period 1 sampled output signal cycle0 (the rising edge clock signal of reference signal
Cycle0), the 9th trigger DFF9 /Q9 output ends are hanging；11st trigger DFF11 Q11 outputs termination the 12nd is touched
Device DFF12 D12 inputs are sent out, while the 11st trigger DFF11 Q11 output ends output second round sampled output signal
Cycle1 (the reference signal rising edge cycle1 for having prolonged a reference signal clock cycle), the 11st trigger DFF11/
Q11 output ends are hanging；12nd trigger DFF12 Q12 output ends output period 3 sampled output signal cycle2 (prolongs
The reference signal rising edge cycle2 of two reference signal clock cycle), the 12nd trigger DFF12 /Q12 output ends hang
It is empty.
The charge-discharge control unit is in the presence of six sub-frequency clock signal CLK2, and every six clock cycle are alternately by the
One periodic sampling output signal cycle0, second round sampled output signal cycle1 or period 3 sampled output signal
Cycle2 and period 1 sampled output signal cycle1, thus for phase frequency detection unit provide with it is delayed delay or
Two input signals of advance time-delay.Switched including three multiselects being made up of full-digital circuit, the structure of three multiselect switches
Identical, each multiselect switch includes a NOT gate NOT and three NAND gate NAND, and reseting input signal connects NOT gate NOT input
End, signal A and NOT gate NOT output end connect the first NAND gate NAND1 two inputs, reseting input signal and letter respectively
Number B connects the second NAND gate NAND2 two inputs, the first NAND gate NAND1 output end and the second NAND gate respectively
NAND2 output end connects the 3rd NAND gate NAND3 two inputs, the 3rd NAND gate NAND3 output end output respectively
Signal out, tracer signal A input are A inputs, and B signal input is B inputs, and reset signal input is that set is defeated
Enter end, out signal output parts are output end out.
Three multiselect switches are called the first multiselect switch MUX1, the second multiselect switch MUX2 and the 3rd multiselect switch respectively
MUX3：Period 1 sampled output signal cycle0 connects the A1 inputs that the first multiselect switchs MUX1, period 3 sampling output
Signal cycle2 connects the B1 inputs that the first multiselect switchs MUX1, and six frequency-dividing clock output signal CLK2 connect the first multiselect switch
MUX1 set1 inputs, the first multiselect switch MUX1 output end out1 connects the B2 inputs of the second multiselect switch；With reference to letter
The A2 inputs that the second multiselect switchs MUX2 number are connect, commencing signal connects the set2 inputs that the second multiselect switchs MUX2, more than second
Choosing switch MUX2 output end out2 exports the first clock output signal clk_out1；Test signal meets the 3rd multiselect switch MUX3
A3 inputs, second round sampled output signal cycle1 connects the B3 inputs that the 3rd multiselect switchs MUX3, and commencing signal connects
3rd multiselect switchs MUX3 set3 inputs, the 3rd multiselect switch MUX3 output end out3 output second clock output signals
clk_out2。
The phase frequency probe unit is conventional phase frequency detector, for detecting the first clock output signal clk_out1
Phase, difference on the frequency with second clock output signal clk_out2, so as to obtain corresponding charge and discharge electric signal；Phase frequency is detected
The input of unit meets the first clock output signal clk_out1 and second clock output signal clk_out2 respectively, and output end is defeated
Go out charging signals U and discharge signal D.
Just the operation principle of the unit of the present invention is illustrated below.
The clock signal clk 1 and CLK2 produced by clock generating unit every three reference signal clock-resets one respectively
Periodic sampling unit provides two input signals and the charge and discharge of startup of every four reference signal clock cycle with the time difference
Electric control unit selection has shifting to an earlier date or delayed test signal for different delayed time, and the input in this, as phase frequency probe unit comes
Alternate charge and discharge electric signal is produced, for the detection to phaselocked loop catastrophic failure.
The Part I of clock generating unit, the three frequency division clock signal clk 1 for producing reference signal is used as periodic sampling list
The reset signal of member, including the first trigger DFF1, the second trigger DFF2 and the 3rd trigger DFF3.I.e. every three with reference to letter
Number clock cycle resets once to periodic sampling unit, the rising edge of next three frequency division clock, and periodic sampling unit is again again
Start sampling, so as to constantly provide test signal output for subsequent conditioning circuit.
The Part II of clock generating unit, the six sub-frequency clock signal CLK2 for producing reference signal are used as charge and discharge control
The control signal of unit, including the 4th trigger DFF4, the 5th trigger DFF5, the 6th trigger DFF6, the 7th trigger
DFF7, the 8th trigger DFF8 and the 9th trigger DFF9.I.e. every six reference signal clock cycle start charge and discharge control list
Member once, according to the phase frequency difference of input signal filled by the rising edge of next six frequency-dividing clock, charge-discharge control unit
Electric discharge.
Periodic sampling unit includes the tenth trigger DFF10, the 11st trigger DFF11 and the 12nd trigger
DFF12；Sampling exports the rising edge cycle0 of reference signal, the reference signal for the reference signal clock cycle that has been delayed respectively
Rising edge cycle1, the reference signal rising edge cycle1 for the two reference signal clock cycle that have been delayed.
Charge-discharge control unit includes the first multiselect switch MUX1, the second multiselect switch MUX2 and the 3rd multiselect switch
MUX3.During charging, period 1 input signal cycle0 and period 3 input signal cycle1 is selected.Period 1 input letter
Number cycle0 carries the previous reference signal clock cycle than second round input signal cycle1.During electric discharge, the period 3 is selected
Input signal cycle2 and second round input signal cycle1.Period 3 input signal cycle2 is inputted than second round to be believed
Number cycle1 delayed reference signal clock cycle.Charge-discharge control unit by clock generating unit six divided output signals
CLK2 is controlled, and every six reference signal clock cycle reselect the input signal of a phase frequency probe unit.
Phase frequency probe unit is identical with conventional tri-state phase frequency detector structure, as detecting the first output signal
Clk1_out and the second output signal clk2_out phase and difference on the frequency, so as to obtain corresponding charge and discharge electric signal.
The phase frequency detector of this case has two kinds of mode of operations.During normal mode of operation, phase frequency detection unit detection ginseng
Examine between signal and pll feedback signal phase frequency difference there is provided the clock signal of system.During test pattern, produced by clock
Raw unit produces two clock signals, is respectively supplied to automatic cycle sampling unit and charge-discharge control unit, has to produce
The charge and discharge electric signal of out of phase difference on the frequency, so as to realize the catastrophic failure detection of phaselocked loop.
The present invention is described in further detail with embodiment below in conjunction with the accompanying drawings.
Fig. 1 is used for the phase frequency detector structured flowchart of phaselocked loop catastrophic failure detection for the present invention's.Fig. 2 is the present invention
Be used for phaselocked loop catastrophic failure detect phase frequency detector structure principle chart.Fig. 3 is used for phaselocked loop disaster for the present invention's
The test flow chart of property fault detect.Fig. 4 be based on the present invention be used for phaselocked loop catastrophic failure detect test when when
Sequence figure.Fig. 5 is the test result that phaselocked loop catastrophic failure is detected that is used for based on the present invention.Table 1 is the present invention for locking
The test result of phase ring catastrophic failure detection.
The failure measure of the new type digital phase locking loop built-in self-testing structure of the present invention of table 1
The phase frequency detector for being used for the detection of phaselocked loop catastrophic failure of the present invention is total it can be seen from Fig. 1, Fig. 2
Word circuit, and several triggers and variable connector are only needed to, for the catastrophic failure detection of phaselocked loop, the frequency and phase discrimination
The characteristics of device structure has digital, inexpensive.
It is of the invention as seen from Figure 3 to be used for the phase frequency detector that phaselocked loop catastrophic failure is detected, can be automatically complete
Into the charge-discharge test of phaselocked loop, so as to be detected to the catastrophic failure of phaselocked loop.Therefore the phase frequency detector structure has
The characteristics of having automatic test.
As seen from Figure 4, the phase frequency detector detected for phaselocked loop catastrophic failure of the invention, normal mode
When, phase frequency detection unit is that input signal is reference signal and feedback signal, and output signal is that phase frequency is poor increasingly
Small charge and discharge electric signal.During test pattern, input signal is the periodic sampling signal with different advance time-delays or delayed delay,
Input signal is alternate regular charge and discharge electric signal.
As seen from Figure 5, the phase frequency detector detected for phaselocked loop catastrophic failure of the invention, to lock phase to be measured
The performance impact of ring is smaller.Using the phase frequency detector that phaselocked loop catastrophic failure is detected that is used for of the present invention, and without using two
In the case of kind, the locking time of phaselocked loop to be measured is respectively 1.08us and 0.89us.
As can be seen from Table 1, the phase frequency detector detected for phaselocked loop catastrophic failure of the invention, to lock to be measured
When phase ring carries out catastrophic failure detection, total fault coverage is 98.75%, and fault coverage is higher.
Described above is only the preferred embodiment of the present invention, it should be pointed out that：For the ordinary skill people of the art
For member, under the premise without departing from the principles of the invention, some improvements and modifications can also be made, these improvements and modifications also should
It is considered as protection scope of the present invention.
Claims (5)
1. a kind of phase frequency detector for catastrophic failure detection on phaselocked loop piece, it is characterised in that：By reference signal and survey
Time difference between trial signal is converted to data signal output and can carry out charge-discharge test to phaselocked loop automatically, when specifically including
Clock generation unit, periodic sampling unit, charge-discharge control unit and phase frequency probe unit：
Reference signal meets the input end of clock CLK of clock generating unit, the input end of clock CLK of periodic sampling unit and filled simultaneously
The reference clock input clk_ref of control of discharge unit, test signal connects the test signal input of charge-discharge control unit
Clk_test, commencing signal meets the testing and control input test of charge-discharge control unit；
The three frequency division clock output signal CLK1 of clock generating unit connects the reset terminal of periodic sampling unit！CLR, clock produces single
Six frequency-dividing clock output signal CLK2 of member meet the control signal input control of charge-discharge control unit；
The period 1 signal that the period 1 sampled output signal cycle0 of periodic sampling unit connects charge-discharge control unit is defeated
Enter and hold cycle0, the second round sampled output signal cycle1 of periodic sampling unit connects the second round of charge-discharge control unit
Signal input part cycle1, the period 3 sampled output signal cycle2 of periodic sampling unit connect the of charge-discharge control unit
Three periodic signal input cycle2；
First clock output signal clk_out1 of charge-discharge control unit connects the first signal input of phase frequency probe unit
Hold ref, the second clock output signal clk_out2 of charge-discharge control unit connect phase frequency probe unit secondary signal it is defeated
Enter to hold var；
Phase frequency probe unit exports charging signals U and discharge signal D；
The clock signal difference automatic start periodic sampling unit and charge-discharge control unit produced by clock generating unit, so that
In output end output the shifting to an earlier date or delay signal with different delayed time of charge-discharge control unit, detected in this, as phase frequency
The input of unit produces alternate charge and discharge electric signal, for being detected to phaselocked loop catastrophic failure.
2. the phase frequency detector according to claim 1 for catastrophic failure detection on phaselocked loop piece, it is characterised in that：
The clock generating unit includes two parts：
Part I, produces three frequency division clock output signal CLK1：Including the first trigger DFF1, the second trigger DFF2 and
Three trigger DFF3, reference signal simultaneously connect the first trigger DFF1, the second trigger DFF2 and the 3rd trigger DFF3 when
Clock input, input supply voltage Vdd meets the first trigger DFF1, the second trigger DFF2 and the 3rd trigger DFF3 simultaneously
The RESET input；First trigger DFF1 the 3rd trigger DFF3 of D1 input terminations /Q3 output ends, the first trigger DFF1
The second trigger DFF2 of Q1 output terminations D2 inputs, the first trigger DFF1 /Q1 output ends are hanging；Second trigger
DFF2 the 3rd trigger DFF3 of Q2 output terminations D3 inputs, the second trigger DFF2 /Q2 output ends are hanging；3rd touches
Send out device DFF3 Q3 output ends output three frequency division clock output signal CLK1；
Part II, produces six frequency-dividing clock output signal CLK2：Including the 4th trigger DFF4, the 5th trigger DFF5,
Six trigger DFF6, the 7th trigger DFF7, the 8th trigger DFF8 and the 9th trigger DFF9, reference signal connect the 4th simultaneously
Trigger DFF4, the 5th trigger DFF5, the 6th trigger DFF6, the 7th trigger DFF7, the 8th trigger DFF8 and the 9th
Trigger DFF9 input end of clock, input supply voltage Vdd meets the 4th trigger DFF4, the 5th trigger DFF5, the 6th simultaneously
Trigger DFF6, the 7th trigger DFF7, the 8th trigger DFF8 and the 9th trigger DFF9 the RESET input；4th triggering
Device DFF4 D4 input termination the 9th trigger DFF9 /Q9 output ends, the 4th trigger DFF4 Q4 output termination the 5th touch
Send out device DFF5 D5 inputs, the 4th trigger DFF4 /Q4 output ends are hanging；5th trigger DFF5 Q5 outputs termination the
Six trigger DFF6 D6 inputs, the 5th trigger DFF5 /Q5 output ends are hanging；6th trigger DFF6 Q6 output ends
Connect the 7th trigger DFF7 D7 inputs, the 6th trigger DFF6 /Q6 output ends are hanging；7th trigger DFF7 Q7 is defeated
Go out the 8th trigger DFF8 of termination D8 inputs, the 7th trigger DFF7 /Q7 output ends are hanging；8th trigger DFF8's
The 9th trigger DFF9 of Q8 output terminations D9 inputs, the 8th trigger DFF8 /Q8 output ends are hanging；9th trigger
DFF9 Q9 output ends export six frequency-dividing clock output signal CLK2.
3. the phase frequency detector according to claim 1 for catastrophic failure detection on phaselocked loop piece, it is characterised in that：
The periodic sampling unit includes the tenth trigger DFF10, the 11st trigger DFF11 and the 12nd trigger DFF12, reference
Signal connects the tenth trigger DFF10, the 11st trigger DFF11 and the 12nd trigger DFF12 input end of clock, three simultaneously
Frequency-dividing clock output signal CLK1 connects the tenth trigger DFF10, the 11st trigger DFF11 and the 12nd trigger simultaneously
DFF12 the RESET input；Tenth trigger DFF10 D10 input terminations input supply voltage Vdd, the tenth trigger DFF10
Q10 output termination the 11st trigger DFF11 D11 inputs, while the tenth trigger DFF10 Q10 output ends output
Period 1 sampled output signal cycle0, the 9th trigger DFF9 /Q9 output ends are hanging；11st trigger DFF11's
The 12nd trigger DFF12 of Q11 output terminations D12 inputs, while the 11st trigger DFF11 Q11 output ends output
Second round sampled output signal cycle1, the 11st trigger DFF11 /Q11 output ends are hanging；12nd trigger
DFF12 Q12 output ends output period 3 sampled output signal cycle2, the 12nd trigger DFF12 /Q12 output ends
Vacantly.
4. the phase frequency detector according to claim 1 for catastrophic failure detection on phaselocked loop piece, it is characterised in that：
The charge-discharge control unit includes three multiselects being made up of full-digital circuit and switched, and the structure of three multiselect switches is identical,
Each multiselect switch includes a NOT gate NOT and three NAND gate NAND, and reseting input signal connects NOT gate NOT input, letter
Number A and NOT gate NOT output end connects B points of the first NAND gate NAND1 two inputs, reseting input signal and signal respectively
Do not connect the second NAND gate NAND2 two inputs, the first NAND gate NAND1 output end and the second NAND gate NAND2's
Output end connects the 3rd NAND gate NAND3 two inputs respectively, the 3rd NAND gate NAND3 output end output signal out,
Tracer signal A input is A inputs, and B signal input is B inputs, and reset signal input is set inputs, out
Signal output part is output end out；
Three multiselect switches are called the first multiselect switch MUX1, the second multiselect switch MUX2 and the 3rd multiselect switch MUX3 respectively：
Period 1 sampled output signal cycle0 connects the A1 inputs that the first multiselect switchs MUX1, period 3 sampled output signal
Cycle2 connects the B1 inputs that the first multiselect switchs MUX1, and six frequency-dividing clock output signal CLK2 connect the first multiselect switch MUX1's
Set1 inputs, the first multiselect switch MUX1 output end out1 connects the B2 inputs of the second multiselect switch；Reference signal connects
Two multiselects switch MUX2 A2 inputs, and commencing signal connects the set2 inputs that the second multiselect switchs MUX2, the second multiselect switch
MUX2 output end out2 exports the first clock output signal clk_out1；The A3 that test signal meets the 3rd multiselect switch MUX3 is defeated
Enter end, second round sampled output signal cycle1 connects the B3 inputs that the 3rd multiselect switchs MUX3, and commencing signal is connect more than the 3rd
Choosing switch MUX3 set3 inputs, the 3rd multiselect switch MUX3 output end out3 output second clock output signals clk_
out2。
5. the phase frequency detector according to claim 1 for catastrophic failure detection on phaselocked loop piece, it is characterised in that：
The phase frequency probe unit is phase frequency detector, for detecting that the first clock output signal clk_out1 and second clock are defeated
Go out signal clk_out2 phase, difference on the frequency, so as to obtain corresponding charge and discharge electric signal；The input of phase frequency probe unit
The first clock output signal clk_out1 and second clock output signal clk_out2, output end output charging signals U are met respectively
With discharge signal D.
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| CN1756080A (en) * | 2004-09-28 | 2006-04-05 | 富士通株式会社 | Semiconductor integrated circuit |
| CN1763552A (en) * | 2004-10-21 | 2006-04-26 | 扬智科技股份有限公司 | Jitter signal circuit device of phase-locked loop for built-in self-test and method thereof |
| CN104020453A (en) * | 2013-03-01 | 2014-09-03 | 富士通株式会社 | Electronic circuit, radar apparatus, and method of performing self-diagnosis on radar apparatus |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1756080A (en) * | 2004-09-28 | 2006-04-05 | 富士通株式会社 | Semiconductor integrated circuit |
| CN1763552A (en) * | 2004-10-21 | 2006-04-26 | 扬智科技股份有限公司 | Jitter signal circuit device of phase-locked loop for built-in self-test and method thereof |
| CN104020453A (en) * | 2013-03-01 | 2014-09-03 | 富士通株式会社 | Electronic circuit, radar apparatus, and method of performing self-diagnosis on radar apparatus |
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