CN104241250A - 用于形成接触件的掺杂保护层 - Google Patents
用于形成接触件的掺杂保护层 Download PDFInfo
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- CN104241250A CN104241250A CN201410234656.XA CN201410234656A CN104241250A CN 104241250 A CN104241250 A CN 104241250A CN 201410234656 A CN201410234656 A CN 201410234656A CN 104241250 A CN104241250 A CN 104241250A
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Classifications
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/28008—Making conductor-insulator-semiconductor electrodes
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- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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Abstract
本发明提供了形成半导体器件的机制的实施例。该半导体器件包括具有第一掺杂区和第二掺杂区的半导体衬底以及形成在半导体衬底上的栅叠层。该半导体器件也包括形成在栅叠层的侧壁上的主间隔件层。半导体器件还包括形成在主间隔件层和半导体衬底之间的保护层,并且保护层掺杂有四价元素。此外,该半导体器件包括形成在半导体衬底和栅叠层上的绝缘层以及形成在绝缘层内的接触件。该接触件具有与第一掺杂区相接触的第一部分且具有与第二掺杂区相接触的第二部分。第一部分比第二部分更深地延伸到半导体衬底中。本发明还提供了用于形成接触件的掺杂保护层。
Description
技术领域
本发明一般地涉及半导体技术领域,更具体地,涉及半导体器件及其形成方法。
背景技术
半导体集成电路(IC)行业已经历了快速发展。由于IC材料和设计方面技术的进步已生产了多代IC,其中,每一代都比上一代具有更小和更复杂的电路。然而,这些进步已增加了处理和制造IC的复杂度。
例如,接触件通常是形成在集成电路内的垂直互连结构,其将半导体器件的扩散区和/或栅电极连接至互连层。为了形成功能集成电路,形成在半导体衬底内的独立的半导体器件通常通过接触件彼此电连接。形成电连接至半导体衬底内的越来越小的半导体元件的接触件变得更困难。
因此,期望一种改进的技术,以形成半导体器件内的可靠接触件结构。
发明内容
为了解决现有技术中所存在的缺陷,根据本发明的一方面,提供了一种半导体器件,包括:半导体衬底,具有第一掺杂区和第二掺杂区;栅叠层,形成在所述半导体衬底上;主间隔件,形成在所述栅叠层的侧壁上;保护层,形成在所述主间隔件和所述半导体衬底之间,其中,所述保护层掺杂有四价元素;绝缘层,形成在所述半导体衬底和所述栅叠层的上方;以及接触件,形成在所述绝缘层内,其中,所述接触件具有与所述第一掺杂区相接触的第一部分,并且所述接触件具有与所述第二掺杂区相接触的第二部分,所述第一部分比所述第二部分更深地延伸到所述半导体衬底内。
在该半导体器件中,所述保护层包括氧化层。
在该半导体器件中,所述接触件的所述第一部分延伸到所述第一掺杂区中的第一距离处,并且所述第一距离在约至约的范围内。
在该半导体器件中,所述接触件的第二部分延伸到所述第二掺杂区中的第二距离处,并且所述第二距离在约至约的范围内。
在该半导体器件中,所述接触件和所述第二掺杂区的边界之间的距离在约至约的范围内。
在该半导体器件中,所述保护层的第一部分形成在所述栅叠层的侧壁上,并且所述保护层的第二部分夹置在所述主间隔件层的底部和所述半导体衬底之间。
在该半导体器件中,掺杂在所述保护层的第二部分内的四价元素的浓度高于掺杂在所述保护层的第一部分内的四价元素的浓度。
在该半导体器件中,所述保护层具有表面部分和下部,所述表面部分位于所述主间隔件层和所述下部之间,并且掺杂在所述表面部分内的四价元素的浓度高于掺杂在所述下部内的四价元素的浓度。
在该半导体器件中,所述接触件还电连接至所述栅叠层的栅电极。
根据本发明的另一方面,提供了一种半导体器件,包括:半导体衬底,具有源极和漏极(S/D)区和轻掺杂源极和漏极(LDD)区;栅叠层,形成在所述半导体衬底上;绝缘层,形成在所述半导体衬底和所述栅叠层上;以及接触件,形成在所述绝缘层内,其中,所述接触件具有与所述S/D区相接触的第一部分,所述接触件具有与所述LDD区相接触的第二部分,并且所述接触件的第一部分比所述接触件的第二部分更深地延伸到所述半导体衬底中。
该半导体器件还包括:保护层,形成在所述半导体衬底上并在所述栅叠层的侧壁上延伸,其中,所述保护层掺杂有四价元素。
在该半导体器件中,所述保护层的位于所述半导体衬底上的部分内的四价元素的浓度高于所述保护层在所述栅叠层的侧壁上延伸的部分的浓度。
在该半导体器件中,所述保护层是非化学计量SixO2层,其中,x大于1。
在该半导体器件中,所述四价元素包括Si、Ge、C、或它们的组合。
在该半导体器件中,所述保护层的厚度在约至约的范围内。
根据本发明的又一方面,提供了一种形成半导体器件的方法,包括:提供其上形成有栅叠层的半导体衬底;形成掺杂有四价元素的保护层以覆盖形成在所述半导体衬底内且紧邻所述栅叠层的第一掺杂区;在所述栅叠层的侧壁上形成主间隔件层以覆盖所述保护层;在所述保护层的上方形成绝缘层;在所述绝缘层内形成开口以露出形成在所述半导体衬底内的第二掺杂区;以及在所述开口内形成一个接触件。
在该形成半导体器件的方法中,在形成所述开口之后露出所述保护层,在露出所述第二掺杂区之后在所述第二掺杂区的上方生长自然氧化层,并且所述方法还包括在形成所述接触件之前,通过蚀刻工艺去除所述开口内的所述自然氧化层和所述保护层。
在该形成半导体器件的方法中,在所述蚀刻工艺中,所述自然氧化层的蚀刻速率高于所述保护层的蚀刻速率。
在该形成半导体器件的方法中,使用注入工艺进行用所述四价元素掺杂所述保护层的步骤。
在该形成半导体器件的方法中,在所述注入工艺过程中,注入的离子的主要运动方向基本垂直于所述半导体衬底的表面。
附图说明
为了更全面地理解实施例及其优势,现将结合附图所进行的以下描述作为参考,其中:
图1A至图1I是根据一些实施例示出形成半导体器件的工艺序列的截面图;
图2是根据一些实施例示出注入有四价元素的保护层的截面图;
图3A和图3B是根据一些实施例均示出半导体器件的保护层的截面图;
图4A是根据一些实施例示出半导体器件的接触件的截面图;
图4B是根据一些实施例示出半导体器件的接触件的截面图;以及
图5A和图5B是根据一些实施例均示出半导体器件的接触件的截面图。
具体实施方式
下面,详细讨论本发明的各实施例的制造和使用。然而,应该理解,可以在各种具体环境中实现这些实施例。所讨论的具体实施例仅仅是说明性的,而不用于限制本发明的范围。
图1A至图1I是根据一些实施例示出形成半导体器件的工艺序列的截面图。如图1A所示,提供了半导体衬底100。半导体衬底100可以是半导体晶圆(如硅晶圆)或半导体晶圆的一部分。在一些实施例中,半导体衬底100包括含有单晶体结构、多晶体结构或非晶结构的硅或锗的元素半导体材料。在一些其他实施例中,半导体衬底100包括化合物半导体,诸如碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、合金半导体(诸如,SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP、和/或它们的组合)。半导体衬底100也可包括多层半导体、绝缘体上硅(SOI)(诸如,绝缘体上硅或绝缘体上锗)、和/或它们的组合。
隔离结构102可选择地形成在半导体衬底100中以限定半导体衬底100中的各种有源区,并且以将相邻器件(例如,晶体管)的彼此电隔离。通过使用隔离技术(诸如,(但不限于)半导体的局部氧化(LOCOS)、浅沟槽隔离(STI)等)可形成隔离结构102。隔离结构102可包括氧化硅、氮化硅、氮氧化硅、掺氟硅玻璃(FSG)、低K介电材料、其他合适的材料、和/或它们的组合。在一些实施例中,隔离结构102的形成包括以下步骤:通过光刻工艺图案化半导体衬底100、在半导体衬底100中蚀刻沟槽(例如,通过使用干蚀刻、湿蚀刻、等离子体蚀刻工艺、和/或它们的组合)、以及(例如,通过使用化学汽相沉积工艺)用介电材料填充沟槽。在一些实施例中,被填充的沟槽可具有多层结构,诸如填充有氮化硅或氧化硅的热氧化衬里层。
如图1A所示,在半导体衬底100上形成栅叠层(诸如,栅叠层10和12)。在一些实施例中,在半导体衬底100上形成栅极绝缘层104。栅极绝缘层104可由氧化硅、氮氧化硅、高介电常数材料(高k材料)、和/或它们的组合制成。高介电常数材料可包括氧化铪(HfO2)、氧化硅铪(HfSiO)、氮氧化硅铪(HfSiON)、氧化钽铪(HfTaO)、氧化钛铪(HfTiO)、氧化锆铪(HfZrO)、其他合适的高k介电材料、和/或它们的组合。高k材料还可包括金属氧化物、金属氮化物、金属硅酸盐、过渡金属氧化物、过渡金属氮化物、过渡金属硅酸盐、金属氮氧化物、金属铝酸盐、硅酸锆、铝酸锆、氧化硅、氮化硅、氮氧化硅、氧化锆、氧化钛、氧化铝、二氧化铪-氧化铝(HfO2-Al2O3)合金、其他合适的材料、和/或它们的组合。可通过任何合适的工艺来形成栅极绝缘层104,诸如原子层沉积(ALD)、化学汽相沉积(CVD)、物理汽相沉积(PVD)、远程等离子体CVD(RPCVD)、等离子体增强CVD(PECVD)、金属有机CVD(MOCVD)、溅射、电镀、其他合适的工艺、和/或它们的组合。然后,例如通过使用CVD工艺或其他合适的工艺在栅极绝缘层104上形成诸如多晶硅层的栅电极层106。
然后,例如通过使用光刻工艺和蚀刻工艺图案化栅极绝缘层104和栅电极层106,使得形成包括栅叠层10和12的栅叠层。
在一些实施例中,在栅叠层10和12的侧壁上形成密封层108。然而,密封层108是可选的。密封层108由介电材料制成。介电材料可包括,例如,氮化硅、氧化硅、氮氧化硅、其他合适的材料、和/或它们的组合。通过使用合适的工艺(诸如,CVD工艺)在栅叠层10和12以及半导体衬底100的表面上沉积密封层108。然后,实施诸如干蚀刻工艺的蚀刻工艺,以部分地去除密封层108,使得密封层108仍保留在栅叠层10和12的相对侧壁上。当进行后续工艺步骤时,密封层108可防止栅叠层10和12被损坏。
接下来,在半导体衬底100内形成掺杂区110。例如,进行离子注入工艺,以在栅叠层10和12的相对侧上以及半导体衬底100内形成掺杂区110。在一些实施例中,掺杂区115是掺杂区110的邻近栅叠层10且位于密封层108下方的一部分,其用作轻掺杂源极/漏极区(LDD区)。因此,参考标号115也用于指定LDD区。在一些实施例中,以一定倾斜角度进行注入工艺,使得形成的LDD区115延伸到栅叠层10和12的下方。
如图1A所示,在栅叠层10和12以及半导体衬底100上形成保护层112。保护层112由介电材料制成。在一些实施例中,保护层112是氧化硅层。然而,也可使用其他介电层,诸如氮氧化层(例如,氮氧化硅层)。通过使用任何合适的工艺来形成保护层112,诸如化学汽相沉积(CVD)、原子层沉积(ALD)、等离子体增强CVD(PECVD)、远程等离子体CVD(RPCVD)、物理汽相沉积(PVD)、其他合适的工艺、和/或它们的组合。在一些实施例中,保护层112共形地形成在半导体衬底100和栅叠层10和12上。
在一些实施例中,保护层112的厚度在约至约的范围内。在一些其他实施例中,保护层112的厚度在约至约的范围内。然而,应该理解,本发明的实施例并不仅限于此。在其他实施例中,保护层112的厚度不同于上述的厚度。在一些实施例中,保护层112的厚度与自然氧化层的厚度相似。一方面,因为很难去除保护层112,所以保护层112的厚度不应该太厚。另一方面,因为在后续的注入工艺中注入的离子可能会穿透保护层112,所以保护层112也不应该太薄。
接下来,如图1B所示,进行掺杂工艺114,用一种或多种四价元素掺杂保护层112,以形成掺杂保护层112’,从而当掺杂保护层112’暴露于氧化蚀刻化学物质时能降低其蚀刻速率。换言之,与非掺杂保护层112或自然氧化层相比,在氧化蚀刻工艺(例如,氧化硅蚀刻工艺)中更难蚀刻掺杂有四价元素的掺杂保护层112’。合适的四价元素可包括硅(Si)、碳(C)、锗(Ge)等、和/或它们的组合。
可通过调整掺杂保护层112’的掺杂的四价元素的浓度来调整其蚀刻速率。掺杂保护层112’掺杂的四价元素的浓度越高,在其暴露给氧化蚀刻工艺时,蚀刻速率越低。然而,因为蚀刻速率可能会太高或可能出现其他问题(任何一种问题都是不希望出现的),所以掺杂保护层112’的四价元素的浓度不应该太高。在一些实施例中,掺杂在保护层112中的四价元素的浓度在约108原子/立方厘米至约1016原子/立方厘米的范围内。在一些实施例中,掺杂在保护层112中的四价元素的浓度在约1010原子/立方厘米至约1015原子/立方厘米的范围内。在一些实施例中,掺杂在保护层112中的四价元素的浓度在约106原子/立方厘米至约1014原子/立方厘米的范围内。在一些实施例中,掺杂保护层112’是注入硅(Si)的氧化硅层。因此,可形成非化学计量的SixO2层,且x大于1。
在一些实施例中,通过使用诸如离子注入工艺的注入工艺来进行掺杂工艺114。四价元素注入有低能量,使得注入的四价元素的主要部分或全部都不会穿透掺杂保护层112’并且到达掺杂保护层112’下方的结构。在一些实施例中,注入的四价元素基本位于掺杂保护层112’的表面部分内。在一些其他实施例中,采用等离子体注入工艺以使掺杂保护层112’注入有四价元素。
在一些实施例中,离子注入工艺的注入能量在约0.3KeV至约2KeV的范围内。在一些其他实施例中,注入能量在约0.5KeV至约1KeV的范围内。应该认真选择注入能量,以防止注入的四价元素到达掺杂保护层112’下方的元件。可根据选择的要被掺杂的四价元素的种类和/或保护层112的厚度来调整注入能量。
图2是根据一些实施例示出注入有四价元素的掺杂保护层112’的截面图,并且相同的参考标号用于指定相同的元件。如图2所示,掺杂保护层112’包括表面部分402和下部404,其分别具有厚度t1和t2。注入的四价元素主要或完全位于表面部分402内。在一些实施例中,表面部分402的厚度t1在约至约的范围内。在一些实施例中,厚度t1和掺杂保护层112’的总厚度之间的比率(即,t1/(t1+t2))在约1/8至约1/2的范围内。在一些其他实施例中,厚度t1和总厚度之间的比率(t1/t1+t2)在约1/4至约1/3的范围内。然而,应该理解,本发明的实施例不仅限于此。在其他实施例中,注入的四价元素均匀地分布在掺杂保护层112’内。在一些其他实施例中,注入在掺杂保护层112’内的四价元素的浓度沿着从表面部分402向下部404的方向逐渐降低。
在一些实施例中,将一种以上的四价元素注入到掺杂保护层112’中。例如,采用两种以上的注入工艺将两种以上的四价元素注入到掺杂保护层112’中。可选地,通过使用单个注入工艺可将一种以上的四价元素注入到掺杂保护层112’内。例如,在单个注入工艺或单独的注入工艺中,可以将硅(Si)和碳(C)或硅(Si)和锗(Ge)注入到氧化硅层。在一些其他实施例中,将图案化的掩模层(未示出)设置在离子源和保护层112之间,使得注入的四价元素基本上仅位于图案化的掩模层的开口下方的特定区内。
此外,在一些实施例中,通过使用注入工艺进行掺杂工艺114。如图所示,在离子注入工艺过程中注入的离子的主要运动方向(如图1B中箭头所示)基本上垂直于半导体衬底100的表面(例如,主顶面)。然而,本发明的实施例并不限于此。在一些其他实施例中,以倾斜的角度进行四价元素的注入工艺。
图3A和图3B是根据一些实施例均示出图1B所示结构的一部分的放大截面图,并且相同的参考数字用于指定相同的元件。如图3A所示,掺杂保护层112’具有位于栅叠层10的侧壁上的部分304和位于半导体衬底100上的部分302。参考数字“306”标示的圆圈用于表示掺杂的四价元素的分布。如图3A所示,掺杂的四价元素306在部分302内的浓度高于掺杂的四价元素306在部分304内的浓度。在一些其他实施例中,如图3B所示,位于栅叠层10的侧壁上的部分304基本上没有掺杂额外的四价元素。掺杂的四价元素306主要或完全位于掺杂保护层112’的部分302和顶端的水平部分内。在一些实施例中,与图2所示的结构相似,掺杂的四价元素306主要位于掺杂保护层112’的表面部分内。掺杂保护层112’的部分302和304可一起形成L形层或类L形的层。换言之,掺杂保护层112’可具有位于半导体衬底100上的部分且具有进一步延伸到栅叠层10的侧壁上的其他部分。
参照图1C,然后在栅叠层10和12的侧壁上形成主间隔件层118以覆盖掺杂保护层112’的部分。主间隔件层118可由介电层形成,诸如氮化硅层、氮氧化硅层、或它们的组合。通过使用诸如CVD工艺的合适的工艺将主间隔件层118沉积在栅叠层10和12以及半导体衬底100上,然后通过使用诸如干蚀刻工艺的蚀刻工艺蚀刻该主间隔件层118,以具有图1C所示的结构。
接下来,使用蚀刻工艺去除未被主间隔件层118覆盖的掺杂保护层112’。也去除掺杂保护层112’的顶端的水平部分。形成附加的掩模无需附加的光刻工艺。因此也降低了制造成本和制造时间。可通过湿蚀刻、干蚀刻、和/或它们的组合进行蚀刻工艺。例如,使用含氟化氢(HF)的溶液去除未被覆盖的掺杂保护层112’,因此,图案化掺杂保护层112’。可选地,在一些其他实施例中,图案化的光刻胶层形成在掺杂保护层112’上,且进行蚀刻工艺使得掺杂保护层112’具有理想的图案。
参照图1C和图2,在一些实施例中,掺杂保护层112’的表面部分402位于主间隔件层118和掺杂保护层112’的下部404之间。掺杂有较高浓度的四价元素的表面部分402紧邻主间隔件层118。
如图1C所示,在半导体衬底100内形成掺杂区120。例如,使用离子注入工艺在半导体衬底100内形成掺杂区120。在一些实施例中,掺杂区120是重掺杂源极/漏极区(S/D区)。在一些实施例中,以倾斜的角度进行S/D注入工艺。在进行S/D注入工艺之后,可进行退火工艺,诸如快速热处理(RTP),以修复S/D区内的硅晶体结构且活化S/D区内的掺杂物。
接下来,如图1D所示,可选择地进行自对准硅化(自对准硅化物)工艺以分别在栅电极层106和掺杂区120(诸如S/D区)上形成金属硅化物区122a和122b。例如,将金属膜沉积在半导体衬底100上以与露出的硅化物表面(诸如,栅电极层106和掺杂区120(例如,S/D区)的表面)直接接触。可以实施任何合适的工艺,诸如PVD工艺、CVD工艺、电镀工艺、化学镀工艺等,以形成金属膜。然后实施加热操作以使沉积的金属膜和露出的硅表面之间发生反应,从而分别形成金属硅化物区122a和122b。然后,例如通过使用蚀刻工艺去除沉积的金属膜的非反应部分。硅化物区122a和122b可从露出的硅化物表面的原表面中凸起。尤其在较小的几何尺寸中,硅化物区122a和122b的电阻低于非硅化区的电阻。
沉积的金属膜的材料可包括镍。因此,可形成包括Ni2Si、NiSi2、NiSi、和/或它们的组合的镍硅化物区。也可使用其他合适的金属材料(诸如,钴(Co)、镍(Ni)、铂(Pt)、钛(Ti)、镱(Yb)、钼(Mo)、铒(Er)、和/或它们的组合)来形成金属硅化物区。金属硅化物区122b可理解为掺杂区120的一部分,诸如S/D区,并且金属硅化物区122a可理解为栅电极层106的一部分。
如图1D所示,然后将接触蚀刻停止层124可选地形成在半导体衬底100、主间隔件层118和金属硅化物区122a和122b上。接触蚀刻停止层124可包括氮化硅层。接触蚀刻停止层124的厚度可在约至约的范围内。接触蚀刻停止层124可共形地沉积在半导体衬底100上。可以通过使用诸如CVD工艺的合适的工艺形成接触蚀刻停止层124。在一些实施例中,接触蚀刻停止层124也用作压力源层,其可增强半导体衬底100的沟道区内的载流子移动率,从而改进由此形成的半导体器件的操作。
然后,通过合适的工艺,诸如CVD工艺、HDPCVD工艺、旋涂工艺、溅射工艺、和/或它们的组合,在半导体衬底100和栅叠层10和12上形成绝缘层126。绝缘层126可包括任何合适的材料,如氧化硅、氮氧化硅、掺硼硅玻璃(BSG)、掺磷硅玻璃(PSG)、掺硼磷硅玻璃(BPSG)、掺氟硅玻璃(FSG)、低k材料、多孔介电材料、和/或它们的组合。然后可采用平坦化工艺,诸如化学机械抛光(CMP)等,使得绝缘层126可具有大致平坦的表面,从而有利于后续的工艺步骤。
如图1E所示,然后进行图案化工艺(包括例如,光刻工艺和蚀刻工艺)来部分地去除绝缘层126以形成开口(包括例如,开口128b和128s)。在一些实施例中,形成开口128b用以形成SRAM器件的对接接触件。从俯视图中所观看到的开口的形状可包括正方形、矩形、圆形、椭圆形等。开口128b和128s的形状可彼此不同。在一些实施例中,开口128b和128s从绝缘层126的大致平坦的表面延伸至先前形成的接触蚀刻停止层124的表面。用于蚀刻绝缘层126的蚀刻剂基本不蚀刻接触蚀刻停止层124或可以非常小的蚀刻速率蚀刻接触蚀刻停止层124。
接下来,如图1F所示,去除开口128b和128s内的接触蚀刻停止层124,使得露出金属硅化物区122a和122b。在一些实施例中,也可以将开口128内的主间隔件层118、位于栅叠层10的侧壁上的掺杂保护层112’的垂直部分、以及密封层108与接触蚀刻停止层124一起去除。因为掺杂保护层112’的垂直部分掺杂有较小量的四价元素并且具有较快的蚀刻速率(与LDD区115上的掺杂保护层112’相比),也可将掺杂保护层112’的垂直部分与接触蚀刻停止层124和主间隔件层118一起去除。在一些其他实施例中,可部分地保留开口128内的主间隔件层118、掺杂保护层112’的垂直部分、和/或密封层108的一些,使它们保持在开口128内。
如图1G所示,去除开口128b和128s内的接触蚀刻停止层124以露出栅叠层10和掺杂区120之后,在栅叠层10、掺杂区120、和/或金属硅化物区122b的露出表面上生长自然氧化层130。在去除下面的接触蚀刻停止层124之后,一旦露出栅叠层10和掺杂区120就可生长自然氧化层130。在一些实施例中,自然氧化层130是氧化硅层。生长的自然氧化层130的厚度可在约至约的范围内,该厚度范围与掺杂保护层112’的厚度范围相同。然而,在其他实施例中,自然氧化层130的厚度不同于上述范围。
接下来,如图1H所示,进行蚀刻工艺,诸如干蚀刻或HF浸渍,以去除露出的自然氧化层130(包括栅叠层10、掺杂区120和开口128s的底部上的自然氧化层130)和露出的掺杂保护层112’以露出掺杂区120(诸如,S/D区和/或S/D区上的金属硅化物区122b)。进行蚀刻工艺之后,也露出LDD区115。也可露出金属硅化物区122a和栅电极层106的侧表面。在一些实施例中,当与自然氧化层130相比较时,相对来说,更难蚀刻掺杂有四价元素的掺杂保护层112’。在蚀刻工艺中,自然氧化层130的蚀刻速率高于掺杂保护层112’的蚀刻速率。在一些实施例中,完全去除LDD区115上的掺杂保护层112’的部分。在一些其他实施例中,掺杂保护层112’的一小部分保留在LDD区115上。
通常,LDD区115很薄且可能由于过蚀刻而受损伤。由于存在掺杂保护层112’,所以在蚀刻工艺过程中不会过蚀刻LDD区115。没有掺杂保护层112’,LDD区115会被过蚀刻并且受损失,使得随后形成在开口128b内的接触件会延伸到LDD区115太多而导致漏电问题和/或短路问题。在一些情况下,随后形成在开口128b内的接触件甚至可能穿透LDD区115。一方面,图4A是根据一些实施例示出半导体器件的接触件结构的截面图,并且未使用掺杂保护层保护LDD区115。在自然氧化层的蚀刻工艺过程中,未受保护的LDD区115被过蚀刻。因此,形成的接触件132b和势垒层133深入地延伸到LDD区115以到达靠近半导体100内的一个区(诸如,阱区)的位置。另一方面,图4B是根据一些实施例示出半导体器件的接触件结构的截面图,并且使用掺杂保护层保护LDD区115。在这种情况下,由掺杂保护层保护的LDD区115未被过蚀刻,并且接触件132b和势垒层133没有太深入地延伸至接近半导体衬底100内的阱区。图4B所示的结构内的接触件132b和LDD区115的边界之间的距离w2明显大于图4A所示的距离w1。在一些实施例中,距离w1在约至约的范围内,并且大于距离w1的距离w2在约至约的范围内。因此,可降低和/或防止漏电问题和/或短路问题。
参照图1I,然后将导电材料填充在开口128b和128s内以形成接触件132b和132s。可以通过使用合适的工艺(诸如,PVD工艺、CVD工艺、溅射工艺、电镀工艺、化学镀工艺等、和/或组合工艺)形成导电材料以填充开口128b和128s。然后可进行平坦化工艺,诸如化学机械抛光工艺等,以去除开口128b和128s外部的多余的导电材料,从而分别形成接触件132b和132s。接触件132b和132s的材料包括钨、铜、铝、金、铂、镍、钛、其他合适的材料、和/或它们的组合。在一些实施例中,接触件132b与栅叠层10的栅电极层106直接接触。栅电极层106的侧壁直接连接至接触件132b。此外,形成接触件132b之前可选择地形成扩散势垒层133,以防止随后形成的接触件132b的金属材料扩散到绝缘层126内。
参照图1I、图3A和图3B,在一些实施例中,掺杂保护层112’(诸如栅叠层10的左侧上的掺杂保护层112’)具有位于栅叠层10的侧壁上的部分304和夹置在半导体衬底100和主间隔件层118(诸如,栅叠层10的左侧上的主间隔件层118)之间的部分302。位于部分302内的掺杂的四价元素306的浓度高于位于部分304内的掺杂的四价元素306的浓度。注入的四价元素306可主要位于掺杂保护层112’的表面部分内。在一些实施例中,使用次级离子质谱仪(SIMS)或其他合适的工具检测注入的四价元素的存在、分布、和/或浓度。
图5A和图5B是根据一些实施例示出半导体器件的接触件132b的截面图,并且相同的参考标号用于指定相同的元件。例如,图5A示出了图1I所示结构中的区R的放大截面图。在一些实施例中,进行蚀刻工艺去除LDD区115上的自然氧化层130和掺杂保护层112’之后,也去除金属硅化物区122b的一部分(也为掺杂区120(诸如S/D区)的一部分),使得开口128b进一步延伸到半导体衬底100中。在这种情况下,形成的接触件132b可具有延伸到掺杂区120或半导体衬底100内的部分232。例如,接触件132b的部分232延伸到掺杂区120(诸如S/D区)的金属硅化物区122b。接触件132b的部分232延伸到掺杂区120或半导体衬底100中的距离为d1。距离d1可在约至约的范围内。
在一些其他实施例中,如图5B所示的实施例,进行蚀刻工艺以去除覆盖LDD区115的自然氧化层130和掺杂保护层112’之后,还稍微地去除LDD区115的一部分,使得开口128b具有进一步延伸到半导体衬底100的第二部分。在这种情况下,形成的接触件132b不仅具有延伸到掺杂区120中的部分232还具有延伸到LDD区115中的部分234。接触件132b的部分234延伸到半导体衬底100或LDD区115中一段距离d2,其中,距离d2小于d1且可在约至约的范围内。换言之,接触件132b的部分232比接触件132b的部分234更深地延伸到半导体衬底100内。因为掺杂保护层112’的低蚀刻速率阻碍蚀刻工艺,所以能够防止接触件132b更多地延伸到LDD区115。因此可降低和/或防止漏电和/或短路。
形成上述半导体器件的机制的实施例能够降低对靠近栅极沟道的硅衬底的过蚀刻。通过形成掺杂保护层以覆盖靠近栅极沟道的硅衬底的表面,可控制且最小化过蚀刻。因此,能够防止随后形成的接触件太深延伸到硅衬底中而导致短路和/或漏电。
根据一些实施例,提供了一种半导体器件。该半导体器件包括具有第一掺杂区和第二掺杂区的半导体衬底、以及形成在半导体衬底上的栅叠层。半导体器件也包括形成在栅叠层的侧壁上的主间隔件层。半导体器件还包括形成在主间隔件层和半导体衬底之间的保护层。保护层掺杂有四价元素。此外,半导体器件包括形成在半导体衬底和栅叠层上方的绝缘层、以及形成在绝缘层内的接触件。接触件具有与第一掺杂区相接触的第一部分且具有与第二掺杂区相接触的第二部分。第一部分比第二部分更深地延伸到半导体衬底。
根据一些实施例,提供了一种半导体器件。该半导体器件包括具有源极和漏极(S/D)区和轻掺杂源极和漏极(LDD)区的半导体衬底。半导体器件也包括形成在半导体衬底上的栅叠层和形成在半导体衬底和栅叠层上的绝缘层。半导体器件还包括形成在绝缘层内的接触件。接触件具有与S/D区相接触的第一部分且具有与LDD区相接触的第二部分。接触件的第一部分比接触件的第二部分更深地延伸到半导体衬底。
根据一些实施例,提供了一种形成半导体器件的方法。该方法包括提供具有形成在半导体衬底上的栅叠层的半导体衬底。该方法还包括形成掺杂有四价元素的保护层以覆盖形成在半导体衬底中且临近栅叠层的第一掺杂区。该方法还包括在栅叠层的侧壁上形成主间隔件层以覆盖保护层,以及在保护层的上方形成绝缘层。此外,该方法包括在绝缘层内形成开口以露出形成在半导体衬底内的第二掺杂区以及在开口内形成接触件。
尽管已经详细地描述了本发明及其优势,但应该理解,可以在不背离所附权利要求限定的本发明主旨和范围的情况下,做各种不同的改变、替换和更改。而且,本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解,通过本发明,现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结构的工艺、机器、制造、材料组分、装置、方法或步骤根据本发明可以被使用。因此,所附权利要求应该包括在这样的工艺、机器、制造、材料组分、装置、方法或步骤的范围内。此外,每条权利要求构成单独的实施例,并且多个权利要求和实施例的组合在本发明的范围内。
Claims (10)
1.一种半导体器件,包括:
半导体衬底,具有第一掺杂区和第二掺杂区;
栅叠层,形成在所述半导体衬底上;
主间隔件,形成在所述栅叠层的侧壁上;
保护层,形成在所述主间隔件和所述半导体衬底之间,其中,所述保护层掺杂有四价元素;
绝缘层,形成在所述半导体衬底和所述栅叠层的上方;以及
接触件,形成在所述绝缘层内,其中,所述接触件具有与所述第一掺杂区相接触的第一部分,并且所述接触件具有与所述第二掺杂区相接触的第二部分,所述第一部分比所述第二部分更深地延伸到所述半导体衬底内。
2.根据权利要求1所述的半导体器件,其中,所述保护层包括氧化层。
3.根据权利要求1所述的半导体器件,其中,所述接触件的所述第一部分延伸到所述第一掺杂区中的第一距离处,并且所述第一距离在约至约的范围内。
4.根据权利要求3所述的半导体器件,其中,所述接触件的第二部分延伸到所述第二掺杂区中的第二距离处,并且所述第二距离在约至约的范围内。
5.根据权利要求1所述的半导体器件,其中,所述接触件和所述第二掺杂区的边界之间的距离在约至约的范围内。
6.根据权利要求1所述的半导体器件,其中,所述保护层的第一部分形成在所述栅叠层的侧壁上,并且所述保护层的第二部分夹置在所述主间隔件层的底部和所述半导体衬底之间。
7.根据权利要求6所述的半导体器件,其中,掺杂在所述保护层的第二部分内的四价元素的浓度高于掺杂在所述保护层的第一部分内的四价元素的浓度。
8.根据权利要求1所述的半导体器件,其中,所述保护层具有表面部分和下部,所述表面部分位于所述主间隔件层和所述下部之间,并且掺杂在所述表面部分内的四价元素的浓度高于掺杂在所述下部内的四价元素的浓度。
9.一种半导体器件,包括:
半导体衬底,具有源极和漏极(S/D)区和轻掺杂源极和漏极(LDD)区;
栅叠层,形成在所述半导体衬底上;
绝缘层,形成在所述半导体衬底和所述栅叠层上;以及
接触件,形成在所述绝缘层内,其中,所述接触件具有与所述S/D区相接触的第一部分,所述接触件具有与所述LDD区相接触的第二部分,并且所述接触件的第一部分比所述接触件的第二部分更深地延伸到所述半导体衬底中。
10.一种形成半导体器件的方法,包括:
提供其上形成有栅叠层的半导体衬底;
形成掺杂有四价元素的保护层以覆盖形成在所述半导体衬底内且紧邻所述栅叠层的第一掺杂区;
在所述栅叠层的侧壁上形成主间隔件层以覆盖所述保护层;
在所述保护层的上方形成绝缘层;
在所述绝缘层内形成开口以露出形成在所述半导体衬底内的第二掺杂区;以及
在所述开口内形成一个接触件。
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106024888A (zh) * | 2015-03-25 | 2016-10-12 | 三星电子株式会社 | 包括面积增加的接触件的半导体器件 |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9136340B2 (en) * | 2013-06-05 | 2015-09-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Doped protection layer for contact formation |
KR101480788B1 (ko) * | 2014-03-27 | 2015-01-14 | 성균관대학교산학협력단 | 반도체 소자의 실리사이드 형성방법 및 반도체 소자용 소스/드레인 |
US10566187B2 (en) | 2015-03-20 | 2020-02-18 | Lam Research Corporation | Ultrathin atomic layer deposition film accuracy thickness control |
US9627474B2 (en) * | 2015-09-18 | 2017-04-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor devices and methods of fabricating the same |
US10867852B2 (en) * | 2015-12-15 | 2020-12-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and manufacturing method thereof |
WO2017111791A1 (en) * | 2015-12-23 | 2017-06-29 | Intel Corporation | Methods for obtaining ultra low defect density gan using cross point trench design |
US9818834B2 (en) * | 2016-01-07 | 2017-11-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device structure and method for forming the same |
CN110326088A (zh) * | 2017-03-30 | 2019-10-11 | 英特尔公司 | 用于制造环绕式接触部的金属化学气相沉积方法和结果得到的结构 |
US9991363B1 (en) * | 2017-07-24 | 2018-06-05 | Globalfoundries Inc. | Contact etch stop layer with sacrificial polysilicon layer |
US11145509B2 (en) * | 2019-05-24 | 2021-10-12 | Applied Materials, Inc. | Method for forming and patterning a layer and/or substrate |
US11594602B2 (en) * | 2020-04-16 | 2023-02-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Butted contacts and methods of fabricating the same in semiconductor devices |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5831305A (en) * | 1994-01-19 | 1998-11-03 | Hyundai Electronics Industries Co., Ltd. | CMOS devices having minimized drain contact area |
US6018180A (en) * | 1997-12-23 | 2000-01-25 | Advanced Micro Devices, Inc. | Transistor formation with LI overetch immunity |
US20040087043A1 (en) * | 2001-10-30 | 2004-05-06 | Asia Pacific Microsystems, Inc. | Package structure and method for making the same |
US20060216882A1 (en) * | 2004-09-11 | 2006-09-28 | Texas Instruments Incorporated | Using Oxynitride Spacer to Reduce Parasitic Capacitance in CMOS Devices |
US20110024890A1 (en) * | 2007-06-29 | 2011-02-03 | Stats Chippac, Ltd. | Stackable Package By Using Internal Stacking Modules |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3326644B2 (ja) * | 1993-11-16 | 2002-09-24 | ソニー株式会社 | シリコン系材料層の加工方法 |
US5721146A (en) * | 1996-04-29 | 1998-02-24 | Taiwan Semiconductor Manufacturing Company Ltd | Method of forming buried contact architecture within a trench |
US6180472B1 (en) * | 1998-07-28 | 2001-01-30 | Matsushita Electrons Corporation | Method for fabricating semiconductor device |
US6040222A (en) * | 1999-02-02 | 2000-03-21 | United Microelectronics Corp. | Method for fabricating an electrostatistic discharge protection device to protect an integrated circuit |
US6720213B1 (en) * | 2003-01-15 | 2004-04-13 | International Business Machines Corporation | Low-K gate spacers by fluorine implantation |
US7342289B2 (en) * | 2003-08-08 | 2008-03-11 | Taiwan Semiconductor Manufacturing Co., Ltd | Strained silicon MOS devices |
US8466502B2 (en) * | 2011-03-24 | 2013-06-18 | United Microelectronics Corp. | Metal-gate CMOS device |
US9136340B2 (en) * | 2013-06-05 | 2015-09-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Doped protection layer for contact formation |
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2013
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2014
- 2014-05-29 CN CN201410234656.XA patent/CN104241250B/zh not_active Expired - Fee Related
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2015
- 2015-09-02 US US14/843,720 patent/US9647087B2/en active Active
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2017
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Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5831305A (en) * | 1994-01-19 | 1998-11-03 | Hyundai Electronics Industries Co., Ltd. | CMOS devices having minimized drain contact area |
US6018180A (en) * | 1997-12-23 | 2000-01-25 | Advanced Micro Devices, Inc. | Transistor formation with LI overetch immunity |
US20040087043A1 (en) * | 2001-10-30 | 2004-05-06 | Asia Pacific Microsystems, Inc. | Package structure and method for making the same |
US20060216882A1 (en) * | 2004-09-11 | 2006-09-28 | Texas Instruments Incorporated | Using Oxynitride Spacer to Reduce Parasitic Capacitance in CMOS Devices |
US20110024890A1 (en) * | 2007-06-29 | 2011-02-03 | Stats Chippac, Ltd. | Stackable Package By Using Internal Stacking Modules |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106024888A (zh) * | 2015-03-25 | 2016-10-12 | 三星电子株式会社 | 包括面积增加的接触件的半导体器件 |
CN106024888B (zh) * | 2015-03-25 | 2021-03-26 | 三星电子株式会社 | 包括面积增加的接触件的半导体器件 |
Also Published As
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US20140361364A1 (en) | 2014-12-11 |
US20170236716A1 (en) | 2017-08-17 |
KR101656135B1 (ko) | 2016-09-08 |
CN104241250B (zh) | 2017-07-21 |
US20150380516A1 (en) | 2015-12-31 |
US9647087B2 (en) | 2017-05-09 |
US9991123B2 (en) | 2018-06-05 |
KR20140143106A (ko) | 2014-12-15 |
US9136340B2 (en) | 2015-09-15 |
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