WO2017111791A1 - Methods for obtaining ultra low defect density gan using cross point trench design - Google Patents

Methods for obtaining ultra low defect density gan using cross point trench design Download PDF

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Publication number
WO2017111791A1
WO2017111791A1 PCT/US2015/000304 US2015000304W WO2017111791A1 WO 2017111791 A1 WO2017111791 A1 WO 2017111791A1 US 2015000304 W US2015000304 W US 2015000304W WO 2017111791 A1 WO2017111791 A1 WO 2017111791A1
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WIPO (PCT)
Prior art keywords
layer
semiconductor
defect density
iii
trenches
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PCT/US2015/000304
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French (fr)
Inventor
Sansaptak DASGUPTA
Han Wui Then
Marko Radosavljevic
Sanaz K. GARNDER
Seung Hoon Sung
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Intel Corporation
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Priority to PCT/US2015/000304 priority Critical patent/WO2017111791A1/en
Priority to TW105138128A priority patent/TWI713632B/en
Publication of WO2017111791A1 publication Critical patent/WO2017111791A1/en

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Abstract

Embodiments of the invention include a semiconductor structure and a method of making such a structure. According to an embodiment, the structure may include a semiconductor substrate with a first shallow trench isolation (STI) layer formed over semiconductor substrate. A plurality of first trenches may be aligned in a row and formed through the first STI layer. In an embodiment, a first ΠΙ-nitride (III-N) layer may be formed in the first trenches and over a top surface of the first STI layer. Additionally, embodiments include a second STI layer formed over the first III-N layer and the top surface of the first STI layer. A second trench formed through the second STI layer may be oriented perpendicular to the row of first trenches. Embodiments include a second III-N layer that fills the second trench.

Description

METHODS FOR OBTAINING ULTRA LOW DEFECT DENSITY GAN USING CROSS
POINT TRENCH DESIGN
FIELD OF THE INVENTION
Embodiments of the invention are in the field of semiconductor devices and processing and, in particular, formation of low defect density Gallium Nitride formed on a silicon wafer for co-integration of GaN transistors with Si CMOS devices, and methods of forming such devices.
BACKGROUND OF THE INVENTION III-N material based transistors are useful for high voltage and high frequency applications. Accordingly, III-N material based transistors are promising candidates for system- on-chip (SoC) applications, like power management integrated circuits PMICs and radio frequency (RF) power amplifiers. BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1A is a cross-sectional illustration of a first GaN layer epitaxially grown to a thickness that is not above a top surface of a trench formed in a first STI layer, according to an embodiment of the invention.
Figure IB is a cross-sectional illustration of a first GaN layer epitaxially grown over a trench pattern formed on a semiconductor substrate, according to an embodiment of the invention.
Figure 1C is a cross-sectional illustration of a second GaN layer epitaxially grown over a first epitaxially grown GaN layer, according to an embodiment of the invention.
Figure 2A is a perspective illustration of a trench pattern formed in a first shallow trench isolation (STI) layer formed over a semiconductor substrate, according to an embodiment of the invention.
Figure 2B is a perspective illustration of a first GaN layer epitaxially grown in the trenches and over the first STI layer, according to an embodiment of the invention.
Figure 2C is a perspective illustration of a first GaN layer epitaxially grown in the trenches and over the first STI layer, according to an additional embodiment of the invention.
Figure 2D is a perspective illustration of a trench pattern in a second STI layer that is oriented perpendicular to the trench pattern in the first STI layer, according to an embodiment of the invention.
Figure 2E is a perspective illustration of a second GaN layer epitaxially grown in the trench and over the second STI layer, according to an embodiment of the invention. Figure 2F is a perspective illustration of a second GaN layer epitaxially grown in the trench and over a conductive layer, according to an embodiment of the invention.
Figure 3 is a perspective illustration a semiconductor substrate that includes a first device formed in a first GaN layer and a second device formed in a second GaN layer, according to an embodiment of the invention.
Figure 4 is a perspective illustration of a semiconductor substrate that includes a non- planar GaN transistor device, according to an embodiment of the invention.
Figure 5 is a perspective illustration of a semiconductor substrate that includes a suspended GaN layer, according to an embodiment of the invention.
Figure 6 is a plan view illustration of a substrate that includes a first silicon portion and a ΙΠ-Ν layer formed over a second portion of the substrate, according to an embodiment of the invention.
Figure 7 is a cross-sectional illustration of an interposer implementing one or more embodiments of the invention.
Figure 8 is a schematic of a computing device that includes one or more transistors built in accordance with an embodiment of the invention.
DETAILED DESCRIPTION OF THE INVENTION
Described herein are systems that include a semiconductor device and methods for forming the semiconductor device. In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present invention may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and
configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present invention may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.
Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present invention, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.
While ΠΙ-Ν material based transistors are promising candidates for SoC applications, co- integration of ΙΠ-Ν material based transistors on a silicon substrate provides significant challenges. One challenge is the large lattice mismatch between the materials. For example, the lattice mismatch between gallium nitride (GaN) and (100) oriented silicon (Si) is approximately 41%. Such a large lattice mismatch produces a high defect density in GaN that is epitaxially grown on a layer of Si. Additionally, the mismatch in thermal expansion coefficient between Si and GaN may result in surface cracks on GaN that is epitaxially grown on Si. For example, the thermal expansion coefficient difference between the two materials may be approximately 116%.
Lattice mismatch may be accommodated by using buffer layers to more gradually change the lattice spacing from a lattice spacing of a first semiconductor material to a lattice spacing of the second semiconductor material. Additionally, lattice defects may be reduced by using aspect ratio trapping. Aspect ratio trapping can take advantage of the propagation of dislocations (e.g., threading dislocations) along slip planes. When the defect reaches the sidewall of the aspect ratio trapping trench, the defect may be prevented from extending further. As such, a material with a lower defect density can be formed at the top of the aspect ratio trapping trench. However, this mechanism may not be as effective when GaN is epitaxially grown due to the orientation of the slip planes. In GaN, the defects may propagate along a slip plane that is substantially vertical. As such, the defects may never run into the sidewalls of the trench.
Accordingly, aspect ratio trapping by itself may not significantly reduce the defect density of GaN.
In the GaN system the threading dislocations, arise due to lattice mismatch. The lattice mismatch is particularly prominent in GaN layers epitaxially grown on a silicon substrate. As noted above, the lattice mismatch between GaN and (100) oriented Si is approximately 41%. Accordingly, an epitaxially grown GaN layer will generally have a high defect density. The high defect density produces traps and bulk traps that prevent a GaN based transistor from being operated at peak theoretical efficiency. Accordingly, while GaN transistors are theoretically ideal for high voltage applications (e.g., PMICs and RF applications), in practice, the high voltage benefits of GaN are not as great as predicted.
Accordingly, embodiments of the invention utilize the propagation direction of threading dislocations to form low defect density GaN layers. In GaN, the threading dislocations can propagate along two different planes. The first plane that can propagate threading dislocations is (11 00). In embodiments of the application, this plane is oriented so that the dislocations propagate in the vertical direction (i.e., parallel to the growth direction). The second plane that can propagate threading dislocations is the (0001) plane. In embodiments of the application, this plane is oriented so that the dislocations propagate in the horizontal direction (i.e., perpendicular to the growth direction). In epitaxially grown GaN layers, the orientation of the trench and the process conditions for epitaxial growth are used to determine which defect propagation scheme occurs. Figures 1 A- 1C shown how embodiments of the invention may utilize a cross point trench design to minimize or eliminate the defects in the second GaN layer. While GaN layers are described in detail herein, it is to be appreciated that the processes for reducing the defect density in the GaN layers are equally applicable to many different semiconductor materials. For example, embodiments of the invention may replace a GaN layer with any Ill-nitride (ΠΙ-Ν) layer.
Referring now to Figure 1A, a cross-sectional illustration of a semiconductor substrate 100 is shown according to an embodiment of the invention. A first STI layer 115 may be formed over a top surface of the semiconductor substrate 100. In an embodiment, a plurality of trenches 120 may be formed through the first STI layer 115. The trenches 120 may be high aspect ratio trenches that are suitable for aspect ratio trapping processes. A GaN material 141 may then be epitaxially grown over the portions of the semiconductor substrate 100 that are exposed along the bottom of the trenches 120. According to an embodiment, a nucleation layer (not shown) may be formed between the GaN material 141 and the semiconductor substrate 101. For example, a nucleation layer may include an A1N, AlGaN, InN, AlInN, or the like. In some embodiments the nucleation layer may be formed only in the trenches 120, or the nucleation layer may be conformally deposited over the STI layer 115 and the silicon substrate 100.
According to an embodiment, the overall thickness of the nucleation layer is less than the thickness of the STI layer 115. For example, the nucleation layer may have a thickness between approximately 15 nm and 200 nm.
As noted above, when the GaN is epitaxially grown over a silicon substrate 100, there may be a significant lattice mismatch between the two layers. As such, there may be a high density of dislocation defects 142 formed in the epitaxially grown GaN 141. Furthermore, aspect ratio trapping alone may not be provide a significant improvement in the dislocation density because the dislocation defects 142 propagate in a slip plane that is parallel to the growth direction and the walls of the trench 120.
Referring now to Figure IB, a cross-sectional illustration of the substrate 100 after further growth of a first GaN layer 140 is shown according to an embodiment of the invention.
According to an embodiment, the GaN layer 140 may extended above the top surface of the first STI layer 115. Once the GaN layer 140 extends above the first STI layer 115, it is no longer constrained by the trenches 140 and begins growing laterally in addition to vertically.
Accordingly, the GaN layer 140 may merge together to form a single continuous layer. As illustrated, the dislocation defects 142 continue to extend in the vertical direction. However, since the dislocation defects 142 only propagate in the vertical direction (i.e., along the (11 00) plane), the lateral growth is formed without defects. Therefore, the first GaN layer 140 may include low defect density portions 143 formed in the lateral growth above the top surface of the first STI layer 115 and a high defect density portion 141 formed in and above the trenches 120 of the first STI layer 115.
Referring now to Figure 1C, a cross-sectional illustration of substrate 100 after a second layer of GaN 145 is formed is shown according to an embodiment of the invention. In an embodiment, the second layer of GaN 145 may be formed by using the low defect density portion 143 as a seed layer to selectively allow growth over the low defect density portion 143 in the vertical direction. In an embodiment, the low defect density portion 143 is selectively allowed to grow by forming a second STI layer 125 that includes one or more trenches 127 that are positioned over the top surface of the first STI layer 115 and oriented perpendicularly (i.e., out of the plane of the illustration). Accordingly, the dislocation defects 142 in the high defect density portion 141 of the first GaN layer 140 are blocked by the bottom surface of the second STI layer 125 and the low defect density portions 143 of the first GaN layer 140 are allowed to extend through the trench 127 formed in the second STI layer 125. The second GaN layer 145 may then begin extending laterally along a top surface of the second STI layer 125 after the GaN extends above the trench 127 to form a planar region of low defect density GaN. Accordingly, the entire second GaN layer 145 may have a low defect density.
According to an embodiment, the low defect density of the second GaN layer 145 is suitable for use in applications that require high performance high voltage GaN transistors (e.g., PMICs or RF applications). Additionally, it is to be appreciated that the first GaN layer 140 is not an unused byproduct of the processing operations. For example, the first GaN layer 140 may also be used for components that do not rely on a low defect density (e.g., capacitors, Schottky diodes, RF filters, or the like). Furthermore, it is to be appreciated that the low defect density GaN layer 140 may be grown over any sized substrate (e.g., 100 mm, 150 mm, 200 mm, 300 mm, 450 mm, etc.) As such, embodiments of the invention allow low defect density GaN for high volume manufacturing (HVM).
Referring now to Figures 2A-2F, a process for forming a low defect density GaN layer is illustrated in a perspective view to more fully explain aspects of the invention.
Referring now to Figure 2A, a perspective view of a device that includes a semiconductor substrate 200 and a first STI layer 215 is shown according to an embodiment of the invention. According to an embodiment, the device may be formed on any suitable crystalline
semiconductor substrate 200. In a particular embodiment, the semiconductor substrate is a bulk silicon or a silicon-on-insulator substrate 200 that is has a { 111 } orientation. In other
embodiments, the semiconductor substrate 200 may be formed using alternate materials that have a lattice mismatch with the GaN layer grown in a subsequent processing operation, which may or may not be combined with silicon. According to an embodiment, the additional materials may include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, SiC, sapphire, or other combinations of group III-V or group IV materials. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the present invention.
According to an embodiment, the first STI layer 215 may be any suitable dielectric material. For example, the first STI layer 215 may be an oxide. Embodiments of the invention may include a plurality of trenches 220 formed through the first STI layer. In an embodiment, the trenches 220 may be oriented in trench rows 221 that are aligned in a predetermined direction (as indicated by arrow 280) based on the orientation of the underlying semiconductor substrate 200. For example, the trench rows 221 may be oriented along a direction 280 that is the <110> direction when the underlying semiconductor substrate 200 is a silicon substrate with a { 111 } orientation. According to an embodiment of the invention, the trenches 220 may be any suitable size for forming high aspect ratio trenches. In one embodiment, the trenches may be rectangular or square in shape, but embodiments are not limited to such configurations. For example, the trenches may have dimensions between approximately 50 - 300 nm x 50 - 300 nm.
In an embodiment, the spacing between the trenches 220 may be chosen in order to provide controlled growth of the subsequently formed GaN layer. For example, the spacing S i between trenches 220 in the same row 221 may be smaller than the spacing S2 between trenches 220 in different rows 221. Providing a smaller spacing Si allows for the subsequently formed GaN layer to merge together along each of the rows 221 without allowing the rows 221 to merge together. For example, S2 may be approximately one and a half times greater than Si.
Referring now to Figure 2B, a perspective view of the device after the first GaN layer 240 is epitaxially grown is shown according to an embodiment of the invention. In an embodiment, the GaN may be grown with any suitable epitaxial deposition process, such as metal organic chemical vapor phase deposition (MOCVD)or molecular beam epitaxy (MBE). Additionally, growing the first GaN layer 240 in the trenches reduces the fill factor of the first GaN layer. For example, the GaN may only be grown over approximately 10% or less of the surface area. As such, the growth rate may be increased, which reduces the process times. Accordingly, embodiments of the invention are suitable for high volume manufacturing (HVM).
In an embodiment, the first GaN layer 240 may be grown using the exposed portions of the semiconductor substrate 200 as the seed layer. Additional embodiments may include forming one or more buffer layers (not shown) over the exposed portions of the semiconductor substrate 200 prior to growing the GaN layer. For example, an A1N layer may be formed over the semiconductor substrate 200 prior to growing the first GaN layer 240.
As illustrated, the first GaN layer 240 may grow above the trenches 220 and begin spreading in the lateral direction once the growth is no longer confined. The lateral growth of the first GaN layer 240 allows for the GaN to merge to form strips of GaN above the first STI layer 215. In addition to controlling the spacing Si and S2 in order to prevent the first GaN layer 240 from merging between rows, the processing conditions of the epitaxial growth may be modified so that growth in the direction of the rows proceeds faster than the direction between the rows. For example, higher temperatures and lower pressures during the epitaxial growth will result in the rate of lateral growth along the direction of the rows being faster than the rate of lateral growth along the direction between the rows.
Similar to the cross-sectional view illustrated and described above in Figure IB, the dislocations in the first GaN layer 240 are isolated to the regions within and directly above the trenches 220 since the threading dislocations only propagate in the vertical direction.
Accordingly, the first GaN layer 240 may include low defect density regions 243 and high defect density regions 241. In Figure 2B, the high defect density regions 241 are located within the dashed lines that indicate where the trenches 220 are formed below the first GaN layer 240.
In Figure 2B, the strips of the first GaN layer 240 have vertical sidewalls (i.e., the (101 0) plane also referred to as the m-plane). However, embodiments of the invention are not limited to such configurations. For example, Figure 2C illustrates a substantially similar first GaN layer 240 that includes triangular facets (i.e., the (101 2) plane). However, it is to be appreciated that the top surface of the first GaN layer 240 in either embodiment is the c-plane (i.e., the (0001) plane) which is the preferred orientation for transistor fabrication and other devices. The formation of (101 2) facets in the first GaN layer 240 may be produced when higher pressures are used during the epitaxial growth process.
Referring now to Figure 2D, a perspective view of a single strip after the second STI layer
225 is formed is shown according to an embodiment of the invention. In the illustrated embodiment, the second STI layer 225 is a dielectric material. For example, the second STI layer 225 may be the same material as the first STI layer 215. According to an additional embodiment, the second STI layer 225 may be replaced with a conductive layer. Such an embodiment allows for different transistor types to be formed, and will be described in greater detail below.
According to an embodiment, the second STI layer 215 may be patterned to form a second plurality of trenches 227. The second trenches 227 may be oriented in a second direction 281 that is perpendicular to the direction 280 of the strips of GaN in the first GaN layer 240. For example, the second trenches 227 may be oriented in the <112 > direction when the semiconductor substrate 200 is a { 111 } silicon substrate. Additionally, embodiments of the invention include aligning the second trenches 227 so that the trench 227 does not expose high defect density portions 241 of the first GaN layer 240. To aid in the understanding of the location of the second trenches 227, the position of the first trenches 220 are illustrated as dashed lines over the second STI layer 225. Accordingly, the only exposed portions of the first GaN layer 240 are low defect density regions 243.
Referring now to Figure 2E, a perspective view of the device after the second GaN layer 245 is grown is shown according to an embodiment of the invention. According to an
embodiment, the second GaN layer 245 may be grown with any suitable epitaxial growth process, such as MOCVD or MBE. Similar to the growth process of the first GaN layer 240, growing the second GaN layer 245 in the second trenches 227 reduces the fill factor of the second GaN layer 245. As such, the growth rate may be increased, which reduces the process times and allows for high volume manufacturing.
The second layer of GaN 245 may be formed by using the low defect density portion 243 as a seed layer to selectively allow growth over the low defect density portion 243 in the vertical direction. In an embodiment, only the low defect density portion 243 is allowed to grow because the second STI layer 225 covers the top surface the high defect density portions 241 of the first GaN layer 240. Accordingly, the dislocation defects present in the high defect density portion 241 of the first GaN layer 240 are blocked by the bottom surface of the second STI layer 225. After extending above the second trench 227, the second GaN layer 245 may begin extending laterally along a top surface of the second STI layer 225 to form a planar region of low defect density GaN. Accordingly, the entire second GaN layer 245 may have a low defect density.
As noted above, some embodiments of the invention may include replacing the second STI layer 245 with a conductive layer 247. Such an embodiment is illustrated in the perspective view shown in Figure 2F. In one embodiment, the conductive layer 247 may be deposited and patterned at the same point in the process flow that the second STI layer 225 was deposited and patterned as described above. Alternatively, the second STI layer 225 may be formed, as described above, and then removed with an etching process after the second GaN layer is formed. The conductive layer 247 may then be back filled around the second GaN layer 245. Further embodiments may include forming a dielectric layer (not shown) between conductive layer 247 and the first and second GaN layers 240, 245. Such embodiments may be beneficial when the conductive layer is used as a gate electrode for a non-planar transistor, as will be described in greater detail below.
It is to be appreciated that the processing flow above includes the formation of two different GaN layers. The first GaN layer 240 includes both high defect density regions 241 and low defect density regions 243, whereas the second GaN layer 245 is entirely formed with a low defect density material. As such, the second GaN layer 245 is suitable for applications that require high performance high voltage GaN transistors (e.g., PMICs or RF applications).
However, this does not preclude using the first GaN layer 240 for other applications that do not require such high performance characteristics. As such, embodiments of the invention may increase the utilization of the surface are of the device by fabricating components on both layers. A Device according to such an embodiment is illustrated and described with respect to Figure 3.
Referring now to Figure 3, a perspective view of a device that includes components formed on a first GaN layer 340 and a second GaN layer 345 are shown according to an embodiment of the invention. As explained above, the second GaN layer 345 will be the layer that has the lowest defect density and hence, fewer traps and bulk trap states. This can be utilized to form high performance high voltage GaN devices for PMIC and RF applications. For example, a metal-oxide-semiconductor field-effect transistor (MOSFET) 360 may be formed on the second GaN layer 345. In an embodiment, the GaN MOSFET 360 may include a source contact 362, a drain contact 364, and a gate electrode 366 formed over the top surface of the second GaN layer 345. While not shown, it is to be appreciated that a gate dielectric layer may be formed between the gate electrode 366 and the surface of the second GaN layer 345.
Additionally, the second GaN layer 345 may include dopants in the source and drain regions below the source and drain contacts 362/264 and/or below the gate electrodef 366 in order to provide the desired electrical properties to the GaN MOSFET 360. For example, the dopants may be in-situ doped during the epitaxial growth of the second GaN layer 345 and/or the dopants may be implanted (e.g., ion implantation and/or diffusion) after the second GaN layer 345 is formed.
Additionally, a second component with lesser defect density requirements may be fabricated on the first GaN layer 340. For example, a GaN metal-oxide-semiconductor (MOS) capacitor 370 may be formed on the first GaN layer 340. In the illustrated embodiment, the MOS capacitor 370 may include an ohmic contact 372, a high-k dielectric 374, and a gate electrode 376 formed over the first GaN layer 340. The inclusion of a MOS capacitor 370 with a high voltage MOSFET may be especially beneficial when the device includes PMIC or RF power amplification (PA) circuits.
Additional embodiments may include any combination of components formed on the first and second GaN layers 340/345. For example, the second GaN layer 345 may be used for components needed in RF PA and the first GaN layer 340 may be used for GaN RF switch devices. Locating an RF switch on the first GaN layer 340 may be beneficial because RF switches need to be well isolated. Since the first GaN layer 340 is formed over the first STI layer 315 there would already be sufficient isolation for these types of components.
In addition to forming planar MOSFET devices, embodiments of the invention may utilize the dual GaN layer structure to form non-planar MOSFET devices as well. A device according to such an embodiment is illustrated and described with respect to Figure 4.
Referring now to Figure 4, a perspective view of a device is shown where the second GaN layer 445 is used to form a non-planar MOSFET. Such embodiments may be fabricated when the second STI layer is replaced with a conductive layer 447, similar to the structure described above with respect to Figure 2F. As illustrated, the conductive layer 447 may function as a gate electrode and provide a double gate or a gate-all-around (GAA) MOSFET device 460. In addition to forming the conductive layer 447 (which may be separated from the second GaN layer 445 by a gate dielectric that is not shown), the non-planar MOSFET device 460 may include source contacts 462 and a drain contact 464. The location of the source contacts 462 and the drain contacts 464 define a pair of channels 468. For example, the channels may be nano- ribbon or nano-wire channels depending on the dimensions of the second GaN layer 445. A second conductive layer 448 (shown as just a surface in order to not obscure the Figure) may be formed over the top surface of the second GaN layer 445 in order function as part of the gate electrode of the non-planar MOSFET 460. Those skilled in the art will recognize that this configuration allows for the formation of nano-ribbon or nano-wire structures that do not require the use of wet etch or any etch of GaN. This is particularly beneficial due to the difficulty of developing etchant chemistries suitable for etching GaN systems.
In addition to active and passive electrical components, embodiments of the invention may utilize the cross-point structure formed by the first and second GaN layers to form mechanical devices as well. For example, mechanical devices may be used to form sensors for RF filter applications, or the like. In one embodiment, the cross-point structure enables the formation of a cantilever beam that may be used in RF filtering applications. A device according to such an embodiment is illustrated and described with respect to Figure 5.
Referring now to Figure 5, a perspective view of a device that includes a cantilever beam 530 is shown according to an embodiment of the invention. In an embodiment the cantilever beam 530 may be formed from the second GaN layer 545 by wet etching off the second STI layer. A conductive layer 547 may then be back filled around a portion of the device. According to an embodiment, the resonant frequency of the cantilever beam 530 may be controlled by adjusting the thickness of the second GaN layer 545 and/or adjusting the length L of the cantilever beam 530.
Referring now to Figure 6, a plan view of a substrate 600 that may be formed in accordance with an embodiment of the invention is show. According to an embodiment, the substrate 600 may be any suitable crystalline semiconductor substrate 600. In a particular embodiment, the semiconductor substrate is a bulk silicon or a silicon-on-insulator substrate 600. In an embodiment, a plurality of dice 682 may be formed over the substrate 600. On one or more of the dice 682, there may be a first portion 684 that is silicon and a second portion that includes a ΠΙ-Ν layer formed over the substrate 600. In an embodiment, the ΠΙ-Ν portion of the die 682 may be formed with an epitaxial growth process that includes a cross-point trench design, such as those described above.
The integration of a silicon portion and a ΙΠ-Ν portion on the same die allows for improved performance of SoC devices. For example, each die 682 may include integrated circuitry such as, logic, memory, power management, and the like. As described above, the ΠΙ-Ν based transistors are useful for high voltage and high frequency applications, such as power management. Accordingly, embodiments of the invention include forming one or more ΓΠ-Ν type transistors on the III-N region 686 and one or more logic CMOS may be included on the silicon portion 684.
Figure 7 illustrates an interposer 700 that includes one or more embodiments of the invention. The interposer 700 is an intervening substrate used to bridge a first substrate 702 to a second substrate 704. The first substrate 702 may be, for instance, an integrated circuit die. The second substrate 704 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer 700 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer 700 may couple an integrated circuit die to a ball grid array (BGA) 706 that can subsequently be coupled to the second substrate 704. In some embodiments, the first and second substrates 702/704 are attached to opposing sides of the interposer 700. In other embodiments, the first and second substrates 702/704 are attached to the same side of the interposer 700. And in further embodiments, three or more substrates are interconnected by way of the interposer 700. The interposer 700 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.
The interposer may include metal interconnects 708 and vias 710, including but not limited to through-silicon vias (TSVs) 712. The interposer 700 may further include embedded devices 714, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 700.
In accordance with embodiments of the invention, apparatuses that include one or more dual layer GaN structures formed in a cross-point configuration, or processes for forming such transistors disclosed herein may be used in the fabrication of interposer 700.
Figure 8 illustrates a computing device 800 in accordance with one embodiment of the invention. The computing device 800 may include a number of components. In one embodiment, these components are attached to one or more motherboards. In an alternate embodiment, these components are fabricated onto a single system-on-a-chip (SoC) die rather than a motherboard. The components in the computing device 800 include, but are not limited to, an integrated circuit die 802 and at least one communication chip 808. In some implementations the communication chip 808 is fabricated as part of the integrated circuit die 802. The integrated circuit die 802 may include a CPU 804 as well as on-die memory 806, often used as cache memory, that can be provided by technologies such as embedded DRAM (eDRAM) or spin-transfer torque memory (STTM or STTM-RAM).
Computing device 800 may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within an SoC die. These other components include, but are not limited to, volatile memory 810 (e.g., DRAM), non- volatile memory 812 (e.g., ROM or flash memory), a graphics processing unit 814 (GPU), a digital signal processor 816, a crypto processor 842 (a specialized processor that executes cryptographic algorithms within hardware), a chipset 820, an antenna 822, a display or a touchscreen display 824, a touchscreen controller 826, a battery 828 or other power source, a power amplifier (not shown), a global positioning system (GPS) device 844, a compass 830, a motion coprocessor or sensors 832 (that may include an accelerometer, a gyroscope, and a compass), a speaker 834, a camera 836, user input devices 838 (such as a keyboard, mouse, stylus, and touchpad), and a mass storage device 840 (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
The communications chip 808 enables wireless communications for the transfer of data to and from the computing device 800. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 808 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (ΓΕΕΕ 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 800 may include a plurality of communication chips 808. For instance, a first communication chip 808 may be dedicated to shorter range wireless
communications such as Wi-Fi and Bluetooth and a second communication chip 808 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
The processor 804 of the computing device 800 includes one or more devices, such as dual layer GaN structures formed in a cross-point configuration, according to an embodiment of the invention. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
The communication chip 808 may also include one or more devices, such as one or more dual layer GaN structures formed in a cross-point configuration, according to an embodiment of the invention.
In further embodiments, another component housed within the computing device 800 may contain one or more devices, such as one or more dual layer GaN structures formed in a cross-point configuration, according to an embodiment of the invention.
In various embodiments, the computing device 800 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 800 may be any other electronic device that processes data.
The above description of illustrated implementations of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific implementations of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.
These modifications may be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific implementations disclosed in the specification and the claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.
Embodiment of the invention include a semiconductor structure comprising: a semiconductor substrate having a first lattice constant; a first shallow trench isolation (STI) layer formed over semiconductor substrate, wherein a plurality of first trenches aligned in a row are formed through the first STI layer; a first Ill-nitride (ΓΠ-Ν) layer having a second lattice constant formed in the first trenches and over a top surface of the first STI layer, wherein the first ΙΠ-Ν layer spans between the first trenches; a second STI layer formed over the first ΙΠ-Ν layer and the top surface of the first STI layer, wherein a second trench is formed through the second STI layer, and wherein the second trench is oriented perpendicular to the row of first trenches; and a second ffl-N layer filling the second trench.
Additional embodiments of the invention include a semiconductor structure, wherein the first lattice constant and the second lattice are different.
Additional embodiments of the invention include a semiconductor structure, wherein the first III-N layer includes a high defect density portion located in and directly above each of the first trenches and a low defect density portion formed over the top surface of the first STI layer.
Additional embodiments of the invention include a semiconductor structure, wherein the second III-N layer is formed in contact with the low-defect density portion.
Additional embodiments of the invention include a semiconductor structure, wherein the semiconductor substrate is a { 111 } oriented silicon substrate and the first ΠΙ-Ν layer is GaN.
Additional embodiments of the invention include a semiconductor structure, wherein the row of first trenches are aligned in the <110> direction.
Additional embodiments of the invention include a semiconductor structure, wherein the a top surface of the first ΠΙ-Ν layer is the (0001) plane and facets of the first ΠΙ-Ν layer are the (101 0) plane or the (101 2) plane. Additional embodiments of the invention include a semiconductor structure, wherein the second trench is aligned in the <112 > direction.
Additional embodiments of the invention include a semiconductor structure, wherein a transistor is formed on the second ΠΙ-Ν layer.
Additional embodiments of the invention include a semiconductor structure, wherein the transistor is a non-planar transistor.
Additional embodiments of the invention include a semiconductor structure, wherein a component is formed on the first III-N layer.
Additional embodiments of the invention include a semiconductor structure, wherein the component is a metal-oxide-semiconductor capacitor.
Additional embodiments of the invention include a semiconductor structure, wherein the second III-N layer is a cantilever beam.
Embodiments of the invention include a method of forming a low defect density semiconductor device, comprising: forming a first STI layer over a semiconductor substrate, wherein the first STI layer includes a plurality of first trenches aligned in a row; growing a first ΙΠ-Ν layer in the first trenches, wherein the first III-N layer extends laterally over a top surface of the first STI layer, and wherein the first III-N layer spans between the first trenches; forming a second STI layer over the first STI layer and the first ΠΙ-Ν layer, wherein a trench is formed through the second STI layer and is oriented perpendicular to the row of first trenches, and wherein the second trench is not formed directly above a first trench; and growing a second ΠΙ-Ν layer in the second trench.
Additional embodiments of the invention include a method of forming a low defect density semiconductor device, wherein first and second ΠΙ-Ν layers are epitaxially grown with a MOCVD or MBE process.
Additional embodiments of the invention include a method of forming a low defect density semiconductor device, wherein dislocations in the first ΠΙ-Ν layer terminate at the bottom surface of the second STI layer, and wherein the first III-N layer includes low defect density regions formed over the surface of the first STI layer and high defect density regions formed in and directly above the first plurality of trenches.
Additional embodiments of the invention include a method of forming a low defect density semiconductor device, wherein growing the second ΙΠ-Ν layer includes selectively growing the layer above only the low defect density regions of the first III-N layer.
Additional embodiments of the invention include a method of forming a low defect density semiconductor device, further comprising: removing the second STI layer. Additional embodiments of the invention include a method of forming a low defect density semiconductor device, further comprising: depositing a conductive layer around the second ΙΠ-Ν layer; and forming a non-planar transistor on the second III-N layer.
Additional embodiments of the invention include a method of forming a low defect density semiconductor device, wherein a portion of the second ΠΙ-Ν layer extends unsupported from below to form a cantilever beam.
Additional embodiments of the invention include a method of forming a low defect density semiconductor device, wherein the first and second III-N layers are GaN.
Embodiments of the invention include a semiconductor structure comprising: a semiconductor substrate having a first lattice constant; a first shallow trench isolation (STI) layer formed over semiconductor substrate, wherein a plurality of first trenches aligned in a row are formed through the first STI layer; a first GaN layer having a second lattice constant that is different than the first lattice constant formed in the first trenches and over a top surface of the first STI layer, wherein the first GaN layer spans between the first trenches, and wherein the first GaN includes a high defect density portion located in and directly above each of the first trenches and a low defect density portion formed over the top surface of the first STI layer; a second STI layer formed over the first GaN layer and the top surface of the first STI layer, wherein a second trench is formed through the second STI layer, and wherein the second trench is oriented perpendicular to the row of first trenches; and a second GaN layer filling the second trench, wherein the second III-N layer is formed in contact with the low-defect density portion.
Additional embodiments of the invention include a semiconductor structure, wherein the semiconductor substrate is a { 111 } oriented silicon substrate, wherein the row of first trenches are aligned in the <110> direction, and wherein the second trench is aligned in the <112 > direction.
Additional embodiments of the invention include a semiconductor structure, wherein a first component is formed on the first GaN layer and a second component is formed on the second GaN layer.
Additional embodiments of the invention include a semiconductor structure, wherein the second GaN layer is a cantilever beam.

Claims

CLAIMS What is claimed is:
1. A semiconductor structure comprising:
a semiconductor substrate having a first lattice constant;
a first shallow trench isolation (STI) layer formed over at least a portion of the semiconductor substrate, wherein a plurality of first trenches aligned in a row are formed through the first STI layer;
a first Ill-nitride (III-N) layer having a second lattice constant formed in the first trenches and over at least a portion of a top surface of the first STI layer, wherein the first III-N layer spans between the first trenches;
a second STI layer formed over the first ΙΠ-Ν layer and the top surface of the first STI layer, wherein a plurality of second trenches are formed through the second STI layer, and wherein the second trenches are oriented perpendicular to the row of first trenches; and
a second III-N layer filling the second trench.
2. The semiconductor structure of claim 1 , wherein the first lattice constant and the second lattice are different.
3. The semiconductor structure of claim 2, wherein the first ΠΙ-Ν layer includes a high defect density portion located in and directly above each of the first trenches and a low defect density portion formed over the top surface of the first STI layer.
4. The semiconductor structure of claim 3, wherein the second ΠΙ-Ν layer is formed in contact with the low-defect density portion.
5. The semiconductor structure of claim 2, wherein the semiconductor substrate is a { 111 } oriented silicon substrate and the first III-N layer is GaN.
6. The semiconductor structure of claim 2, wherein the row of first trenches are aligned in the <110> direction.
7. The semiconductor structure of claim 6, wherein the a top surface of the first ΠΙ-Ν layer is the (0001) plane and facets of the first ΠΙ-Ν layer are the (101 0) plane or the (101 2) plane.
8. The semiconductor structure of claim 6, wherein the second trench is aligned in the <112 > direction.
9. The semiconductor structure of claim 1, wherein a transistor is formed on the second III- N layer.
10. The semiconductor structure of claim 9, wherein the transistor is a non-planar transistor.
11. The semiconductor structure of claim 9, wherein a component is formed on the first ΙΠ-Ν layer.
12. The semiconductor structure of claim 11, wherein the component is a metal-oxide- semiconductor capacitor.
13. The semiconductor structure of claim 1, wherein the second ΙΠ-Ν layer is a cantilever beam.
14. A method of forming a low defect density semiconductor device, comprising:
forming a first structural layer over at least a portion of a semiconductor substrate, wherein the semiconductor substrate is a first semiconductor material;
patterning a first trench into the first structural layer to expose a surface of the first semiconductor material;
epitaxially growing a first layer of a second semiconductor material through the first trench, wherein the second semiconductor material grows laterally along a top surface of the first structural layer after the trench is filled with the second semiconductor material;
forming a second structural layer over at least a portion of the first structural layer and the second semiconductor material;
patterning a second trench into the second structural layer, wherein the second trench exposes lateral growth of the second semiconductor material formed over the first structural layer; and
growing a second layer of the second semiconductor material through the second trench.
15. The method of claim 14, wherein the second semiconductor material is a III-N semiconductor, and wherein the layers are epitaxially grown with a MOCVD or MBE process.
16. The method of claim 14, wherein dislocations in the first semiconductor layer terminate at the bottom surface of the second structural layer, and wherein the first layer of the second semiconductor material includes low defect density regions formed over the surface of the first structural layer and high defect density regions formed in and directly above the first trench.
17. The method of claim 16, wherein growing the second layer of the second semiconductor includes selectively growing the layer above only the low defect density regions of the first layer of the second semiconductor.
18. The method of claim 14, further comprising: removing the second structural layer;
depositing a conductive layer around the second III-N layer; and
forming a non-planar transistor on the second ΠΙ-Ν layer.
19. A semiconductor device comprising:
a silicon substrate;
a first portion of the silicon substrate that includes a plurality of logic CMOS;
a ΠΙ-Ν region formed over at least a portion of the silicon substrate, wherein the III-N region comprises:
a first structural layer formed over at least a portion of the top surface of the silicon substrate;
a first III-N layer formed through and over a portion of the first structural layer; a second structural layer formed over the first ΙΠ-Ν layer; and
a second III-N layer formed through the first structural layer and in contact with the first III-N layer.
20. The semiconductor device of claim 19, wherein the first structural material is a dielectric layer, and wherein the second structural material is a conductive material.
21. The semiconductor device of claim 20, wherein the second structural material is a gate electrode for a non-planar transistor formed on the second III-N layer.
22. The method of claim 19, wherein a first component is formed on the first III-N layer, and a second component is formed on the second ΙΠ-Ν layer.
23. The semiconductor structure of claim 22, wherein the first component is a passive component and the second component is an active component.
The semiconductor structure of claim 22, wherein the second component is a cantilever
25. The semiconductor structure of claim 19, wherein the first ΙΠ-Ν layer includes a high defect density portion and a low defect density portion, and wherein the second ΠΙ-Ν layer is formed in contact with the low-defect density portion of the first III-N layer.
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