TW201732942A - Methods for obtaining ultra low defect density GaN using cross point trench design - Google Patents

Methods for obtaining ultra low defect density GaN using cross point trench design Download PDF

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TW201732942A
TW201732942A TW105138128A TW105138128A TW201732942A TW 201732942 A TW201732942 A TW 201732942A TW 105138128 A TW105138128 A TW 105138128A TW 105138128 A TW105138128 A TW 105138128A TW 201732942 A TW201732942 A TW 201732942A
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layer
nitride layer
trench
sti
gallium nitride
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TW105138128A
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TWI713632B (en
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山薩塔克 達斯古塔
漢威 陳
馬可 拉多撒福傑維克
薩納斯 珈納
成承訓
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英特爾股份有限公司
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Abstract

Embodiments of the invention include a semiconductor structure and a method of making such a structure. According to an embodiment, the structure may include a semiconductor substrate with a first shallow trench isolation (STI) layer formed over semiconductor substrate. A plurality of first trenches may be aligned in a row and formed through the first STI layer. In an embodiment, a first III-nitride (III-N) layer may be formed in the first trenches and over a top surface of the first STI layer. Additionally, embodiments include a second STI layer formed over the first III-N layer and the top surface of the first STI layer. A second trench formed through the second STI layer may be oriented perpendicular to the row of first trenches. Embodiments include a second III-N layer that fills the second trench.

Description

使用交叉點溝槽設計獲得超低缺陷密度氮化鎵(GaN)的方法 Method for obtaining ultra-low defect density gallium nitride (GaN) using cross-point trench design

本發明之實施例是在半導體裝置及處理之領域，且尤係在矽晶圓上形成低缺陷密度氮化鎵用於氮化鎵(GaN)電晶體與矽互補金屬氧化物半導體(CMOS)裝置共同整合以及形成此種裝置之領域。 Embodiments of the present invention are in the field of semiconductor devices and processing, and in particular to form low defect density gallium nitride on germanium wafers for gallium nitride (GaN) transistors and germanium complementary metal oxide semiconductor (CMOS) devices. Joint integration and the formation of such devices.

基於III族氮化物材料之電晶體適用於高電壓及高頻率的應用。因此，基於III族氮化物材料之電晶體是諸如電源管理積體電路(Power Management Integrated Circuit；簡稱PMIC)以及射頻(Radio Frequency；簡稱RF)功率放大器等的系統單晶片(System-on-Chip；簡稱SoC)應用之有前途的候選者。 Silicon crystals based on Group III nitride materials are suitable for high voltage and high frequency applications. Therefore, the III-based nitride material-based transistor is a system-on-chip (System-on-Chip; such as a Power Management Integrated Circuit (PMIC) and a Radio Frequency (RF) power amplifier; Promising candidates for SoC) applications.

100、200‧‧‧半導體基板 100,200‧‧‧Semiconductor substrate

115、215、315‧‧‧第一淺溝槽隔離層 115, 215, 315‧‧‧ first shallow trench isolation layer

120、127、220、227‧‧‧溝槽 120, 127, 220, 227‧‧‧ trenches

141‧‧‧氮化鎵材料 141‧‧‧ gallium nitride material

142‧‧‧位錯缺陷 142‧‧‧Dislocation defects

140、240、340‧‧‧第一氮化鎵層 140, 240, 340‧‧‧ first gallium nitride layer

143、243‧‧‧低缺陷密度部分 143, 243‧‧‧ low defect density part

141、241‧‧‧高缺陷密度部分 141, 241‧‧‧ high defect density part

145、245、345、445、545‧‧‧第二氮化鎵層 145, 245, 345, 445, 545‧‧‧ second gallium nitride layer

125、225‧‧‧第二淺溝槽隔離層 125, 225‧‧‧Second shallow trench isolation

221‧‧‧列 221‧‧‧

280、281‧‧‧方向 280, 281‧‧‧ directions

247、447、547‧‧‧導電層 247, 447, 547‧‧‧ conductive layer

360‧‧‧金屬氧化物半導體場效電晶體 360‧‧‧Metal Oxide Semiconductor Field Effect Transistor

362、462‧‧‧源極接點 362, 462‧‧‧ source contacts

364、464‧‧‧汲極接點 364, 464‧‧ ‧ 汲 contact

366、376‧‧‧閘極電極 366, 376‧‧‧ gate electrode

370‧‧‧金屬氧化物半導體電容 370‧‧‧Metal Oxide Semiconductor Capacitors

372‧‧‧歐姆接觸 372‧‧‧Ohm contact

374‧‧‧高K值介電質 374‧‧‧High K-value dielectric

460‧‧‧非平面金屬氧化物半導體場效電晶體裝置 460‧‧‧Non-planar metal oxide semiconductor field effect transistor device

468‧‧‧通道 468‧‧‧ channel

448‧‧‧第二導電層 448‧‧‧Second conductive layer

530‧‧‧懸臂樑 530‧‧‧Cantilever beam

600‧‧‧基板 600‧‧‧Substrate

682‧‧‧晶粒 682‧‧‧ grain

684‧‧‧矽部分 684‧‧‧矽part

686‧‧‧III族氮化物區 686‧‧‧III nitride zone

700‧‧‧轉接板 700‧‧‧Adapter plate

702‧‧‧第一基板 702‧‧‧First substrate

704‧‧‧第二基板 704‧‧‧second substrate

706‧‧‧銲球柵陣列 706‧‧‧ solder ball grid array

708‧‧‧金屬互連 708‧‧‧Metal interconnection

710‧‧‧通孔 710‧‧‧through hole

712‧‧‧穿透矽通孔 712‧‧‧through through hole

714‧‧‧嵌入式裝置 714‧‧‧ embedded devices

800‧‧‧計算裝置 800‧‧‧ Computing device

802‧‧‧積體電路晶粒 802‧‧‧Integrated circuit die

808‧‧‧通訊晶片 808‧‧‧Communication chip

804‧‧‧中央處理單元 804‧‧‧Central Processing Unit

806‧‧‧晶粒內置記憶體 806‧‧‧Grade internal memory

810‧‧‧揮發性記憶體 810‧‧‧ volatile memory

812‧‧‧非揮發性記憶體 812‧‧‧ Non-volatile memory

814‧‧‧圖形處理單元 814‧‧‧Graphic Processing Unit

816‧‧‧數位信號處理器 816‧‧‧Digital Signal Processor

842‧‧‧密碼處理器 842‧‧‧ cryptographic processor

820‧‧‧晶片組 820‧‧‧ chipsets

822‧‧‧天線 822‧‧‧Antenna

824‧‧‧觸控式螢幕顯示器 824‧‧‧Touch screen display

826‧‧‧觸控式螢幕控制器 826‧‧‧Touch screen controller

828‧‧‧電池 828‧‧‧Battery

844‧‧‧全球衛星定位系統裝置 844‧‧‧Global Positioning System (GPS) device

830‧‧‧羅盤 830‧‧‧ compass

832‧‧‧移動感測器 832‧‧‧Mobile sensor

834‧‧‧喇叭 834‧‧‧ Speaker

836‧‧‧相機 836‧‧‧ camera

838‧‧‧使用者輸入裝置 838‧‧‧User input device

840‧‧‧大量儲存裝置 840‧‧‧Many storage devices

第1A圖是根據本發明的一實施例而以磊晶方式生長 到不高於在一第一STI層中形成的溝槽的頂面的厚度之一第一氮化鎵層之一橫斷面圖。 Figure 1A is an epitaxial growth method in accordance with an embodiment of the present invention. A cross-sectional view of one of the first gallium nitride layers to a thickness no higher than a top surface of the trench formed in a first STI layer.

第1B圖是根據本發明的一實施例而以磊晶方式生長到一半導體基板上形成的一溝槽型樣之上的一第一氮化鎵層之一橫斷面圖。 1B is a cross-sectional view of a first gallium nitride layer grown epitaxially onto a trench pattern formed on a semiconductor substrate in accordance with an embodiment of the present invention.

第1C圖是根據本發明的一實施例而以磊晶方式生長到一第一磊晶生長氮化鎵層之上的一第二氮化鎵層之一橫斷面圖。 1C is a cross-sectional view of a second gallium nitride layer grown epitaxially onto a first epitaxially grown gallium nitride layer in accordance with an embodiment of the present invention.

第2A圖是根據本發明的一實施例而在一半導體基板之上形成的一第一淺溝槽隔離(STI)層中形成之一溝槽型樣之一透視圖。 2A is a perspective view of a trench pattern formed in a first shallow trench isolation (STI) layer formed over a semiconductor substrate in accordance with an embodiment of the present invention.

第2B圖是根據本發明的一實施例而在該等溝槽中以及在該第一STI層之上以磊晶方式生長的一第一氮化鎵層之一透視圖。 2B is a perspective view of a first gallium nitride layer grown in epitaxial manner in the trenches and over the first STI layer, in accordance with an embodiment of the present invention.

第2C圖是根據本發明的一額外實施例而在該等溝槽中以及在該第一STI層之上以磊晶方式生長的一第一氮化鎵層之一透視圖。 2C is a perspective view of a first gallium nitride layer grown in epitaxial manner in the trenches and over the first STI layer in accordance with an additional embodiment of the present invention.

第2D圖是根據本發明的一實施例的被定向成垂直於該第一STI層中之該溝槽型樣的一第二STI層中之一溝槽型樣之一透視圖。 2D is a perspective view of a trench pattern in a second STI layer oriented perpendicular to the trench pattern in the first STI layer, in accordance with an embodiment of the present invention.

第2E圖是根據本發明的一實施例而在該溝槽中且在該第二STI層之上以磊晶方式生長的一第二氮化鎵層之一透視圖。 2E is a perspective view of a second gallium nitride layer grown in the trench and epitaxially over the second STI layer in accordance with an embodiment of the present invention.

第2F圖是根據本發明的一實施例而在該溝槽中且在 一導電層之上以磊晶方式生長的一第二氮化鎵層之一透視圖。 Figure 2F is in the trench and in accordance with an embodiment of the present invention A perspective view of a second gallium nitride layer grown epitaxially over a conductive layer.

第3圖是根據本發明的一實施例而包含在一第一氮化鎵層中形成的一第一裝置以及在一第二氮化鎵層中形成的一第二裝置之一半導體基板之一透視圖。 3 is a diagram of a semiconductor substrate including a first device formed in a first gallium nitride layer and a second device formed in a second gallium nitride layer, in accordance with an embodiment of the present invention. perspective.

第4圖是根據本發明的一實施例而包含一非平面氮化鎵電晶體裝置之一半導體基板之一透視圖。 4 is a perspective view of a semiconductor substrate including a non-planar gallium nitride transistor device in accordance with an embodiment of the present invention.

第5圖是根據本發明的一實施例而包含一懸置氮化鎵層之一半導體基板之一透視圖。 Figure 5 is a perspective view of a semiconductor substrate including a suspended gallium nitride layer in accordance with an embodiment of the present invention.

第6圖是根據本發明的一實施例而包含一第一矽部分以及在基板的一第二部分之上形成的一III族氮化物層之一基板之一平面圖。 Figure 6 is a plan view of a substrate comprising a first germanium portion and a substrate of a group III nitride layer formed over a second portion of the substrate, in accordance with an embodiment of the present invention.

第7圖是實施本發明的一或多個實施例的一轉接板之一橫斷面圖。 Figure 7 is a cross-sectional view of one of the adapter plates embodying one or more embodiments of the present invention.

第8圖是包含根據本發明的一實施例而建構的一或多個電晶體的一計算裝置之一示意圖。 Figure 8 is a schematic illustration of a computing device including one or more transistors constructed in accordance with an embodiment of the present invention.

【發明內容與實施方式】 SUMMARY OF THE INVENTION AND EMBODIMENTS

本發明說明了包含一半導體裝置之系統以及形成該半導體裝置之方法。在下文的說明中，將使用熟悉此項技術者普遍用於將其工作之內容傳遞給其他熟悉此項技術者的術語說明各實施例之各種觀點。然而，熟悉此項技術者顯然理解：可以只利用所說明的該等觀點中之某些觀點實施實施例。為了便於解說，述及了一些特定的數字、材料、 及組態，以便提供對該等實施例之徹底了解。然而，熟悉此項技術者顯然理解：可在沒有該等特定細節之情形下實施實施例。在其他的情形中，省略或簡化了習知的特徵，以便不會模糊了該等說明性實施例。 The present invention describes a system including a semiconductor device and a method of forming the same. In the following description, various aspects of the various embodiments will be described using the terms commonly used by those skilled in the art to <RTIgt; However, it will be apparent to those skilled in the art that the embodiments may be practiced using only some of the described aspects. For the sake of explanation, some specific figures, materials, And configuration to provide a thorough understanding of the embodiments. However, it is apparent to those skilled in the art that the embodiments may be practiced without the specific details. In other instances, well-known features are omitted or simplified so as not to obscure the illustrative embodiments.

將以一種最有助於了解本發明之方式，而以依次進行的多個分立式操作之形式說明各操作，然而，不應將說明的順序詮釋為意味著這些操作必然是與順序相依的。尤其，不需要按照呈現的順序執行這些操作。 Each operation will be described in the form of a plurality of discrete operations that are performed in a manner that is most helpful in understanding the present invention. However, the order of the description should not be construed as meaning that the operations are necessarily sequential. . In particular, it is not necessary to perform these operations in the order presented.

雖然基於III族氮化物材料之電晶體是SoC應用之有前途的候選者，但是將基於III族氮化物材料之電晶體共同整合在一半導體基板上也是很大的挑戰。一個挑戰是該等材料之間的重大晶格失配(lattice mismatch)。例如，氮化鎵(GaN)與(100)晶向((100)oriented)之矽(Si)之間的晶格失配是大約41%。此種重大晶格失配產生了在一矽層上以磊晶方式生長的氮化鎵中之高缺陷密度。此外，矽與氮化鎵之間的熱膨脹係數(thermal expansion coefficient)失配可能導致在矽上以磊晶方式生長的氮化鎵上之表面裂紋(surface crack)。例如，該等兩種材料之間的熱膨脹係數差異可以是大約116%。 Although III-based nitride material-based transistors are promising candidates for SoC applications, it is also a significant challenge to integrate a Group III nitride-based transistor together on a semiconductor substrate. One challenge is the significant lattice mismatch between these materials. For example, the lattice mismatch between gallium nitride (GaN) and (100) crystal orientation (()) is about 41%. This significant lattice mismatch produces a high defect density in gallium nitride grown epitaxially on a layer of germanium. In addition, a thermal expansion coefficient mismatch between germanium and gallium nitride may result in a surface crack on the gallium nitride grown epitaxially on the germanium. For example, the difference in coefficient of thermal expansion between the two materials can be about 116%.

可藉由使用緩衝層較徐緩地自第一半導體材料的晶格間距(lattice spacing)改變到第二半導體材料的晶格間距，而適應晶格失配。此外，可藉由使用寬高比捕獲(aspect ratio trapping)寬而減少晶格缺陷。寬高比捕獲可利用沿著各滑移面(slip plane)的位錯(例如，穿透位 錯(threading dislocation))之傳播。當該缺陷抵達該寬高比捕獲溝槽的側壁時，可阻止該缺陷進一步延伸。因此，可在該寬高比捕獲溝槽的頂部上形成具有較低缺陷密度的一材料。然而，該機制在因該等滑移面的方向而以磊晶方式生長氮化鎵時可能不那麼有效。在氮化鎵中，該等缺陷可能沿著實質上垂直的一滑移面而擴展。因此，該等缺陷可能永遠不會抵達該溝槽的該等側壁。因此，寬高比捕獲可能無法單獨顯著地減少氮化鎵的缺陷密度。 The lattice mismatch can be accommodated by using a buffer layer that changes more slowly from the lattice spacing of the first semiconductor material to the lattice spacing of the second semiconductor material. In addition, lattice defects can be reduced by using aspect ratio trapping width. Aspect ratio capture can utilize dislocations along each slip plane (eg, puncturing bits) The spread of threading dislocation. When the defect reaches the sidewall of the aspect ratio capture trench, the defect can be prevented from further extending. Thus, a material having a lower defect density can be formed on top of the aspect ratio capture trench. However, this mechanism may be less effective in epitaxially growing gallium nitride due to the direction of the slip planes. In gallium nitride, the defects may expand along a substantially vertical slip plane. Therefore, the defects may never reach the side walls of the trench. Therefore, aspect ratio capture may not significantly reduce the defect density of gallium nitride alone.

在氮化鎵系統中，由於晶格失配而產生穿透位錯。在一矽基板上以磊晶方式生長的氮化鎵層中之晶格失配特別明顯。如前文所述，氮化鎵與(100)晶向的矽之間的晶格失配是大約41%。因此，以磊晶方式生長的氮化鎵層通常將有高缺陷密度。該高缺陷密度產生了使基於氮化鎵之電晶體無法在峰值理論效率下工作的陷阱及塊材陷阱(bulk trap)。因此，雖然氮化鎵電晶體對高電壓應用(例如，PMIC及RF應用)是理論上理想的，但是實際上，氮化鎵的高電壓效益不如預期那麼大。 In GaN systems, threading dislocations occur due to lattice mismatch. The lattice mismatch in the epitaxially grown gallium nitride layer on a germanium substrate is particularly pronounced. As mentioned earlier, the lattice mismatch between gallium nitride and the (100) crystal orientation is about 41%. Therefore, a gallium nitride layer grown in an epitaxial manner will generally have a high defect density. This high defect density creates traps and bulk traps that prevent gallium nitride based transistors from operating at peak theoretical efficiency. Thus, while gallium nitride transistors are theoretically ideal for high voltage applications (eg, PMIC and RF applications), in practice, the high voltage benefits of gallium nitride are not as great as expected.

因此，本發明之實施例將穿透位錯的傳播方向用於形成低缺陷密度氮化鎵層。在氮化鎵中，穿透位錯可沿著兩個不同的面而傳播。可傳播穿透位錯的第一面是(1100)。在本申請案的各實施例中，該面被定向成使位錯沿著垂直方向(亦即，平行於生長方向)而傳播。可傳播穿透位錯的第二面是(0001)面。在本申請案的各實施例中，該面被定向成使位錯沿著水平方向(亦即，垂直於生 長方向)而傳播。 Thus, embodiments of the present invention use the propagation direction of threading dislocations to form a low defect density gallium nitride layer. In gallium nitride, threading dislocations can propagate along two different faces. The first side that can propagate threading dislocations is (1100). In various embodiments of the present application, the face is oriented such that dislocations propagate in a vertical direction (i.e., parallel to the growth direction). The second side that can propagate the threading dislocation is the (0001) plane. In various embodiments of the present application, the face is oriented such that the dislocations are in a horizontal direction (ie, perpendicular to the Spread in the long direction).

在以磊晶方式生長的氮化鎵層中，溝槽的定向以及磊晶生長的製程條件(process condition)被用於決定將發生何種缺陷傳播方式。第1A-1C圖示出本發明之實施例如何可將一交叉點溝槽設計用於最小化或消除第二氮化鎵層中之缺陷。雖然本發明中將詳細說明氮化鎵層，但是應當理解：用於減少氮化鎵層中之缺陷密度的製程同樣適用於許多不同的半導體材料。例如，本發明之實施例可以任何III族氮化物(III-N)層取代一氮化鎵層。 In the epitaxially grown gallium nitride layer, the orientation of the trench and the process conditions of the epitaxial growth are used to determine which defect propagation mode will occur. 1A-1C illustrate how an embodiment of the present invention can be used to minimize or eliminate defects in the second gallium nitride layer. While the gallium nitride layer will be described in detail in the present invention, it should be understood that the process for reducing the defect density in the gallium nitride layer is equally applicable to many different semiconductor materials. For example, embodiments of the invention may replace a gallium nitride layer with any of the group III nitride (III-N) layers.

現在請參閱第1A圖，根據本發明的一實施例而示出一半導體基板100之一橫斷面圖。可在半導體基板100的一頂面之上形成一第一STI層115。在一實施例中，可形成通過第一STI層115之複數個溝槽120。該等溝槽120可以是適於寬高比捕獲製程之高寬高比溝槽。然後可在半導體基板100中沿著該等溝槽120的底部而露出之該等部分之上以磊晶方式生長一氮化鎵材料141。根據一實施例，可在氮化鎵材料141與半導體基板100之間形成一成核層(nucleation layer)(圖中未示出)。例如，一成核層可包括氮化鋁(AlN)、氮化鋁鎵(AlGaN)、氮化銦(InN)、或氮化鋁銦(AlInN)等的材料。在某些實施例中，可以只在該等溝槽120中形成該成核層，或者可在STI層115及半導體基板100之上以保形方式沈積該成核層。根據一實施例，該成核層之總厚度小於STI層115之厚度。例如，該成核層可具有大約15奈米與200奈米之 間的厚度。 Referring now to FIG. 1A, a cross-sectional view of a semiconductor substrate 100 is shown in accordance with an embodiment of the present invention. A first STI layer 115 may be formed over a top surface of the semiconductor substrate 100. In an embodiment, a plurality of trenches 120 through the first STI layer 115 may be formed. The trenches 120 can be high aspect ratio trenches suitable for the aspect ratio capture process. A gallium nitride material 141 can then be epitaxially grown over the portions of the semiconductor substrate 100 that are exposed along the bottom of the trenches 120. According to an embodiment, a nucleation layer (not shown) may be formed between the gallium nitride material 141 and the semiconductor substrate 100. For example, a nucleation layer may include materials such as aluminum nitride (AlN), aluminum gallium nitride (AlGaN), indium nitride (InN), or aluminum indium nitride (AlInN). In some embodiments, the nucleation layer can be formed only in the trenches 120, or the nucleation layer can be deposited in a conformal manner over the STI layer 115 and the semiconductor substrate 100. According to an embodiment, the total thickness of the nucleation layer is less than the thickness of the STI layer 115. For example, the nucleation layer can have approximately 15 nm and 200 nm The thickness between the two.

如前文所述，當在一矽基板100之上以磊晶方式生長氮化鎵時，該等兩層之間可能有顯著的晶格失配。因此，可能有在該以磊晶方式生長的氮化鎵141中形成之高密度的位錯缺陷142。此外，寬高比捕獲可能無法單獨對位錯密度提供顯著的改善，這是因為該等位錯缺陷142沿著平行於生長方向以及溝槽120的壁之一滑移面而傳播。 As described above, when gallium nitride is grown epitaxially over a germanium substrate 100, there may be significant lattice mismatch between the two layers. Therefore, there may be a high-density dislocation defect 142 formed in the epitaxial gallium nitride 141. Moreover, aspect ratio capture may not provide a significant improvement in dislocation density alone because the dislocation defects 142 propagate along parallel to the growth direction and one of the walls of the trench 120.

現在請參閱第1B圖，根據本發明的一實施例而示出在一第一氮化鎵層140的進一步生長之後的基板100之一橫斷面圖。根據一實施例，氮化鎵層140可延伸到第一STI層115的頂面之上。氮化鎵層140一旦延伸到第一STI層115之上之後，就不再被該等溝槽120限制，且除了垂直地生長外，也開始橫向地生長。因此，氮化鎵層140可合併在一起，而形成一單一連續層。如圖所示，該等位錯缺陷142繼續沿著垂直方向延伸。然而，因為該等位錯缺陷142只沿著垂直方向(亦即，沿著在115面)傳播，所以在沒有缺陷的情形下形成橫向生長。因此，第一氮化鎵層140可包含在第一STI層115的頂面之上的橫向生長中形成之低缺陷密度部分143、以及在第一STI層115的該等溝槽120中形成的以及在該等溝槽120之上形成的高缺陷密度部分141。 Referring now to FIG. 1B, a cross-sectional view of a substrate 100 after further growth of a first gallium nitride layer 140 is shown in accordance with an embodiment of the present invention. According to an embodiment, the gallium nitride layer 140 may extend over the top surface of the first STI layer 115. Once extended over the first STI layer 115, the gallium nitride layer 140 is no longer confined by the trenches 120 and begins to grow laterally in addition to being grown vertically. Thus, the gallium nitride layer 140 can be combined to form a single continuous layer. As shown, the dislocation defects 142 continue to extend in the vertical direction. However, since the dislocation defects 142 propagate only in the vertical direction (i.e., along the 115 faces), lateral growth is formed without defects. Accordingly, the first gallium nitride layer 140 may include a low defect density portion 143 formed in lateral growth over the top surface of the first STI layer 115, and formed in the trenches 120 of the first STI layer 115. And a high defect density portion 141 formed over the trenches 120.

現在請參閱第1C圖，根據本發明的一實施例而示出在形成了一第二氮化鎵層145之後的基板100之一橫斷面圖。在一實施例中，可將低缺陷密度部分143用來作為一 晶種層(seed layer)，以便可選擇性地沿著垂直方向在低缺陷密度部分143之上生長，而形成第二氮化鎵層145。在一實施例中，藉由形成其中包含一或多個溝槽127的一第二STI層125，而可選擇性地生長低缺陷密度部分143，其中該一或多個溝槽127被定位在第一STI層115的頂面之上，且該一或多個溝槽127被垂直地定向(亦即，自該圖的面離開)。因此，第一氮化鎵層140的高缺陷密度部分141中之位錯缺陷142被第二STI層125的底面阻擋，且容許第一氮化鎵層140的低缺陷密度部分143延伸通過第二STI層125中形成的溝槽127。在第二氮化鎵層145延伸到溝槽127之上之後，該第二氮化鎵層145可接著開始沿著第二STI層125的頂面而橫向地延伸，用以形成一平面區的低缺陷密度氮化鎵。因此，整個第二氮化鎵層145可具有低缺陷密度。 Referring now to FIG. 1C, a cross-sectional view of one of the substrates 100 after forming a second gallium nitride layer 145 is shown in accordance with an embodiment of the present invention. In an embodiment, the low defect density portion 143 can be used as a A seed layer is formed so as to be selectively grown on the low defect density portion 143 in the vertical direction to form the second gallium nitride layer 145. In one embodiment, the low defect density portion 143 is selectively grown by forming a second STI layer 125 having one or more trenches 127 therein, wherein the one or more trenches 127 are positioned Above the top surface of the first STI layer 115, the one or more trenches 127 are oriented vertically (ie, away from the face of the figure). Therefore, the dislocation defect 142 in the high defect density portion 141 of the first gallium nitride layer 140 is blocked by the bottom surface of the second STI layer 125, and allows the low defect density portion 143 of the first gallium nitride layer 140 to extend through the second A trench 127 is formed in the STI layer 125. After the second gallium nitride layer 145 extends over the trench 127, the second gallium nitride layer 145 may then begin to extend laterally along the top surface of the second STI layer 125 to form a planar region. Low defect density gallium nitride. Therefore, the entire second gallium nitride layer 145 can have a low defect density.

根據一實施例，第二氮化鎵層145的低缺陷密度適用於需要高性能及高電壓的氮化鎵電晶體之應用(例如，PMIC或RF應用)。此外，應當理解：第一氮化鎵層140不是該等處理操作的無使用之副產品。例如，第一氮化鎵層140亦可被用於不依賴低缺陷密度之組件(例如，電容、肖特基二極體(Schottky diode)、或RF濾波器等的組件)。此外，應當理解：可在任何尺寸的基板(例如，100毫米、150毫米、200毫米、300毫米、450毫米等的尺寸的基板)之上生長低缺陷密度氮化鎵層140。如此一來，本發明之實施例可容許大量製造(High Volume Manufacturing；簡稱HVM)低缺陷密度氮化鎵。 According to an embodiment, the low defect density of the second gallium nitride layer 145 is suitable for applications requiring high performance and high voltage gallium nitride transistors (eg, PMIC or RF applications). Moreover, it should be understood that the first gallium nitride layer 140 is not a by-product of such processing operations. For example, the first gallium nitride layer 140 can also be used for components that do not rely on low defect density (eg, capacitors, Schottky diodes, or components of RF filters, etc.). In addition, it should be understood that the low defect density gallium nitride layer 140 can be grown over a substrate of any size (eg, a substrate of a size of 100 mm, 150 mm, 200 mm, 300 mm, 450 mm, etc.). As such, embodiments of the present invention allow for mass manufacturing (High Volume Manufacturing; referred to as HVM) low defect density gallium nitride.

現在請參閱第2A-2F圖，以透視圖示出用於形成一低缺陷密度氮化鎵層的一製程，以便更完整地解說本發明的觀點。 Referring now to Figures 2A-2F, a process for forming a low defect density gallium nitride layer is shown in perspective to more fully illustrate the aspects of the present invention.

現在請參閱第2A圖，根據本發明的一實施例而示出包含一半導體基板200以及一第一STI層215的一裝置之一透視圖。根據一實施例，可在任何適當的結晶半導體基板200上形成該裝置。在一特定實施例中，該半導體基板是具有一{111}晶向的一塊狀矽(bulk silicon)或一絕緣層上覆矽(silicon-on-insulator)基板200。在其他實施例中，可使用與後續處理操作中生長的氮化鎵層有晶格失配的替代材料形成半導體基板200，其中該等替代材料可與或可不與矽結合。根據一實施例，該等額外的材料可包括但不限於鍺、銻化銦(indium antimonide)、碲化鉛(lead telluride)、砷化銦(indium arsenide)、磷化銦(indium phosphide)、砷化鎵(gallium arsenide)、砷化銦鎵(indium gallium arsenide)、銻化鎵(gallium antimonide)、碳化矽(SiC)、藍寶石、或III-V族材料或IV族材料的其他組合。雖然本說明書說明了可用於形成該基板的材料之一些例子，但是可被用來作為可在其上建造一半導體裝置的基礎之任何材料都在本發明的精神及範圍內。 Referring now to FIG. 2A, a perspective view of a device including a semiconductor substrate 200 and a first STI layer 215 is shown in accordance with an embodiment of the present invention. According to an embodiment, the device can be formed on any suitable crystalline semiconductor substrate 200. In a particular embodiment, the semiconductor substrate is a bulk silicon or a silicon-on-insulator substrate 200 having a {111} crystal orientation. In other embodiments, the semiconductor substrate 200 can be formed using an alternative material that is lattice mismatched with the gallium nitride layer grown in subsequent processing operations, wherein the alternate materials may or may not be combined with germanium. According to an embodiment, the additional materials may include, but are not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, arsenic. Gallium arsenide, indium gallium arsenide, gallium antimonide, tantalum carbide (SiC), sapphire, or other combination of III-V materials or Group IV materials. Although the present specification describes some examples of materials that can be used to form the substrate, any material that can be used as a basis upon which a semiconductor device can be built is within the spirit and scope of the present invention.

根據一實施例，第一STI層215可以是任何適當的介電材料。例如，第一STI層215可以是氧化物。本發明之 實施例可包含通過該第一STI層而形成之複數個溝槽220。在一實施例中，該等溝槽220可被定向在各溝槽列221中，其中沿著基於下方半導體基板200的晶向之一預定方向(如箭頭280所示)對齊該等溝槽列221。例如，當下方半導體基板200是具有{111}晶向的一矽基板時，該等溝槽列221可被定向成係為<110>方向的一方向280。根據本發明的一實施例，該等溝槽220可以是任何適於形成高寬高比溝槽的尺寸。在一實施例中，該等溝槽的形狀可以是矩形或正方形，但是各實施例不限於此類組態。例如，該等溝槽可具有大約50-300奈米x 50-300奈米的尺寸。 According to an embodiment, the first STI layer 215 can be any suitable dielectric material. For example, the first STI layer 215 can be an oxide. The invention Embodiments can include a plurality of trenches 220 formed by the first STI layer. In an embodiment, the trenches 220 can be oriented in each of the trench columns 221, wherein the trench columns are aligned along a predetermined direction (as indicated by arrow 280) based on the crystal orientation of the underlying semiconductor substrate 200. 221. For example, when the lower semiconductor substrate 200 is a germanium substrate having a {111} crystal orientation, the trench columns 221 can be oriented in a direction 280 that is in the <110> direction. According to an embodiment of the invention, the trenches 220 may be any size suitable for forming high aspect ratio trenches. In an embodiment, the shapes of the grooves may be rectangular or square, but embodiments are not limited to such configurations. For example, the grooves can have a size of about 50-300 nm x 50-300 nm.

在一實施例中，可選擇該等溝槽220之間的間隔，以便提供後續形成的氮化鎵層之受控制的生長。例如，相同列221中之各溝槽220之間的間隔S1可小於不同列221中之各溝槽220之間的間隔S2。提供較小的間隔S1時，可使後續形成的氮化鎵層沿著該等列221中之每一列而合併在一起，而不會使該等列221合併在一起。例如，S2可比S1大了大約一倍半。 In an embodiment, the spacing between the trenches 220 can be selected to provide controlled growth of the subsequently formed gallium nitride layer. For example, the spacing S 1 between the trenches 220 in the same column 221 may be less than the spacing S 2 between the trenches 220 in the different columns 221 . 1 provide a small spacing S, the subsequent gallium nitride layer can be formed along each of these columns in column 221 and combined, without making such columns 221 combined. For example, S 2 can be about one and a half times larger than S 1 .

現在請參閱第2B圖，根據本發明的一實施例而示出在以磊晶方式生長第一氮化鎵層240之後的該裝置之一透視圖。在一實施例中，可利用諸如金屬有機化學氣相沈積(Metalorganic Chemical Vapor Deposition；簡稱MOCVD)或分子束磊晶(Molecular Beam Epitaxy；簡稱MBE)等的任何適當之磊晶沈積製程生長該氮化鎵。此 外，在該等溝槽中生長第一氮化鎵層240時，將減少該第一氮化鎵層的填充因數(fill factor)。例如，可以只在大約10%或更小的表面積之上生長該氮化鎵。因此，可增加生長速率，因而減少製程時間。因此，本發明之實施例適於大量製造(HVM)。 Referring now to FIG. 2B, a perspective view of the apparatus after epitaxial growth of the first gallium nitride layer 240 is illustrated in accordance with an embodiment of the present invention. In an embodiment, the nitridation may be grown by any suitable epitaxial deposition process such as Metalorganic Chemical Vapor Deposition (MOCVD) or Molecular Beam Epitaxy (MBE). gallium. this In addition, when the first gallium nitride layer 240 is grown in the trenches, the fill factor of the first gallium nitride layer is reduced. For example, the gallium nitride can be grown only over a surface area of about 10% or less. Therefore, the growth rate can be increased, thereby reducing the process time. Thus, embodiments of the present invention are suitable for mass production (HVM).

在一實施例中，可將半導體基板200的該等露出部分用來作為晶種層，而生長第一氮化鎵層240。額外的實施例可包含：在生長該氮化鎵層之前，先在半導體基板200的該等露出部分之上形成一或多個緩衝層(圖中未示出)。例如，在生長第一氮化鎵層240之前，可先在半導體基板200之上形成一氮化鋁(AlN)層。 In one embodiment, the exposed portions of the semiconductor substrate 200 can be used as a seed layer to grow the first gallium nitride layer 240. Additional embodiments may include forming one or more buffer layers (not shown) over the exposed portions of the semiconductor substrate 200 prior to growing the gallium nitride layer. For example, an aluminum nitride (AlN) layer may be formed over the semiconductor substrate 200 prior to growing the first gallium nitride layer 240.

如圖所示，一旦生長不再被限制之後，第一氮化鎵層240可生長到該等溝槽220之上，且開始沿著橫向方向而伸展。第一氮化鎵層240的橫向生長可讓氮化鎵合併，而在第一STI層215之上形成一些氮化鎵條。除了控制間隔S1及S2而使第一氮化鎵層240不會在各列之間合併之外，可將磊晶生長的製程條件修改成使沿著該等列的方向之生長以比沿著各列間之方向之生長快之方式進行。例如，磊晶生長期間之較高的溫度及較低的壓力將導致沿著該等列的方向之橫向生長速率比沿著該等列之間的方向之橫向生長速率快。 As shown, once the growth is no longer limited, the first gallium nitride layer 240 can be grown over the trenches 220 and begin to stretch in the lateral direction. The lateral growth of the first gallium nitride layer 240 allows the gallium nitride to merge while forming some gallium nitride strips over the first STI layer 215. In addition to controlling the intervals S 1 and S 2 such that the first gallium nitride layer 240 is not combined between the columns, the process conditions for epitaxial growth can be modified to cause growth along the direction of the columns. The growth along the direction between the columns is fast. For example, higher temperatures and lower pressures during epitaxial growth will result in a lateral growth rate along the direction of the columns being faster than a lateral growth rate along the direction between the columns.

與第1B圖所示的橫斷面圖以及前文中參照該圖所述的類似，第一氮化鎵層240中之位錯與該等溝槽220內及正上方的區域隔離，這是因為穿透位錯只沿著垂直方向傳 播。因此，第一氮化鎵層240可包含低缺陷密度區243以及高缺陷密度區241。在第2B圖中，該等高缺陷密度區241位於指示在第一氮化鎵層240之下形成該等溝槽220的該等虛線內。 Similar to the cross-sectional view shown in FIG. 1B and the foregoing description with reference to the figure, the dislocations in the first gallium nitride layer 240 are isolated from the regions in and above the trenches 220 because Penetration dislocations only pass along the vertical direction broadcast. Therefore, the first gallium nitride layer 240 may include the low defect density region 243 and the high defect density region 241. In FIG. 2B, the contoured high defect density regions 241 are located within the dashed lines indicating the formation of the trenches 220 under the first gallium nitride layer 240.

在第2B圖中，該等條的第一氮化鎵層240具有垂直側壁(亦即，也被稱為m面之(101 0)面)。然而，本發明之實施例不限於此類組態。例如，第2C圖示出包含三角形小面(facet)(亦即，(101 2)面)之一實質上類似的第一氮化鎵層240。然而，應當理解：在任一實施例中之第一氮化鎵層240的頂面是用於電晶體製造及其他裝置的較佳定向之c面(亦即，(0001)面)。當在磊晶生長製程期間使用較高的壓力時，可產生第一氮化鎵層240中之(101 2)面的形成。 In Figure 2B, the first gallium nitride layer 240 of the strips has vertical sidewalls (i.e., also referred to as the m-plane (101 0) plane). However, embodiments of the invention are not limited to such configurations. For example, Figure 2C shows a first gallium nitride layer 240 comprising substantially one of triangular facets (i.e., (101 2) faces). However, it should be understood that the top surface of the first gallium nitride layer 240 in any embodiment is the c-plane (i.e., the (0001) plane) for the preferred orientation of the transistor fabrication and other devices. The formation of the (101 2) face in the first gallium nitride layer 240 can be produced when a higher pressure is used during the epitaxial growth process.

現在請參閱第2D圖，根據本發明的一實施例而示出在形成了第二STI層225之後的一單一條之一透視圖。在該所示之實施例中，第二STI層225是一介電材料。例如，第二STI層225可以是與第一STI層215相同的材料。根據一額外的實施例，可以一導電層取代第二STI層225。此種實施例可形成不同的電晶體類型，且將於後文中更詳細地說明此種實施例。根據一實施例，可在第二STI層225中產生圖案，以便形成第二複數個溝槽227。該等第二溝槽227可被定向在垂直於第一氮化鎵層240的該等條的氮化鎵的方向280之第二方向281。例如，當半導體基板200是一{111}矽基板時，該等第二溝槽227可 被定向在<112>方向。此外，本發明之實施例包含：對齊該等第二溝槽227，使該等溝槽227不露出第一氮化鎵層240的高缺陷密度部分241。為了有助於了解該等第二溝槽227的位置，該複數個第一溝槽220的位置被示出為在第二STI層225之上的虛線。因此，第一氮化鎵層240的唯一露出部分是低缺陷密度區243。 Referring now to FIG. 2D, a perspective view of a single strip after formation of the second STI layer 225 is illustrated in accordance with an embodiment of the present invention. In the illustrated embodiment, the second STI layer 225 is a dielectric material. For example, the second STI layer 225 can be the same material as the first STI layer 215. According to an additional embodiment, the second STI layer 225 can be replaced by a conductive layer. Such embodiments may form different transistor types and such embodiments will be described in greater detail below. According to an embodiment, a pattern may be created in the second STI layer 225 to form a second plurality of trenches 227. The second trenches 227 can be oriented in a second direction 281 that is perpendicular to the direction 280 of the gallium nitride of the first gallium nitride layer 240. For example, when the semiconductor substrate 200 is a {111} 矽 substrate, the second trenches 227 may be Oriented in the <112> direction. Moreover, embodiments of the present invention include aligning the second trenches 227 such that the trenches 227 do not expose the high defect density portion 241 of the first gallium nitride layer 240. To aid in understanding the location of the second trenches 227, the locations of the plurality of first trenches 220 are shown as dashed lines above the second STI layer 225. Therefore, the only exposed portion of the first gallium nitride layer 240 is the low defect density region 243.

現在請參閱第2E圖，根據本發明的一實施例而示出在生長了第二氮化鎵層245之後的該裝置之一透視圖。根據一實施例，可利用諸如MOCVD或MBE等的任何適當之磊晶生長製程生長第二氮化鎵層245。與第一氮化鎵層240的生長製程類似，在該等第二溝槽227中生長第二氮化鎵層245時，將減少第二氮化鎵層245的填充因數。因此，可增加生長速率，因而減少製程時間，且允許可進行大量製造。 Referring now to Figure 2E, a perspective view of the device after growth of the second gallium nitride layer 245 is shown in accordance with an embodiment of the present invention. According to an embodiment, the second gallium nitride layer 245 may be grown using any suitable epitaxial growth process such as MOCVD or MBE. Similar to the growth process of the first gallium nitride layer 240, when the second gallium nitride layer 245 is grown in the second trenches 227, the fill factor of the second gallium nitride layer 245 will be reduced. Therefore, the growth rate can be increased, thereby reducing the process time, and allowing mass production to be performed.

可藉由將低缺陷密度部分243用來作為一晶種層，以便可選擇性地沿著垂直方向在低缺陷密度部分243之上生長，而形成第二氮化鎵層245。在一實施例中，只容許生長低缺陷密度部分243，這是因為第二STI層225覆蓋了第一氮化鎵層240的高缺陷密度部分241之頂面。因此，第二STI層225的底面阻擋了第一氮化鎵層240的高缺陷密度部分241中存在的位錯缺陷。第二氮化鎵層245延伸到該等第二溝槽227之上之後，可開始沿著第二STI層225的頂面而橫向延伸，而形成低缺陷密度氮化鎵的一平面區。因此，整個第二氮化鎵層245可具有低缺陷密度。 The second gallium nitride layer 245 can be formed by using the low defect density portion 243 as a seed layer so as to be selectively grown along the vertical direction over the low defect density portion 243. In an embodiment, only the low defect density portion 243 is allowed to grow because the second STI layer 225 covers the top surface of the high defect density portion 241 of the first gallium nitride layer 240. Therefore, the bottom surface of the second STI layer 225 blocks the dislocation defects existing in the high defect density portion 241 of the first gallium nitride layer 240. After the second gallium nitride layer 245 extends over the second trenches 227, it may begin to extend laterally along the top surface of the second STI layer 225 to form a planar region of low defect density gallium nitride. Therefore, the entire second gallium nitride layer 245 can have a low defect density.

如前文所述，本發明的某些實施例可包含：以一導電層247取代第二STI層225。第2F圖所示之透視圖示出此種實施例。在一實施例中，可在前文所述的沈積第二STI層225且在第二STI層225中產生圖案的流程中之相同點上沈積導電層247且在導電層247中產生圖案。或者，可以前文所述之方式形成第二STI層225，然後在形成了第二STI層225之後，利用一蝕刻製程移除第二STI層225。然後可在第二氮化鎵層245周圍回填(back fill)導電層247。進一步的實施例可包含：在導電層247與第一及第二氮化鎵層240、245之間形成一介電層(圖中未示出)。如將於下文中更詳細說明的，當該導電層被用來作為一非平面電晶體(non-planar transistor)的一閘極電極時，此類實施例可能是有利的。 As mentioned previously, certain embodiments of the invention may include replacing the second STI layer 225 with a conductive layer 247. The perspective view shown in Fig. 2F shows such an embodiment. In an embodiment, conductive layer 247 may be deposited and a pattern created in conductive layer 247 at the same point in the process of depositing second STI layer 225 and creating a pattern in second STI layer 225 as previously described. Alternatively, the second STI layer 225 can be formed in the manner described above, and then after the second STI layer 225 is formed, the second STI layer 225 is removed using an etching process. Conductive layer 247 can then be backfilled around second gallium nitride layer 245. A further embodiment may include forming a dielectric layer (not shown) between the conductive layer 247 and the first and second gallium nitride layers 240, 245. As will be explained in more detail below, such an embodiment may be advantageous when the conductive layer is used as a gate electrode of a non-planar transistor.

應當理解：前文所述之流程包含形成兩個不同的氮化鎵層。第一氮化鎵層240包含高缺陷密度區241及低缺陷密度區243，而完全由一低缺陷密度材料形成第二氮化鎵層245。因此，第二氮化鎵層245適於需要高性能及高電壓的氮化鎵電晶體之應用(例如，PMIC或RF應用)。然而，這並不排除將第一氮化鎵層240用於不需要高性能特性的其他應用。因此，本發明之實施例可藉由在兩層上製造組件，而增加該裝置的表面積之利用率。以與第3圖有關之方式示出且說明根據此種實施例的一裝置。 It should be understood that the process described above involves forming two different gallium nitride layers. The first gallium nitride layer 240 includes a high defect density region 241 and a low defect density region 243, and the second gallium nitride layer 245 is formed entirely of a low defect density material. Thus, the second gallium nitride layer 245 is suitable for applications requiring high performance and high voltage gallium nitride transistors (eg, PMIC or RF applications). However, this does not preclude the use of the first gallium nitride layer 240 for other applications that do not require high performance characteristics. Thus, embodiments of the present invention can increase the utilization of the surface area of the device by fabricating components on both layers. A device according to such an embodiment is shown and described in relation to Figure 3.

現在請參閱第3圖，根據本發明的一實施例而示出包含在一第一氮化鎵層340以及一第二氮化鎵層345上形成 的組件的一裝置之一透視圖。如前文所述，第二氮化鎵層345將是有最低的缺陷密度且因而有較少的陷阱以及塊材陷阱狀態之層。可將該層用於形成PMIC及RF應用之高性能及高電壓氮化鎵裝置。例如，可在第二氮化鎵層345上形成一金屬氧化物半導體場效電晶體(Metal Oxide Semiconductor Field Effect Transistor；簡稱MOSFET)360。在一實施例中，氮化鎵MOSFET 360可包含在第二氮化鎵層345的頂面上形成之一源極接點362、一汲極接點364、以及一閘極電極366。雖然圖中未示出，但是應當理解：可在閘極電極366與第二氮化鎵層345的面之間形成一閘極介電層(gate dielectric layer)。此外，第二氮化鎵層345可包含在源極及汲極接點362/364之下及/或在閘極電極366之下的源極及汲極區中之摻雜劑，以便將所需的電性提供給氮化鎵MOSFET 360。例如，可在第二氮化鎵層345的磊晶生長期間以原處摻雜方式摻雜該等摻雜劑，且/或可在形成第二氮化鎵層345之後植入(例如，離子植入及/或擴散)該等摻雜劑。 Referring now to FIG. 3, a first gallium nitride layer 340 and a second gallium nitride layer 345 are formed in accordance with an embodiment of the present invention. A perspective view of one of the components of the assembly. As previously described, the second gallium nitride layer 345 will be the layer with the lowest defect density and thus fewer traps and bulk trap states. This layer can be used to form high performance and high voltage gallium nitride devices for PMIC and RF applications. For example, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) 360 may be formed on the second gallium nitride layer 345. In one embodiment, the gallium nitride MOSFET 360 can include a source contact 362, a drain contact 364, and a gate electrode 366 formed on the top surface of the second gallium nitride layer 345. Although not shown in the drawings, it should be understood that a gate dielectric layer may be formed between the gate electrode 366 and the face of the second gallium nitride layer 345. In addition, the second gallium nitride layer 345 can include dopants in the source and drain regions below the source and drain contacts 362/364 and/or below the gate electrode 366. The required electrical conductivity is provided to the GaN MOSFET 360. For example, the dopants may be doped in situ during the epitaxial growth of the second gallium nitride layer 345 and/or may be implanted after forming the second gallium nitride layer 345 (eg, ions) Implanting and/or diffusing the dopants.

此外，可在第一氮化鎵層340上製造具有較少的缺陷密度要求之一第二組件。例如，可在第一氮化鎵層340上形成一氮化鎵金屬氧化物半導體(Metal Oxide Semiconductor；簡稱MOS)電容370。在該所示實施例中，MOS電容370可包含在第一氮化鎵層340之上形成的一歐姆接觸372、一高K值介電質374、以及一閘極電極376。當該裝置包含PMIC或RF功率放大(Power Amplification；簡稱PA)電路時，包含一MOS電容370以及一高電壓MOSFET可能特別有利。 Additionally, one of the second components having less defect density requirements can be fabricated on the first gallium nitride layer 340. For example, a gallium nitride metal oxide semiconductor (MOS) capacitor 370 can be formed on the first gallium nitride layer 340. In the illustrated embodiment, MOS capacitor 370 can include an ohmic contact 372 formed over first gallium nitride layer 340, a high K dielectric 374, and a gate electrode 376. When the device contains PMIC or RF power amplification (Power Amplification; abbreviated as PA) circuitry, including a MOS capacitor 370 and a high voltage MOSFET may be particularly advantageous.

額外的實施例可包括在第一及第二氮化鎵層340/345上形成的各組件之任何組合。例如，第二氮化鎵層345可被用於RF PA中所需的組件，且第一氮化鎵層340可被用於氮化鎵RF開關裝置。將一RF開關設置在第一氮化鎵層340上可能是有利的，這是因為RF開關需要被妥善地隔離。因為是在第一STI層315之上形成第一氮化鎵層340，所以已有這些類型的組件所需之足夠隔離。 Additional embodiments may include any combination of components formed on the first and second gallium nitride layers 340/345. For example, the second gallium nitride layer 345 can be used for components required in RF PA, and the first gallium nitride layer 340 can be used for a gallium nitride RF switching device. It may be advantageous to have an RF switch disposed on the first gallium nitride layer 340 because the RF switches need to be properly isolated. Because the first gallium nitride layer 340 is formed over the first STI layer 315, there is sufficient isolation required for these types of components.

除了形成平面MOSFET裝置之外，本發明之實施例也可將該雙氮化鎵層結構用於形成非平面MOSFET裝置。將以與第4圖有關之方式示出且說明根據此種實施例的一裝置。 In addition to forming a planar MOSFET device, embodiments of the present invention can also be used to form a non-planar MOSFET device. A device according to such an embodiment will be shown and described in relation to Figure 4.

現在請參閱第4圖，示出將第二氮化鎵層445用於形成非平面MOSFET的一裝置之一透視圖。當以類似於前文中以與第2F圖有關之方式所述的結構之一導電層447取代該第二STI層時，可製造此類實施例。如圖所示，導電層447可充當一閘極電極，且提供一個雙閘極或環繞式閘極(Gate All Around；簡稱GAA)MOSFET裝置460。除了形成導電層447(圖中未示出的一閘極介電質可將導電層447與第二氮化鎵層445隔離)之外，非平面MOSFET裝置460可包含源極接點462及汲極接點464。該等源極接點462及汲極接點464的位置界定了一對通道468。例如，根據第二氮化鎵層445之尺寸，該等通道可 以是奈米帶(nano-ribbon)或奈米線(nano-wire)通道。可在第二氮化鎵層445的T頂面之上形成一第二導電層448(為了不模糊該圖而只示出一面)，以便充當非平面MOSFET 460的閘極電極之一部分。熟悉此項技術者當可了解：該組態可形成不需要對氮化鎵使用濕式蝕刻(wet etch)或任何蝕刻的奈米帶或奈米線結構。此種方式因將適於蝕刻氮化鎵系統的蝕刻劑化學品顯影的難度而是特別有利的。 Referring now to Figure 4, there is shown a perspective view of a device for forming a second gallium nitride layer 445 for forming a non-planar MOSFET. Such an embodiment can be fabricated when the second STI layer is replaced with a conductive layer 447 similar to that described above in the manner associated with FIG. 2F. As shown, conductive layer 447 can act as a gate electrode and provide a double gate or a Gate All Around (GAA) MOSFET device 460. In addition to forming a conductive layer 447 (a gate dielectric not shown may isolate the conductive layer 447 from the second gallium nitride layer 445), the non-planar MOSFET device 460 may include source contacts 462 and 汲Contact 464. The locations of the source contacts 462 and the drain contacts 464 define a pair of channels 468. For example, according to the size of the second gallium nitride layer 445, the channels may be It is a nano-ribbon or a nano-wire channel. A second conductive layer 448 (only one side is shown in order not to obscure the figure) may be formed over the top surface of the second gallium nitride layer 445 to serve as a portion of the gate electrode of the non-planar MOSFET 460. Those skilled in the art will appreciate that this configuration can form a nanobelt or nanowire structure that does not require wet etching or any etching of gallium nitride. This approach is particularly advantageous due to the difficulty of developing etchant chemicals suitable for etching gallium nitride systems.

除了主動及被動電組件之外，本發明之實施例也可將該第一及第二氮化鎵層形成的交叉點結構用於形成機械裝置。例如，機械裝置可被用於形成RF濾波應用之感測器等的組件。在一實施例中，該交叉點結構能夠形成可被用於RF濾波應用之一懸臂樑。將以與第5圖有關之方式示出且說明根據此種實施例的一裝置。 In addition to active and passive electrical components, embodiments of the present invention may also use the intersection structure formed by the first and second gallium nitride layers to form a mechanical device. For example, mechanical devices can be used to form components of sensors, etc. for RF filtering applications. In an embodiment, the cross-point structure is capable of forming a cantilever beam that can be used in RF filtering applications. A device according to such an embodiment will be shown and described in relation to Figure 5.

現在請參閱第5圖，根據本發明的一實施例而示出包含一懸臂樑530的一裝置之一透視圖。在一實施例中，可藉由將該第二STI層濕式蝕刻掉，而自第二氮化鎵層545形成懸臂樑530。然後可在該裝置的一部分周圍回填一導電層547。根據一實施例，可藉由調整第二氮化鎵層545的厚度及/或調整懸臂樑530的長度L，而控制懸臂樑530的共振頻率(resonant frequency)。 Referring now to Figure 5, a perspective view of a device including a cantilever beam 530 is shown in accordance with an embodiment of the present invention. In one embodiment, the cantilever beam 530 can be formed from the second gallium nitride layer 545 by wet etching the second STI layer. A conductive layer 547 can then be backfilled around a portion of the device. According to an embodiment, the resonant frequency of the cantilever beam 530 can be controlled by adjusting the thickness of the second gallium nitride layer 545 and/or adjusting the length L of the cantilever beam 530.

現在請參閱第6圖，示出可根據本發明的一實施例而形成的一基板600之一平面圖。根據一實施例，基板600可以是任何適當的結晶半導體基板600。在一特定實施例 中，該半導體基板是一塊狀矽或一絕緣層上覆矽基板600。在一實施例中，可在基板600之上形成複數個晶粒682。在一或多個晶粒682上，可以有係為矽之一第一部分684、以及包含在基板600之上形成的一III族氮化物層之一第二部分。在一實施例中，可利用包含諸如前文所述的那些交叉點溝槽設計等的一交叉點溝槽設計之一磊晶生長製程形成晶粒682的該III族氮化物部分。 Referring now to Figure 6, a plan view of a substrate 600 that can be formed in accordance with an embodiment of the present invention is shown. According to an embodiment, substrate 600 can be any suitable crystalline semiconductor substrate 600. In a particular embodiment The semiconductor substrate is a one-layered germanium or an insulating layer overlying the germanium substrate 600. In an embodiment, a plurality of dies 682 can be formed over the substrate 600. On one or more of the dies 682, there may be a first portion 684 that is a ruthenium and a second portion of one of the Ill-nitride layers formed over the substrate 600. In one embodiment, the III-nitride portion of the die 682 can be formed using one of the cross-dot trench designs including a cross-dot trench design such as those described above.

在相同晶粒上的一矽部分及一III族氮化物部分之整合可提高SoC裝置之性能。例如，每一晶粒682可包含諸如邏輯、記憶體、以及電源管理等的積體電路。如前文所述，該等基於III族氮化物之電晶體適用於諸如電源管理等的高電壓及高頻應用。因此，本發明之實施例包含：在III族氮化物區686上形成一或多個III族氮化物類型的電晶體，且一或多個邏輯互補金屬氧化物半導體(CMOS)可被包含在矽部分684上。 The integration of a germanium portion and a group III nitride portion on the same die can improve the performance of the SoC device. For example, each die 682 can include integrated circuitry such as logic, memory, and power management. As described above, these Group III nitride based transistors are suitable for high voltage and high frequency applications such as power management. Thus, embodiments of the invention include forming one or more III-nitride type transistors on a group III nitride region 686, and one or more logic complementary metal oxide semiconductors (CMOS) can be included in the germanium Part 684.

第7圖示出包含本發明的一或多個實施例之一轉接板700。轉接板700是被用於將一第一基板702橋接到一第二基板704的一中間基板。第一基板702可以是諸如一積體電路晶粒。第二基板704可以是諸如一記憶體模組、一電腦主機板、或另一積體電路晶粒。一般而言，轉接板700之用途在於使一連接伸展到一較寬的間距或使一連接重新佈線到一不同的連接。例如，一轉接板700可將一積體電路晶粒耦合到一銲球柵陣列(Ball Grid Array；簡稱BGA)706，而該BGA 706然後可被耦合到第二基板 704。在某些實施例中，第一及第二基板702/704被連接到轉接板700的相反面。在其他實施例中，第一及第二基板702/704被連接到轉接板700的相同面。且在進一步的實施例中，藉由利用轉接板700將三個或更多個基板互連。 Figure 7 shows an interposer 700 incorporating one or more embodiments of the present invention. The adapter plate 700 is an intermediate substrate that is used to bridge a first substrate 702 to a second substrate 704. The first substrate 702 can be, for example, an integrated circuit die. The second substrate 704 can be, for example, a memory module, a computer motherboard, or another integrated circuit die. In general, the purpose of the adapter plate 700 is to extend a connection to a wider spacing or to rewire a connection to a different connection. For example, an interposer 700 can couple an integrated circuit die to a Ball Grid Array (BGA) 706, which can then be coupled to a second substrate. 704. In some embodiments, the first and second substrates 702/704 are connected to opposite faces of the interposer board 700. In other embodiments, the first and second substrates 702/704 are connected to the same side of the interposer board 700. And in a further embodiment, three or more substrates are interconnected by utilizing an interposer board 700.

可由環氧樹脂、玻璃纖維強化環氧樹脂、陶瓷材料、或諸如聚醯亞胺等的聚合物材料形成轉接板700。在進一步的實施例中，可由諸如矽、鍺、以及其他的III-V族及IV族材料等的可包括與前文所述的用於半導體基板之相同材料等的替代的剛性或軟性材料形成該轉接板。 The adapter plate 700 may be formed of an epoxy resin, a glass fiber reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In a further embodiment, the rigid or soft material may comprise an alternative material such as tantalum, niobium, and other III-V and Group IV materials that may include the same materials and the like described above for the semiconductor substrate. Adapter plate.

該轉接板可包含一些金屬互連708、以及其中包括但不限於一些穿透矽通孔(Through-Silicon Via；簡稱TSV)712的一些通孔710。轉接板700可進一步包含嵌入式裝置714，其中包括被動及主動裝置。此類裝置包括但不限於電容器、去耦合電容器、電阻器、電感器、熔絲、二極體、變壓器、感測器、以及靜電放電(Electrostatic Discharge；簡稱ESD)裝置。亦可在轉接板700上形成諸如射頻(RF)裝置、功率放大器、電源管理裝置、天線、陣列、感測器、及微機電系統(MEMS)裝置等的更複雜的裝置。 The interposer may include some metal interconnects 708, and some vias 710 including, but not limited to, some Through-Silicon Via (TSV) 712. The interposer board 700 can further include an embedded device 714 including passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and Electrostatic Discharge (ESD) devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices can also be formed on the interposer board 700.

根據本發明之實施例，包含在一交叉點組態中形成的一或多個雙層氮化鎵結構之設備或用於形成本發明揭露的此類電晶體之製程可被用於轉接板700的製造。 In accordance with an embodiment of the present invention, a device comprising one or more bi-layered gallium nitride structures formed in a cross-point configuration or a process for forming such a transistor disclosed herein may be used for an interposer The manufacture of 700.

第8圖示出根據本發明的一實施例之一計算裝置 800。計算裝置800可包含一些組件。在一實施例中，這些組件被連接到一或多個主機板。在一替代實施例中，這些組件被製造到一單一系統單晶片(SoC)中，而不是被製造到一主機板上。計算裝置800中之該等組件包括但不限於一積體電路晶粒802以及至少一通訊晶片808。在某些實施例中，通訊晶片808被製造為積體電路晶粒802的一部分。積體電路晶粒802可包含一CPU 804、以及通常被用來作為快取記憶體之晶粒內置記憶體806，且可以諸如嵌入式動態隨機存取記憶體(embedded DRAM；簡稱eDRAM)或自旋轉移力矩記憶體(Spin-Transfer Torque Memory；簡稱STTM或STTM-RAM)等的技術提供該晶粒內置記憶體806。 Figure 8 shows a computing device in accordance with an embodiment of the present invention 800. Computing device 800 can include some components. In an embodiment, these components are connected to one or more motherboards. In an alternate embodiment, these components are fabricated into a single system, single-chip (SoC), rather than being fabricated onto a motherboard. The components in computing device 800 include, but are not limited to, an integrated circuit die 802 and at least one communication chip 808. In some embodiments, the communication chip 808 is fabricated as part of the integrated circuit die 802. The integrated circuit die 802 can include a CPU 804, and a die internal memory 806 that is typically used as a cache memory, and can be, for example, an embedded dynamic DRAM (eDRAM) or The die built-in memory 806 is provided by a technique such as a Spin-Transfer Torque Memory (STTM or STTM-RAM).

計算裝置800可包含可在或可不在實體上及電氣上被耦合到主機板的(或一SoC晶粒內製造的)其他組件。這些其他的組件包括但不限於揮發性記憶體810(例如，動態隨機存取記憶體(DRAM))、非揮發性記憶體812(例如，唯讀記憶體(ROM)或快閃記憶體)、一圖形處理單元(Graphics Processing Unit；簡稱GPU)814、一數位信號處理器816、一密碼處理器842(一種執行硬體內的密碼演算法之專用處理器)、一晶片組820、一天線822、一顯示器或一觸控式螢幕顯示器824、一觸控式螢幕控制器826、一電池828或或其他電源、一功率放大器(圖中未示出)、一全球衛星定位系統(Global Positioning System；簡稱GPS)裝置844、一羅盤830、 一移動共處理器或感測器832(可包括一加速度計(accelerometer)、一陀螺儀(gyroscope)、及一羅盤)、一喇叭834、一相機836、使用者輸入裝置838(例如，鍵盤、滑鼠、觸控筆、及觸控板)、以及一大量儲存裝置840(例如，硬碟機、光碟(Compact Disk；簡稱CD)、及數位多功能光碟(Digital Versatile Disk；簡稱DVD)等的大量儲存裝置)。 Computing device 800 can include other components that may or may not be physically and electrically coupled to a motherboard (or fabricated within a SoC die). These other components include, but are not limited to, volatile memory 810 (eg, dynamic random access memory (DRAM)), non-volatile memory 812 (eg, read only memory (ROM) or flash memory), a graphics processing unit (GPU) 814, a digital signal processor 816, a cryptographic processor 842 (a dedicated processor that executes a cryptographic algorithm in a hard body), a chipset 820, an antenna 822, a display or a touch screen display 824, a touch screen controller 826, a battery 828 or other power source, a power amplifier (not shown), a global positioning system (Global Positioning System; GPS) device 844, a compass 830, a mobile coprocessor or sensor 832 (which may include an accelerometer, a gyroscope, and a compass), a speaker 834, a camera 836, and a user input device 838 (eg, a keyboard, a mouse, a stylus, and a touchpad), and a mass storage device 840 (for example, a hard disk drive, a compact disk (CD), and a digital versatile disk (DVD). A large number of storage devices).

通訊晶片808能夠執行無線通訊，而將資料傳輸進出計算裝置800。術語"無線"及其派生詞可被用於描述可利用通過非固體介質之調變電磁輻射而傳送資料之電路、裝置、系統、方法、技術、通訊通道等的術語。該術語並不意味著相關聯的裝置不包含任何導線，但是在某些實施例中，該等相關聯的裝置可能不包含任何導線。通訊晶片808可實施其中包括但不限於Wi-Fi(IEEE 802.11系列)、WiMAX(IEEE 802.16系列)、IEEE 802.20、長期演進技術(Long Term Evolution；簡稱LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、藍牙(Bluetooth)、以上各項的衍生標準或協定、以及被稱為3G、4G、5G、及更新的世代之任何其他無線協定的一些無線標準或協定中之任何標準或協定。計算裝置800可包含複數個通訊晶片808。例如，一第一通訊晶片808可被專用於諸如Wi-Fi及藍牙等的較短距離之無線通訊，且一第二通訊晶片808可被專用於諸如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、 Ev-DO、及其他無線通訊標準等的較長距離之無線通訊。 The communication chip 808 is capable of performing wireless communication and transmitting data into and out of the computing device 800. The term "wireless" and its derivatives may be used to describe terms, circuits, systems, methods, techniques, communication channels, and the like that may utilize data transmitted by modulated electromagnetic radiation through a non-solid medium. The term does not mean that the associated device does not contain any wires, but in some embodiments, such associated devices may not contain any wires. The communication chip 808 can be implemented including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+ , EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivative standards or agreements for the above, and some wireless standards for any other wireless protocol known as 3G, 4G, 5G, and newer generations Or any standard or agreement in the agreement. Computing device 800 can include a plurality of communication chips 808. For example, a first communication chip 808 can be dedicated to short-range wireless communication such as Wi-Fi and Bluetooth, and a second communication chip 808 can be dedicated to applications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE. , Long-distance wireless communication such as Ev-DO and other wireless communication standards.

計算裝置800之處理器804包含諸如根據本發明的一實施例而在一交叉點組態中形成的雙層氮化鎵結構等的一或多個裝置。術語"處理器"可意指用於處理來自暫存器及/或記憶體的電子資料而將該電子資料轉換為可被儲存在暫存器及/或記憶體的其他電子資料之任何裝置或裝置的一部分。 Processor 804 of computing device 800 includes one or more devices, such as a two-layer gallium nitride structure formed in a cross-point configuration, in accordance with an embodiment of the present invention. The term "processor" may mean any device that processes electronic data from a register and/or memory and converts the electronic data into other electronic data that can be stored in a register and/or memory or Part of the device.

通訊晶片808亦可包含諸如根據本發明的一實施例而在一交叉點組態中形成的一或多個雙層氮化鎵結構等的一或多個裝置。 Communication die 808 may also include one or more devices, such as one or more bi-layered gallium nitride structures formed in a cross-point configuration in accordance with an embodiment of the present invention.

在進一步的實施例中，被安裝在計算裝置800內之另一組件可包含諸如根據本發明的一實施例而在一交叉點組態中形成的一或多個雙層氮化鎵結構等的一或多個裝置。 In a further embodiment, another component installed within computing device 800 can include one or more bi-layer GaN structures, such as formed in a cross-point configuration, in accordance with an embodiment of the present invention. One or more devices.

在各實施例中，計算裝置800可以是膝上型電腦、簡易筆記型電腦、筆記型電腦、超輕薄筆記本電腦、智慧型手機、平板電腦、個人數位助理(Personal Digital Assistant；簡稱PDA)、超級行動個人電腦、行動電話、桌上型電腦、伺服器、印表機、掃描器、監視器、機上盒、娛樂控制單元、數位相機、可攜式音樂播放器、或數位錄影機。在進一步的實施例中，計算裝置800可以是用於處理資料之任何其他電子裝置。 In various embodiments, the computing device 800 can be a laptop, a simple notebook, a notebook, an ultra-thin laptop, a smart phone, a tablet, a Personal Digital Assistant (PDA), a super Mobile PCs, mobile phones, desktops, servers, printers, scanners, monitors, set-top boxes, entertainment control units, digital cameras, portable music players, or digital video recorders. In a further embodiment, computing device 800 can be any other electronic device for processing data.

其中包括在"發明摘要"中所述者的前文中對本發明的所示實施例之說明之用意不是詳盡無遺的，也不是將本發明限制在所揭露之確切形式。雖然為了例示之目的而在本 說明書中說明了本發明的特定實施例及例子，但是如熟悉此項技術者將可了解的，可在本發明的範圍內作出各種等效的修改。 The description of the illustrated embodiments of the present invention is not intended to be exhaustive or to limit the invention. Although this is for the purpose of illustration Specific embodiments and examples of the invention are described in the specification, and various equivalent modifications can be made within the scope of the invention as will be apparent to those skilled in the art.

可根據上述之詳細說明而作出本發明的這些修改。不應將隨後申請專利範圍中使用的術語詮釋為將本發明限制在本說明書及申請專利範圍中揭露的特定實施例。而是將完全由將根據申請專利範圍詮釋的公認信條而詮釋之隨後申請專利範圍決定本發明之範圍。 These modifications of the invention can be made in light of the above detailed description. The terms used in the following claims are not to be construed as limiting the invention to the particular embodiments disclosed herein. Rather, the scope of the present invention will be determined by the scope of the subsequent patent application, which is fully interpreted by the accepted cre

本發明之實施例包含一種半導體結構，該半導體結構包含：具有一第一晶格常數(lattice constant)之一半導體基板；在半導體基板之上形成的一第一淺溝槽隔離(STI)層，其中通過該第一STI層而形成在一列中對齊的複數個第一溝槽；在該複數個第一溝槽中且在該第一STI層的一頂面之上形成的具有一第二晶格常數之一第一III族氮化物(III-N)層，其中該第一III族氮化物層跨越該複數個第一溝槽之間；在該第一III族氮化物層之上且在該第一STI層的該頂面之上形成的一第二STI層，其中通過該第二STI層而形成一第二溝槽，且其中該第二溝槽被定向成垂直於該列的第一溝槽；以及填滿該第二溝槽的一第二III族氮化物層。 Embodiments of the invention include a semiconductor structure comprising: a semiconductor substrate having a first lattice constant; a first shallow trench isolation (STI) layer formed over the semiconductor substrate, Forming, by the first STI layer, a plurality of first trenches aligned in a column; and forming a second crystal in the plurality of first trenches and formed on a top surface of the first STI layer a first group III nitride (III-N) layer, wherein the first group III nitride layer spans between the plurality of first trenches; above the first group III nitride layer a second STI layer formed on the top surface of the first STI layer, wherein a second trench is formed by the second STI layer, and wherein the second trench is oriented perpendicular to the column a trench; and a second Ill-nitride layer filling the second trench.

本發明之額外的實施例包含一半導體結構，其中該第一晶格常數及該第二晶格常數是不同的。 An additional embodiment of the invention includes a semiconductor structure in which the first lattice constant and the second lattice constant are different.

本發明之額外的實施例包含一半導體結構，其中該第一III族氮化物層包含位於該複數個第一溝槽的每一第一 溝槽中及正上方之一高缺陷密度部分、以及在該第一STI層的該頂面之上形成的一低缺陷密度部分。 An additional embodiment of the present invention includes a semiconductor structure wherein the first Ill-nitride layer comprises each of the first plurality of first trenches a high defect density portion in the trench and directly above, and a low defect density portion formed over the top surface of the first STI layer.

本發明之額外的實施例包含一半導體結構，其中以與該低缺陷密度部分接觸之方式形成該第二III族氮化物層。 An additional embodiment of the invention includes a semiconductor structure in which the second Ill-nitride layer is formed in contact with the low defect density portion.

本發明之額外的實施例包含一半導體結構，其中該半導體基板是一{111}晶向的矽基板，且該第一III族氮化物層是氮化鎵。 An additional embodiment of the present invention includes a semiconductor structure wherein the semiconductor substrate is a {111} crystal orientation germanium substrate and the first Ill-nitride layer is gallium nitride.

本發明之額外的實施例包含一半導體結構，其中沿著<110>方向對齊該列的第一溝槽。 An additional embodiment of the invention includes a semiconductor structure in which the first trenches of the column are aligned along the <110> direction.

本發明之額外的實施例包含一半導體結構，其中該第一III族氮化物層之一頂面是(0001)面，且該第一III族氮化物層之各小面是(101 0)面或(101 2)面。 An additional embodiment of the present invention includes a semiconductor structure in which a top surface of one of the first group III nitride layers is a (0001) plane, and each facet of the first group III nitride layer is a (101 0) plane Or (101 2) face.

本發明之額外的實施例包含一半導體結構，其中沿著<112>方向對齊該第二溝槽。 An additional embodiment of the invention includes a semiconductor structure in which the second trench is aligned along the <112> direction.

本發明之額外的實施例包含一半導體結構，其中在該第二III族氮化物層上形成一電晶體。 An additional embodiment of the invention includes a semiconductor structure in which a transistor is formed over the second Ill-nitride layer.

本發明之額外的實施例包含一半導體結構，其中該電晶體是一非平面電晶體。 An additional embodiment of the invention includes a semiconductor structure in which the transistor is a non-planar transistor.

本發明之額外的實施例包含一半導體結構，其中在該第一III族氮化物層上形成一組件。 An additional embodiment of the invention includes a semiconductor structure in which an assembly is formed on the first Ill-nitride layer.

本發明之額外的實施例包含一半導體結構，其中該組件是一金屬氧化物半導體電容。 An additional embodiment of the invention includes a semiconductor structure in which the component is a metal oxide semiconductor capacitor.

本發明之額外的實施例包含一半導體結構，其中該第 二III族氮化物層是一懸臂樑。 An additional embodiment of the invention includes a semiconductor structure in which the The second Ill-nitride layer is a cantilever beam.

本發明之實施例包含一種形成低缺陷密度半導體裝置之方法，該方法包含下列步驟：在一半導體基板之上形成一第一STI層，其中該第一STI層包含在一列中對齊的複數個第一溝槽；在該複數個第一溝槽中生長一第一III族氮化物層，其中該第一III族氮化物層橫向延伸到該第一STI層的一頂面之上，且其中該第一III族氮化物層跨越該複數個第一溝槽之間；在該第一STI層之上且在該第一III族氮化物層之上形成一第二STI層，其中通過該第二STI層而形成一溝槽，且該溝槽被定向成垂直於該列的第一溝槽，且其中不在一第一溝槽正上方形成該第二溝槽；以及在該第二溝槽中生長一第二III族氮化物層。 Embodiments of the invention include a method of forming a low defect density semiconductor device, the method comprising the steps of: forming a first STI layer over a semiconductor substrate, wherein the first STI layer comprises a plurality of aligned first columns a trench; a first group III nitride layer is grown in the plurality of first trenches, wherein the first group III nitride layer extends laterally over a top surface of the first STI layer, and wherein a first III-nitride layer spanning between the plurality of first trenches; a second STI layer over the first STI layer and over the first Ill-nitride layer, wherein the second STI layer is formed a trench is formed in the STI layer, and the trench is oriented perpendicular to the first trench of the column, and wherein the second trench is not formed directly over a first trench; and in the second trench A second Group III nitride layer is grown.

本發明之額外的實施例包含形成低缺陷密度半導體裝置之一方法，其中利用一MOCVD或MBE製程而以磊晶方式生長第一及第二III族氮化物層。 An additional embodiment of the present invention includes a method of forming a low defect density semiconductor device in which the first and second Ill-nitride layers are grown in an epitaxial manner using an MOCVD or MBE process.

本發明之額外的實施例包含形成低缺陷密度半導體裝置之一方法，其中該第一III族氮化物層中之位錯終止於該第二STI層之底面，且其中該第一III族氮化物層包含在該第一STI層的表面之上形成的低缺陷密度區、以及在該第一複數個溝槽中及正上方形成的高缺陷密度區。 An additional embodiment of the present invention includes a method of forming a low defect density semiconductor device, wherein dislocations in the first Ill-nitride layer terminate in a bottom surface of the second STI layer, and wherein the first III-nitride The layer includes a low defect density region formed over the surface of the first STI layer, and a high defect density region formed in and directly above the first plurality of trenches.

本發明之額外的實施例包含形成低缺陷密度半導體裝置之一方法，其中生長該第二III族氮化物層之該步驟包含下列步驟：只在該第一III族氮化物層的該等低缺陷密度區之上選擇性地生長該第二III族氮化物層。 An additional embodiment of the present invention includes a method of forming a low defect density semiconductor device, wherein the step of growing the second Ill-nitride layer comprises the step of: only such low defects in the first Ill-nitride layer The second Ill-nitride layer is selectively grown over the density region.

本發明之額外的實施例包含形成低缺陷密度半導體裝置之一方法，進一步包含下列步驟：移除該第二STI層。 An additional embodiment of the present invention includes a method of forming a low defect density semiconductor device, further comprising the step of removing the second STI layer.

本發明之額外的實施例包含形成低缺陷密度半導體裝置之一方法，進一步包含下列步驟：在該第二III族氮化物層周圍沈積一導電層；以及在該第二III族氮化物層上形成一非平面電晶體。 An additional embodiment of the present invention includes a method of forming a low defect density semiconductor device, further comprising the steps of: depositing a conductive layer around the second Ill-nitride layer; and forming on the second Ill-nitride layer A non-planar transistor.

本發明之額外的實施例包含形成低缺陷密度半導體裝置之一方法，其中該第二III族氮化物層的一部分以沒有來自下方的支承之方式延伸，而形成一懸臂樑。 An additional embodiment of the present invention includes a method of forming a low defect density semiconductor device wherein a portion of the second Ill-nitride layer extends without a support from below to form a cantilever beam.

本發明之額外的實施例包含形成低缺陷密度半導體裝置之一方法，其中該第一及第二III族氮化物層是氮化鎵。 An additional embodiment of the invention includes a method of forming a low defect density semiconductor device wherein the first and second Ill-nitride layers are gallium nitride.

本發明之實施例包含一種半導體結構，該半導體結構包含：具有一第一晶格常數之一半導體基板；在半導體基板之上形成的一第一淺溝槽隔離(STI)層，其中通過該第一STI層而形成在一列中對齊的複數個第一溝槽；在該複數個第一溝槽中且在該第一STI層的一頂面之上形成的具有不同於該第一晶格常數的一第二晶格常數之一第一氮化鎵層，其中該第一氮化鎵層跨越該複數個第一溝槽之間，且其中該第一氮化鎵包含位於該複數個第一溝槽的每一第一溝槽中及正上方之一高缺陷密度部分、以及在該第一STI層的該頂面之上形成之一低缺陷密度部分；在該第一氮化鎵層之上且在該第一STI層的該頂面之上形成的一第二STI層，其中通過該第二STI層而形成一第二溝槽， 且其中該第二溝槽被定向成垂直於該列的第一溝槽；以及填滿該第二溝槽的一第二氮化鎵層，其中以與該低缺陷密度部分接觸之方式形成該第二III族氮化物層。 Embodiments of the present invention comprise a semiconductor structure comprising: a semiconductor substrate having a first lattice constant; a first shallow trench isolation (STI) layer formed over the semiconductor substrate, wherein the first Forming, by an STI layer, a plurality of first trenches aligned in a column; forming a plurality of first lattices above the top surface of the first STI layer different from the first lattice constant a first gallium nitride layer, wherein the first gallium nitride layer spans between the plurality of first trenches, and wherein the first gallium nitride is included in the plurality of first a high defect density portion in and directly above each of the first trenches of the trench, and a low defect density portion over the top surface of the first STI layer; in the first gallium nitride layer a second STI layer formed over the top surface of the first STI layer, wherein a second trench is formed by the second STI layer, And wherein the second trench is oriented perpendicular to the first trench of the column; and a second gallium nitride layer filling the second trench, wherein the second trench is formed in contact with the low defect density portion A second Ill-nitride layer.

本發明之額外的實施例包含一半導體結構，其中該半導體基板是一{111}晶向的矽基板，其中沿著<110>方向對齊該列的第一溝槽，且其中沿著<112>方向對齊該第二溝槽。 An additional embodiment of the present invention includes a semiconductor structure wherein the semiconductor substrate is a {111} crystal orientation germanium substrate, wherein the first trench of the column is aligned along the <110> direction, and wherein <112> The direction is aligned with the second groove.

本發明之額外的實施例包含一半導體結構，其中在該第一氮化鎵層上形成一第一組件，且在該第二氮化鎵層上形成一第二組件。 An additional embodiment of the present invention includes a semiconductor structure in which a first component is formed on the first gallium nitride layer and a second component is formed on the second gallium nitride layer.

本發明之額外的實施例包含一半導體結構，其中該第二氮化鎵層是一懸臂樑。 An additional embodiment of the invention includes a semiconductor structure wherein the second gallium nitride layer is a cantilever beam.

100‧‧‧半導體基板 100‧‧‧Semiconductor substrate

115‧‧‧第一淺溝槽隔離層 115‧‧‧First shallow trench isolation

120、127‧‧‧溝槽 120, 127‧‧‧ trench

125‧‧‧第二淺溝槽隔離層 125‧‧‧Second shallow trench isolation

140‧‧‧第一氮化鎵層 140‧‧‧First GaN layer

142‧‧‧位錯缺陷 142‧‧‧Dislocation defects

145‧‧‧第二氮化鎵層 145‧‧‧Second gallium nitride layer

Claims (25)

一種半導體結構，包含：具有一第一晶格常數之一半導體基板；在該半導體基板之上形成的一第一淺溝槽隔離(STI)層，其中通過該第一STI層而形成在一列中對齊的複數個第一溝槽；在該複數個第一溝槽中且在該第一STI層的一頂面之上形成的具有一第二晶格常數之一第一III族氮化物(III-N)層，其中該第一III族氮化物層跨越該複數個第一溝槽之間；在該第一III族氮化物層之上且在該第一STI層的該頂面之上形成的一第二STI層，其中通過該第二STI層而形成一第二溝槽，且其中該第二溝槽被定向成垂直於該列的第一溝槽；以及填滿該第二溝槽的一第二III族氮化物層。 A semiconductor structure comprising: a semiconductor substrate having a first lattice constant; a first shallow trench isolation (STI) layer formed over the semiconductor substrate, wherein the first STI layer is formed in a column Aligning a plurality of first trenches; a first group III nitride having a second lattice constant formed in the plurality of first trenches and over a top surface of the first STI layer a layer of -N), wherein the first Ill-nitride layer spans between the plurality of first trenches; over the first Ill-nitride layer and over the top surface of the first STI layer a second STI layer, wherein a second trench is formed by the second STI layer, and wherein the second trench is oriented perpendicular to the first trench of the column; and filling the second trench a second group III nitride layer. 如申請專利範圍第1項之半導體結構，其中該第一晶格常數及該第二晶格常數是不同的。 The semiconductor structure of claim 1, wherein the first lattice constant and the second lattice constant are different. 如申請專利範圍第2項之半導體結構，其中該第一III族氮化物層包含位於該複數個第一溝槽的每一第一溝槽中及正上方之一高缺陷密度部分、以及在該第一STI層的該頂面之上形成的一低缺陷密度部分。 The semiconductor structure of claim 2, wherein the first group III nitride layer comprises a high defect density portion in and directly above each of the first trenches of the plurality of first trenches, and A low defect density portion formed over the top surface of the first STI layer. 如申請專利範圍第3項之半導體結構，其中以與該低缺陷密度部分接觸之方式形成該第二III族氮化物層。 The semiconductor structure of claim 3, wherein the second group III nitride layer is formed in contact with the low defect density portion. 如申請專利範圍第2項之半導體結構，其中該半導體基板是一{111}晶向的矽基板，且該第一III族氮化物層是氮化鎵(GaN)。 The semiconductor structure of claim 2, wherein the semiconductor substrate is a {111} crystal orientation germanium substrate, and the first group III nitride layer is gallium nitride (GaN). 如申請專利範圍第2項之半導體結構，其中沿著<110>方向對齊該列的第一溝槽。 The semiconductor structure of claim 2, wherein the first trench of the column is aligned along the <110> direction. 如申請專利範圍第6項之半導體結構，其中該第一III族氮化物層之一頂面是(0001)面，且該第一III族氮化物層之各小面是(101 0)面或(101 2)面。 The semiconductor structure of claim 6, wherein a top surface of one of the first group III nitride layers is a (0001) plane, and each of the facets of the first group III nitride layer is a (101 0) plane or (101 2) Face. 如申請專利範圍第6項之半導體結構，其中沿著<112>方向對齊該第二溝槽。 The semiconductor structure of claim 6, wherein the second trench is aligned along the <112> direction. 如申請專利範圍第1項之半導體結構，其中在該第二III族氮化物層上形成一電晶體。 The semiconductor structure of claim 1, wherein a transistor is formed on the second group III nitride layer. 如申請專利範圍第9項之半導體結構，其中該電晶體是一非平面電晶體。 The semiconductor structure of claim 9, wherein the transistor is a non-planar transistor. 如申請專利範圍第9項之半導體結構，其中在該第一III族氮化物層上形成一組件。 The semiconductor structure of claim 9, wherein an assembly is formed on the first group III nitride layer. 如申請專利範圍第11項之半導體結構，其中該組件是一金屬氧化物半導體電容。 The semiconductor structure of claim 11, wherein the component is a metal oxide semiconductor capacitor. 如申請專利範圍第1項之半導體結構，其中該第二III族氮化物層是一懸臂樑。 The semiconductor structure of claim 1, wherein the second group III nitride layer is a cantilever beam. 一種形成低缺陷密度半導體裝置之方法，包含：在一半導體基板之上形成一第一STI層，其中該第一STI層包含在一列中對齊的複數個第一溝槽；在該複數個第一溝槽中生長一第一III族氮化物層， 其中該第一III族氮化物層橫向延伸到該第一STI層的一頂面之上，且其中該第一III族氮化物層跨越該複數個第一溝槽之間；在該第一STI層之上且在該第一III族氮化物層之上形成一第二STI層，其中通過該第二STI層而形成一溝槽，且該溝槽被定向成垂直於該列的第一溝槽，且其中不在一第一溝槽正上方形成該第二溝槽；以及在該第二溝槽中生長一第二III族氮化物層。 A method of forming a low defect density semiconductor device, comprising: forming a first STI layer over a semiconductor substrate, wherein the first STI layer comprises a plurality of first trenches aligned in a column; A first group III nitride layer is grown in the trench, Wherein the first Ill-nitride layer extends laterally over a top surface of the first STI layer, and wherein the first Ill-nitride layer spans between the plurality of first trenches; at the first STI Forming a second STI layer over the layer and over the first group III nitride layer, wherein a trench is formed by the second STI layer, and the trench is oriented perpendicular to the first trench of the column a trench, and wherein the second trench is not formed directly over a first trench; and a second Ill-nitride layer is grown in the second trench. 如申請專利範圍第14項之方法，其中利用一金屬有機化學氣相沈積(MOCVD)或分子束磊晶(MBE)製程而以磊晶方式生長第一及第二III族氮化物層。 The method of claim 14, wherein the first and second group III nitride layers are grown in an epitaxial manner by a metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) process. 如申請專利範圍第14項之方法，其中該第一III族氮化物層中之位錯終止於該第二STI層之底面，且其中該第一III族氮化物層包含在該第一STI層的表面之上形成的低缺陷密度區、以及在該第一複數個溝槽中及正上方形成的高缺陷密度區。 The method of claim 14, wherein the dislocations in the first group III nitride layer terminate in a bottom surface of the second STI layer, and wherein the first group III nitride layer is included in the first STI layer A low defect density region formed over the surface, and a high defect density region formed in and directly above the first plurality of trenches. 如申請專利範圍第16項之方法，其中生長該第二III族氮化物層包含：只在該第一III族氮化物層的該等低缺陷密度區之上選擇性地生長該第二III族氮化物層。 The method of claim 16, wherein the growing the second group III nitride layer comprises: selectively growing the second group III above the low defect density regions of the first group III nitride layer. Nitride layer. 如申請專利範圍第14項之方法，進一步包含：移除該第二STI層。 The method of claim 14, further comprising: removing the second STI layer. 如申請專利範圍第18項之方法，進一步包含：在該第二III族氮化物層周圍沈積一導電層；以及 在該第二III族氮化物層上形成一非平面電晶體。 The method of claim 18, further comprising: depositing a conductive layer around the second Ill-nitride layer; A non-planar transistor is formed on the second Ill-nitride layer. 如申請專利範圍第18項之方法，其中該第二III族氮化物層的一部分以沒有來自下方的支承之方式延伸，而形成一懸臂樑。 The method of claim 18, wherein a portion of the second group III nitride layer extends without support from below to form a cantilever beam. 如申請專利範圍第14項之方法，其中該第一及第二III族氮化物層是氮化鎵。 The method of claim 14, wherein the first and second Ill-nitride layers are gallium nitride. 一種半導體結構，包含：具有一第一晶格常數之一半導體基板；在該半導體基板之上形成的一第一淺溝槽隔離(STI)層，其中通過該第一STI層而形成在一列中對齊的複數個第一溝槽；在該複數個第一溝槽中且在該第一STI層的一頂面之上形成的具有不同於該第一晶格常數的一第二晶格常數之一第一氮化鎵層，其中該第一氮化鎵層跨越該複數個第一溝槽之間，且其中該第一氮化鎵包含位於該複數個第一溝槽的每一第一溝槽中及正上方之一高缺陷密度部分、以及在該第一STI層的該頂面之上形成之一低缺陷密度部分；在該第一氮化鎵層之上且在該第一STI層的該頂面之上形成的一第二STI層，其中通過該第二STI層而形成一第二溝槽，且其中該第二溝槽被定向成垂直於該列的第一溝槽；以及填滿該第二溝槽的一第二氮化鎵層，其中以與該低缺陷密度部分接觸之方式形成該第二III族氮化物層。 A semiconductor structure comprising: a semiconductor substrate having a first lattice constant; a first shallow trench isolation (STI) layer formed over the semiconductor substrate, wherein the first STI layer is formed in a column Aligning a plurality of first trenches; forming a second lattice constant different from the first lattice constant in the plurality of first trenches and over a top surface of the first STI layer a first gallium nitride layer, wherein the first gallium nitride layer spans between the plurality of first trenches, and wherein the first gallium nitride comprises each first trench located in the plurality of first trenches a high defect density portion in the trench and directly above, and a low defect density portion over the top surface of the first STI layer; above the first gallium nitride layer and in the first STI layer a second STI layer formed over the top surface, wherein a second trench is formed by the second STI layer, and wherein the second trench is oriented perpendicular to the first trench of the column; Filling a second gallium nitride layer of the second trench, wherein the portion is in contact with the low defect density portion Into the second III-nitride layer. 如申請專利範圍第22項之半導體結構，其中該 半導體基板是一{111}晶向的矽基板，其中沿著<110>方向對齊該列的第一溝槽，且其中沿著<112>方向對齊該第二溝槽。 Such as the semiconductor structure of claim 22, wherein The semiconductor substrate is a {111} crystal orientation germanium substrate in which the first trench of the column is aligned along the <110> direction, and wherein the second trench is aligned along the <112> direction. 如申請專利範圍第22項之半導體結構，其中在該第一氮化鎵層上形成一第一組件，且在該第二氮化鎵層上形成一第二組件。 The semiconductor structure of claim 22, wherein a first component is formed on the first gallium nitride layer and a second component is formed on the second gallium nitride layer. 如申請專利範圍第22項之半導體結構，其中該第二氮化鎵層是一懸臂樑。 The semiconductor structure of claim 22, wherein the second gallium nitride layer is a cantilever beam.
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