CN104218938B - Programmable mixed signal input/output (IO) - Google Patents
Programmable mixed signal input/output (IO) Download PDFInfo
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- CN104218938B CN104218938B CN201410203172.9A CN201410203172A CN104218938B CN 104218938 B CN104218938 B CN 104218938B CN 201410203172 A CN201410203172 A CN 201410203172A CN 104218938 B CN104218938 B CN 104218938B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017581—Coupling arrangements; Interface arrangements programmable
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
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Abstract
It describes for providing the technology of highly integrated and configurable I/O port for integrated circuit, the I/O port can be disposed separately as the number or analog functuion for many general, such as the analog-digital converter (ADC) of multichannel, digital analog converter (DAC), multiplexer, GPIO, analog switch, switch and the multiplexer of multichannel, digital logic level converter, comparator, temperature sensor and repeater etc..The configuration of each port can be arranged by configuration register, and the configuration register for example can specify the function and voltage range of port, without influencing other ports.In embodiment, the logical mappings of port order sequence can be defined.It can also include data register, for handling microcontroller order, and store the transformation result for example from the port for being used as ADC input port.These abilities can be with the high voltage and high current combined ability of its multiregion to improve function.
Description
Cross reference to related applications
It is submitting and entitled on June 3rd, 2013 that the application is based on 35U.S.C. § 119 (e) requirement
The U.S. Provisional Application sequence NO.61/830,206's of " PROGRAMMABLE MIXED-SIGNAL INPUT/OUTPUT (IO) "
Equity, the provisional application are fully incorporated herein by reference.
Technical field
This disclosure relates to programmable mixed signal input/output (IO), and in particular, to for providing height for integrated circuit
The technology of integrated and configurable port input/output (IO), input/output (IO) port can be configured separately
For many general number or analog functuion.
Background technique
Integrated design circuit is an extremely complex and time-consuming process.Engineers devote a tremendous amount of time to configure
The framework of integrated circuit can make local running with for its intended purpose.Although for will mass production dedicated collection
For circuit (ASIC), this time, effort and cost are acceptable, but are designed for the collection of specific purposes sometimes
It is unpractiaca or uneconomic at circuit.For some applications, as a result, adapt to visitor to desired function
Family brings complicated and non-efficient scheme.
For example, it is extremely complex for being used to control with the integrated circuit of automation application, this is because they are capable of handling
A large amount of function.Such integrated circuit is widely used for communication, industrial automation and field of medical device.It is answered for these
Integrated circuit usually realize a large amount of port support multichannel analog-digital converter (ADC), multichannel digital-to-analogue conversion
Device (DAC), universal input/output equipment (GPIO), comparator, temperature sensor, multiplexer, repeater etc..As a result, this
A little integrated circuits may become quite huge.Therefore, many realizations use multiple integrated circuits rather than single integrated circuit,
In, each integrated circuit executes limited function collection.
Summary of the invention
It describes for providing the technology of highly integrated and configurable port input/output (IO) for integrated circuit,
Input/output (IO) port can be configured separately for many general number or analog functuion, such as the mould of multichannel
Number converter (ADC), the digital analog converter (DAC) of multichannel, multiplexer, universal input/output equipment (GPIO), simulation are opened
It closes, switch and multiplexer, digital logic level converter, comparator, temperature sensor and repeater etc..Configurable I/O
Being separately configured for port can be arranged by configuration register, the configuration register for example can specify port function and
Voltage range is without influencing other ports.In embodiment, the logical mappings of port order sequence can also be defined.May include
Data register stores the transformation result from the port for being used for example as ADC input port.These abilities can be with multiregion
High voltage and high current ability be combined to provide general function to integrated circuit.
The summary is provided just for the sake of introducing the theme that will be described comprehensively in specific embodiment and attached drawing.Accordingly
The summary should not be considered as description essential feature or be used to determine the scope of the claims by ground.
Detailed description of the invention
It is described with reference to specific embodiment.In the accompanying drawings, the number on the most left side of reference number identifies the reference
The digital attached drawing occurred for the first time.It is similar to the use instruction of same reference numbers in different instances in the specification and illustrated in the drawings
Or identical project.
Fig. 1 is the schematic diagram according to the integrated circuit of the exemplary realization of present disclosure.
Fig. 2 is the signal according to the ADC configuration port as single-ended ADC input terminal of the exemplary realization of present disclosure
Figure.
In the schematic shown in figure 3, according to the exemplary realization of present disclosure, two ports are configured for use as difference
ADC input terminal.
In the schematic diagram of Fig. 4 A and 4B, according to the exemplary realization of present disclosure, two ports are configured for use as
Pseudo-differential ADC input terminal.
In the schematic diagram of Fig. 5, according to the exemplary realization of present disclosure, a port is configured for use as simulating
DAC output end.
In the schematic diagram of Fig. 6, according to the exemplary realization of present disclosure, a port is configured for use as having
The simulation DAC output end of ADC readback function.
In the schematic diagram of Fig. 7, according to the exemplary realization of present disclosure, two ports are electric to GPIO and unidirectional logic
Flat transformation provides interruptive port.
The process of Fig. 8 shows the exemplary realization according to present disclosure to including I/O port in integrated circuits
The method configured.
The process of Fig. 9 shows the method for being used to operate integrated circuit according to the exemplary realization of present disclosure,
Permission configures each I/O port by using register.
Specific embodiment
It summarizes
IC design for automating and controlling is usually huge and complicated, this is because these are applied
Different functions is supported using a large amount of I/O port, for example, multiplexing, digital-to-analogue conversion etc..As a result, the product in these fields
Manufacturer receives chip huge or with the port not used sometimes.In addition, these manufacturers generally use multiple cores
Piece adapts to selected function.Subsequent method consumes more power compared with one single chip, and may be more difficult to be integrated into
In product.
Correspondingly, technology, integrated circuit and the method for providing highly integrated I/O port, the height collection are described
At I/O port can be disposed separately for analog input end, simulation output end, digital input end, digital output end and
General-use.On piece register can be used and carry out the function of selection port to which the configuration of port be arranged.Port is configurable,
To support general modulus function, the digital analog converter (DAC) of analog-digital converter (ACD), multichannel including multichannel, multiplexing
Device, GPIO, analog switch, switch and multiplexer, digital logic level converter, comparator, temperature sensor and repeater.
Example integrated circuit
Fig. 1 shows the integrated circuit 100 according to the embodiment of present disclosure.Although integrated circuit 100 can be used for
Or various purposes are configured for, but in embodiment, integrated circuit 100 is configured to include in being used in automation process
, it is for power supply heat management, for power amplification biasing etc. equipment in.
As shown, integrated circuit 100 includes port manager 102, is configured to configurable multiple ports.Example
Such as, port manager 102 be illustrated as to can a ports 104 in 20 (20) of separate configurations configure.Just for the sake of convenient
Purpose, by this 20 port-marks be port [0:19].Traditionally, each port will be referred to as port 01, port 02, end
Mouth 03 etc..Therefore, it is possible to any one port configuration be configured, without consider configured by port manager 102 its
The configuration of its port 104.For example, can be configured to port 01, without considering other remaining ports (for example, port 02, end
Mouthful 03, port 04 etc.) any one of 104 configuration.Although describing the configuration of a port in 20 (20), should manage
Solution, the quantity and configuration of port can desired use, customer Canonical etc. based on chip be changed.
Each port 104 can be used for the analog or digital function of many general.For example, port 01 can be used for independently of
The signal that any one of the other ports 104 configured by port manager 102 are carried, and send DAC output.By port
The remaining port 104 that manager 102 configures equally is configurable, without considering how port 01 is arranged.
Port 104 can be used for supporting general analog or digital function.For example, the end configured by port manager 102
Any one of mouth 104 can support DAC 106, without influencing to include any other port 104 in multiple ports 104
Whether transmitting DAC output or any other function can be set to.In this way, client (such as manufacturer) can be via
The function of port 104 is arranged in register, rather than has the fixed configurations applied due to IC design.This ability energy
Plate space is enough saved, the port (for example, compared with specification of client, by the port of bad configuration) etc. not used is eliminated.
With reference to Fig. 1, it can be used including the register in appropriate memory and the configuration of port 104 be set.Implementing
In example, register includes configuration register (such as individual character register) and data register.For example, configuration register is to port
Function and its voltage range are configured.For example, register port 104 can be configured with support include but is not limited to
Under function: analog-to-digital conversion, digital-to-analogue conversion, universal input end (GPI), general purpose outputs (GPO), multiplexer or comparator or
Person's analog switch.Illustrative voltage range includes positive and negative or bipolarity.Illustrative voltage range can be zero to ten volts
(0V to 10V), minus five Dao positive five volts (- 5V arrives+5V) and minus ten to zero volt (- 10V to 0V).Although the electricity of port 104
Pressure range and function can be set/reset, but in embodiment, these voltage ranges can be by client or similar user
It is configured.Thus, in initial power-on, port 104 is not configured (for example, being configured to high impedance status or height-
Z), so that when register is arranged in client, by configuration register device come to port assignment function and voltage range.Configuration deposit
The setting of device can be used software and be programmed.Although DAC 106 and ADC 108 are illustrated as being respectively provided with 12 (12) positions
Output end and the input terminal of 12 (12) positions (carry out temperature monitoring and other systems for use as the servo loops of 12 (12) positions
System function), it is also contemplated that other configurations.
In embodiment, multiple memorizers equipment can be used to save configuration register.Illustrative memory devices
Including d type flip flop, static random access memory (SRAM), other nonvolatile memories etc..This memory can integrate
In any structure on integrated circuit 100.
Voltage is arranged in data register, such as DAC 106 is driven at the voltage.For example, using configuration deposit
The voltage range of zero to ten volts (0-10V) in device is configured port 03, to support DAC 106.In operational process
In, DAC 106 drives port 03 based on the input from microcontroller with three and half volt (3.5V).In the example shown, micro-control
Voltage is arranged in device processed, and 106 output end of DAC passes through via microcontroller interface 110 and serial line interface sum number at the voltage
The voltage is written data register and driven by word control 112.Microcontroller can carry out this operation, such as to make
To use temperature sequencer 114 and one or more temperature sensors (being referred to as long-range and local temperature sensor 116)
Supervise a part of power supply heat management.
The purpose that the example of the above power supply heat management is merely to illustrate that is provided, and is not intended to limit shown in Fig. 1
Embodiment.It should be understood that in this embodiment, integrated circuit 100 is used as the slave of microcontroller.
Microcontroller interface 110 can be configured as with various configurations.Illustrative microcontroller interface 110 include but
It is not necessarily limited to: serial peripheral interface (SPI) or I2C interface (I squares of C) interface.Thus, in I2DAC106 is driven in C interface with 3.5V
In the example of moved end mouthful 03, the port SCL and SDA is used, and the port AD1 and AD0 is used for I2The address of C is to identify integrated electricity
The unique identification on road 100, such as in the case where multiple chips.On the contrary, for SPI interface, using CSB, DOUT, SCLK and
DIN executes write operation.
Configuration register can be used to carry out the mapping of logic to physics.For example, in physical port port 01, port 03
In the case where being configured to DAC configuration port with port 05, the virtual address of these ports can be arranged to DAC by register
1,2 and 3.This virtual addressing can be used during carrying out time sequencing to these ports.In this way, sequencer
Only proceed to port corresponding with the function of its positive sequencing.
DAC 106 and ADC 108 is communicably coupled to multiple ports 104.In embodiment, ADC 108 and DAC 106 are single
Solely it is coupled to by each port that port manager 102 configures and is coupled to serial line interface and digital control 112.Thus,
Each port is separately connected to DAC 106 and ADC 108.As shown, DAC 106 passes through for the single logical of each port
Letter route is coupled, and ADC 108 can be coupled by one or two route for each port, this is depended on
Configuration.
In embodiment, for the port configured by port manager 102, single DAC 106 and single ADC is realized
108.Allow to carry out signal using single DAC 106 and single ADC 108 time-multiplexed.In this way, port tube
Reason device 102 configuration of each port can be arranged by configuration register, and carry out it is time-multiplexed, with give port assignment
Flexibility is provided during function.
Reference signal is respectively coupled to DAC external reference 120, ADC internal reference 122 and ADC external reference 124.
Reference device 118 and DAC 106 can also be attached by the DAC internal reference from internal interface 128.Outside DAC
Individual port can be used with reference to 120, ADC internal reference 122 and ADC external reference 124 to be coupled, to transmit each letter
Number.In embodiment, thus it is possible to vary the voltage at DAC external reference end 120 and ADC external reference end 124, to adjust to by port tube
The voltage that the related port that reason device 102 configures is driven.
As shown in Figure 1, integrated circuit 100 includes for establishing scheduled current/voltage for internal reference 128
Main bias 126.DAC 106, Ref Mux 118 are coupled in internal reference 128, to refer to 120 and ADC internal reference 122 for DAC
Establish current/voltage.
As shown, integrated circuit 100 further includes clock generator 130.Clock generator 130 is used as entire integrated circuit
100 clock source.
As shown, ADC sequencer 132 includes between ADC 108 and the port configured by port manager 102.ADC
Sequencer 132 is to the port with ADC function (for example, the purpose being merely to illustrate that, physical port port 01, port 03
With port 05) carry out sequencing.ADC sequencer 132 can execute this sequencing with various ways.For example, ADC sequencer 132
It can dispatch and be converted from lowest virtual address to the ADC of highest virtual address, and corresponding data register is written into transformation result
Device.Then, ADC sequencer 132 stops.In another mode, ADC sequencer 132 can execute Infinite Cyclic, described unlimited
In circulation, conversion is indefinitely carried out around ADC configuration port and recycles transformation result write-in data register.
In other modes, ADC sequencer 132 can carry out multiple conversions to port, and then average transformation result is written
To corresponding data register.For example, ADC sequencer 132 can be configured as carries out eight ADC conversions at port 01,
It carries out three times at port 03, and is carried out twice at port 05, and for each of these ports report, will be averaged
Value write-in data register.
As shown in the embodiment of figure 1, DAC sequencer 134 is included between DAC 106 and port manager 102, with
Sequencing is carried out for coming to export DAC in a time multiplexed fashion.In this way, can be arranged according to register will be different
Output is distributed to port 104.Thus, the configuration of each port independently of other ports configuration, this is because its signal is base
In time-multiplexed, rather than defined by physical structure.In embodiment, DAC sequencer 134 is in a manner of time control to output
Sequencing is carried out, to allow to share single DAC 106.For example, being carried out using tracking and saving function to port value
Setting saves the port value until the port is by sequencing again with the voltage.
In the embodiment that integrated circuit is configured for heat monitoring and control, temperature sequencer 114 and one or more
A temperature sensor (being referred to as 116) may include in integrated circuit 100.The expression of temperature sensor 116 can be used for monitoring
Temperature is to prevent the sensor of power supply or other overheating components.Each sensor can be on piece sensor, or pass through port
It is coupled for remote sense.In this configuration, integrated circuit may be used as servo loops to carry out temperature management.
As shown in Figure 1, port manager 102 further includes for GPIO port in port manager 102 and string
Communication line between line interface and digital control 112.It is as shown, conducting wire include 20 it is general enter communication lines and
20 general outgoing communication lines, to allow any one port to be used as general input terminal or output end.It should be understood that
, the quantity of conducting wire can be changed based on the quantity of the port configured by port manager 102.
Also show disrupted circuit 136.When some event occurs in the chips (for example, temperature reaches the temperature of setting
On or port be overcurrent), use interruption.In this example, interruptive port can be changed, such as be changed from 1
To 0, then it is placed into interrupt register.Microcontroller can check interrupt register and parse the event.In can be used
Disconnected mask shields or hides occurring but do not need the event that microcontroller pays attention to.
It continues to refer to figure 1, integrated circuit 100 further includes bias generator 138, is coupled to port manager 102.Bias
138 pairs of each ports configured by port manager 102 of generator carry out bias, to establish stable offset electricity for each port
Pressure.
Fig. 2 generally illustrates embodiment 200, and in embodiment 200, ADC configures port and is used as single-ended ADC input terminal.
The embodiment 200 of Fig. 2 includes the adjustment selection of the exemplary voltage range and adjustment block of the port.It can change in user outer
When portion refers to, such as using external reference port, internal reference is arranged to 2.5V, such as ADC_INT_REF is 2.5V.Institute
In the example shown, which may be used as going to the analog input end of single-ended ADC.The port is able to use internal or external reference
Voltage realizes various input ranges.It, can be via SPI or I such as the embodiment of Fig. 12C interface couples microcontroller.
Fig. 3 generally illustrates embodiment 300, and in embodiment 300, it is defeated that two ports are configured for use as difference ADC
Enter end.Although referring to port 1 and 2, any two port can be configured to provide this function.The port
It can be realized a variety of input ranges, and select internal or external reference voltage.It, can be via SPI or I such as the embodiment of Fig. 12C
Interface couples microcontroller.
Fig. 4 A and 4B generally illustrate embodiment 400, and in embodiment 400, two ports are configured for use as artifact
Divide ADC input terminal.Although referring to port 1 and 2, can be configured by port manager (such as port manager 102)
Any two port, which can be configured as, provides this function.The port is able to use internal or external reference voltage to realize
A variety of input ranges.ADC input terminal can share public DC bias point.It can be via SPI or I2C interface couples microcontroller
Device.
Fig. 5 generally illustrates embodiment 500, and in embodiment 500, it is defeated that a port is configured for use as simulation DAC
Outlet.DAC can for example drive port with 25mA, and limit current to as 50mA.The port can be configured as
Three ranges (such as 0V to 10V, -5V to+5V or -10V to 0V) in run.
Fig. 6 generally illustrates embodiment 600, and in embodiment 600, a port is configured for use as returning with ADC
Read the simulation DAC output end of function.In an illustrated embodiment, DAC and ADC can be set to identical reference voltage.It can
To use this configuration to provide calibration and alignment via ADC.
Fig. 7 generally illustrates embodiment 700, and in embodiment 700, two ports become to GPIO and unidirectional logic level
Offer interruptive port is provided.It can be run with this configuration by any two port that port manager configures.As shown,
In embodiment, GPI can undergo the lag of ± 30mV.It can be compiled by threshold voltage of the microcontroller to GPI input terminal
Journey.GPO has the current limit of 50mA, and can be programmed by microcontroller to 1 level of logic caused by GPO.
Clock control is not carried out to this function, and GPO function can substantially change immediately with the movable variation of GPI.
GPO output end and GPO input terminal can also be in turn.
Although can be based on it should be understood that describing integrated circuit 100 with certain specific degree
Selected specific implementation carries out various changes or modification.Although for example, integrated circuit 100 is described as slave,
It to a certain extent can include in integrated circuits, to provide autonomy to a certain degree by function in other embodiments.This theory
Being intended that for bright book covers and includes such modification.Although describing various embodiments, it should be appreciated that, Qi Tapei
It is also possible for setting.For example, two ports may be configured to bi-directional logic level converter.In this embodiment, two phases
Adjacent port is used as the bi-directional logic level converter of any open-drain logical drive.In this embodiment, external pull-up resistor
Device and external logic power supply should be provided by user.Clock control is not carried out to this function, so appointing in two ports
What one substantially can immediately drag down another port.
Illustrative methods
The method that above system, technology, method, framework and module are realized that can be used is described below.In these methods
The scheme of each can be realized with hardware, firmware or software or a combination thereof.The method is illustrated as specified performed
Operation one group of box, and the sequence of the operation is executed shown in being not necessarily limited to by corresponding square.Discussed below
It, will be with reference to the integrated circuit 100 in Fig. 1 described above in multiple portions.
Fig. 8 is shown to the method 800 configured including I/O port in integrated circuits.In embodiment, port
It can be configured, the configuration without considering other ports.Thus, the general analog or digital function of each port is not limited to
Specific port configuration.
As shown, establish register (box 802).For example, establishing configuration register in memory, held with saving
The configuration or personality data of the port of mouth manager configuration.Configuration data may include the function, logical address, voltage model of port
Enclose etc..In an illustrated embodiment, it establishes register and is included in volatile memory and establish data register, such as to protect
Reading and DAC output end voltage associated with DAC configuration output port from ADC configuration port is deposited to be arranged.
It provides ADC and DAC sequencer (box 804).In embodiment, ADC and DAC sequencer is directed to by port manager
The port of configuration and support single DAC and single ADC.DAC and ADC sequencer allows single DAC and single ADC pairs
The each carry out in I/O port configured by port manager is time-multiplexed.
Write-in configuration register (box 806) is arranged in configuration.For example, can function to port and voltage range carry out
Configuration.In this way, port can be by client or other user configurations.The above configuration can be in the mistake configured to port
Hoisting depth is integrated in journey and flexibility.
Fig. 9 shows the method operated to integrated circuit (integrated circuit for example including configuration and data register)
900, the integrated circuit, which is constructed to permit by using register, configures each input/output end port.In this way,
Client can customize port based on the specification of client.This can be minimized the size of the plate of integrated circuit, avoid using multiple
Integrated circuit simultaneously minimizes the port not used.
As shown, the function and voltage range (box 902) of port are set in configuration register.Software can be used
General simulation numeral function and voltage are divided into and are arranged into memory.
ADC transformation result is written to data register (box 904).For example, ADC sequencer can match to from ADC
The input voltage for setting port is converted, and data register is written in transformation result.For example, microcontroller can issue via
Serial line interface and the digital control order transmitted, the DAC output end DAC code of particular port is written.Then, DAC will be defeated
The DAC code is arrived in outlet driving.
It updates data register (box 906).It can be based on microcontroller order (such as report temperature sensing operation
Local or Remote temperature) come update including in data register value or ADC sequencer can be by the Change-over knot of ADC
Data register is written in fruit.Therefore, it is possible to based on ADC and GPI reading and for the microcontroller order of the port DAC and GPO
To update register.
Conclusion
Although with the language description operated specific to structure feature and/or process theme it should be appreciated that
It is that subject matter defined in the appended claims is not necessarily limited to above-mentioned specific feature or movement.On the contrary, above-mentioned special characteristic and
Movement is carried out disclosed as the exemplary form for realizing claim.
Claims (20)
1. a kind of IDE, comprising:
Multiple ports, each port in the multiple port, which is based on the setting of on piece register, can be configured as input terminal or defeated
Outlet comes at least one of transmitting digital signals or analog signal；
Single analog-digital converter is time-multiplexed the multiple port；And
Single digital analog converter is time-multiplexed the multiple port.
2. IDE as described in claim 1, wherein each port in the multiple port is can be separately configured
's.
3. IDE as described in claim 1, wherein each port in the multiple port can be used as simulating
At least one of input terminal, simulation output end, digital input end or digital output end.
4. IDE as described in claim 1, further includes:
It is configured as the memory of storage configuration register, the configuration register is configured to storage port configuration setting and electricity
Press range.
5. IDE as claimed in claim 4, further includes:
The data register being stored in volatile memory, for storing DAC code associated with corresponding port.
6. IDE as claimed in claim 4, wherein each port in the multiple port can be separately configured for
Receive voltage range.
7. IDE as described in claim 1, wherein each port in the multiple port is configured for leading to
Analog functuion or digital function.
8. a kind of IDE, comprising:
Port manager configures multiple ports for configuration to be configured or exported with input, every in the multiple port
A port can be separately configured to support digital signal or analog signal；
Single analog-digital converter is communicably coupled to the multiple port by analog-digital converter sequencer；
Single digital analog converter is communicably coupled to the multiple port by digital analog converter sequencer；And
Including the memory in the integrated circuit, it is used for storage register, the register to be configured to receive user couple
The selection that sequence used at least one of the analog-digital converter sequencer or the digital analog converter sequencer carries out.
9. IDE as claimed in claim 8, wherein the single analog-digital converter and the single digital-to-analogue
Converter is the only analog-digital converter and only digital analog converter for being communicably coupled to port respectively.
10. IDE as claimed in claim 8, wherein each port in the multiple port can be configured to use
Make general analog functuion or digital function.
11. IDE as claimed in claim 10, wherein general analog functuion or digital function is in following
At least one: the analog-digital converter (ADC) of multichannel, the digital analog converter (DAC) of multichannel, multiplexer, GPIO, simulation are opened
Pass, switch and multiplexer, digital logic level converter, comparator, temperature sensor and repeater.
12. IDE as claimed in claim 8, further includes:
Be configured to contain the volatile memory of data register, the data register be configured to comprising with it is the multiple
The associated ADC transformation result in each port in port.
13. IDE as claimed in claim 8, wherein each port in the multiple port is initially set
For in high impedance mode (High-Z).
14. a kind of IDE, comprising:
Port manager configures multiple ports for configuration to be configured or exported with input, every in the multiple port
A port can be separately configured to support digital signal or analog signal；
Analog-digital converter is communicably coupled to the multiple port by analog-digital converter sequencer；
Digital analog converter is communicably coupled to the multiple port by digital analog converter sequencer；And
Including the memory in the integrated circuit, it is used for storage register, the register to be configured to receive user couple
The selection that sequence used at least one of the analog-digital converter sequencer or the digital analog converter sequencer carries out.
15. IDE as claimed in claim 14, wherein each port in the multiple port is individually to match
It sets.
16. IDE as claimed in claim 14, wherein each port in the multiple port can be used as mould
At least one of quasi- input terminal, simulation output end, digital input end or digital output end.
17. IDE as claimed in claim 14, wherein the register includes configuration register, the configuration
Register is configured to storage port configuration setting and voltage range.
18. IDE as claimed in claim 17, wherein the register further includes data register, the number
According to register for storing transformation result associated with corresponding port.
19. IDE as claimed in claim 18, wherein each port in the multiple port can be separately configured
To receive voltage range.
20. IDE as claimed in claim 14, wherein each port in the multiple port is configured for
General analog functuion or digital function.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201361830206P | 2013-06-03 | 2013-06-03 | |
| US61/830,206 | 2013-06-03 | ||
| US14/190,311 | 2014-02-26 | ||
| US14/190,311 US9148147B2 (en) | 2013-06-03 | 2014-02-26 | Programmable mixed-signal input/output (IO) |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104218938A CN104218938A (en) | 2014-12-17 |
| CN104218938B true CN104218938B (en) | 2019-03-12 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410203172.9A Active CN104218938B (en) | 2013-06-03 | 2014-05-14 | Programmable mixed signal input/output (IO) |
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| Country | Link |
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| US (2) | US9148147B2 (en) |
| CN (1) | CN104218938B (en) |
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| US20140354328A1 (en) | 2014-12-04 |
| US9525420B2 (en) | 2016-12-20 |
| US9148147B2 (en) | 2015-09-29 |
| US20160020770A1 (en) | 2016-01-21 |
| CN104218938A (en) | 2014-12-17 |
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