CN104218016A - IC (integrated circuit) carrier board and semiconductor device with same - Google Patents
IC (integrated circuit) carrier board and semiconductor device with same Download PDFInfo
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- CN104218016A CN104218016A CN201310217967.0A CN201310217967A CN104218016A CN 104218016 A CN104218016 A CN 104218016A CN 201310217967 A CN201310217967 A CN 201310217967A CN 104218016 A CN104218016 A CN 104218016A
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- Prior art keywords
- substrate
- circuit substrate
- electric connection
- connection pad
- sandwich layer
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
Abstract
The invention relates to an IC (integrated circuit) carrier board comprising a circuit carrier board and a first intermediate board. The circuit carrier board comprises a core circuit substrate and a first laminated circuit substrate. The first laminated circuit substrate is laminated on one side of the core circuit substrate and is provided with a first opening penetrating the first laminated circuit substrate and allowing exposure of part of the core circuit substrate. The exposed part of the core circuit substrate is provided with a plurality of first electrical contact pads. The first intermediate board is arranged in the first opening. The first intermediate board comprises a first glass substrate provided with a plurality of conducting holes and first and second electrical connection pads exposed from two opposing sides of the first glass substrate. Each electric electrical connection pad is electrically connected with one second electrical connection pad through one conducting hole of the first glass substrate. Each first electrical connection pad is electrically connected with one first electrical contact pad through one first conducting member. The second electrical connection pads are used for electrically connecting an external chip. The invention further relates to a semiconductor device with the IC carrier board.
Description
Technical field
The present invention relates to a kind of IC support plate and there is the semiconductor device of this IC support plate.
Background technology
Existing chip bearing substrate comprises one or more layers dielectric base and is formed at the conductive circuit layer of this dielectric base side or relative both sides.Growing along with chip technology, the line pitch in chip is more and more thinner, and the spacing of the conducting wire in the chip bearing substrate of carries chips is also required more and more thinner, cause the manufacture difficulty of chip bearing substrate increasing, manufacturing cost increases.
Summary of the invention
In view of this, a kind of IC support plate overcoming the problems referred to above and the semiconductor device with this IC support plate is provided to be necessary.
A kind of IC support plate, it comprises circuit board and the first intermediate plate.Described circuit board comprises the sandwich layer circuit substrate being formed with conducting wire and the first laminated circuit substrate being formed with conducting wire.Described ground floor volt circuit substrate layer is pressed on described sandwich layer circuit substrate side.Described first laminated circuit substrate has the first perforate.Described first perforate runs through described first laminated circuit substrate, with sandwich layer circuit substrate described in exposed portion.Described sandwich layer circuit substrate has multiple first electric contact mats exposed from described first perforate.Described first intermediate plate is contained in described first perforate completely, and is electrically connected with described circuit board.Described first intermediate plate comprises first substrate of glass being formed with multiple conductive hole and is exposed to described first substrate of glass relative to multiple first electric connection pad of both sides and multiple second electric connection pad.Each described first electric connection pad is all electrically connected by a conductive hole in described first substrate of glass and described second electric connection pad.Each described first electric connection pad is all electrical connected by first conductive member and first electric contact mat.Described multiple second electric connection pad is in order to be electrically connected external chip.
A kind of semiconductor device, it comprises IC support plate and the first chip.Described IC support plate comprises circuit board and the first intermediate plate.Described circuit board comprises the sandwich layer circuit substrate being formed with conducting wire and the first laminated circuit substrate being formed with conducting wire.Described ground floor volt circuit substrate layer is pressed on described sandwich layer circuit substrate side.Described first laminated circuit substrate has the first perforate.Described first perforate runs through described first laminated circuit substrate, with sandwich layer circuit substrate described in exposed portion.Described sandwich layer circuit substrate has multiple first electric contact mats exposed from described first perforate.Described first intermediate plate is positioned in described first perforate, and is electrically connected with described circuit board.Described first intermediate plate comprises first substrate of glass being formed with multiple conductive hole and is exposed to described first substrate of glass relative to multiple first electric connection pad of both sides and multiple second electric connection pad.Each described first electric connection pad is all electrically connected by a conductive hole in described first substrate of glass and described second electric connection pad.Each described first electric connection pad is all electrical connected by first conductive member and first electric contact mat.Described first chip packaging at described first intermediate plate away from described sandwich layer circuit substrate side, and described first chip and being contained in completely in described first perforate with the first intermediate plate of its electric connection.
IC support plate in the present invention utilizes the first intermediate plate as the connection medium of circuit board and external chip.Making material due to the first intermediate plate is glass, it can make the ultra fine-line that live width line-spacing (that is: the distance between the width/wire of wire) is less than 5/5 micron, therefore general circuit board is made can to adapt to the live width line-spacing of chip, and the cost of the first intermediate plate is lower, the cost of whole IC support plate is reduced.In addition, the semiconductor device in the present invention is contained in described perforate completely due to intermediate plate and with the chip of its electric connection, makes can accommodate more chip in IC support plate of the same area, and whole semiconductor device can be made thinning.
Accompanying drawing explanation
Fig. 1 is the profile of the semiconductor device that first embodiment of the invention provides.
Fig. 2 is the profile of the semiconductor device that second embodiment of the invention provides.
Main element symbol description
| Semiconductor device | 100，200 |
| IC support plate | 10，20 |
| First chip | 18 |
| Second chip | 19 |
| Circuit board | 11，21 |
| First intermediate plate | 12，22 |
| Second intermediate plate | 13，23 |
| Sandwich layer circuit substrate | 111，211 |
| First laminated circuit substrate | 112，212 |
| Second laminated circuit substrate | 113，213 |
| First substrate | 1111，2111 |
| Second substrate | 1121，221 |
| 3rd substrate | 1131，231 |
| At the bottom of first subbase | 2011 |
| At the bottom of second subbase | 2021 |
| First substrate of glass | 121 |
| Second substrate of glass | 131 |
| First conductive circuit pattern | 1112，2112 |
| Second conductive circuit pattern | 1113，2113 |
| 3rd conductive circuit pattern | 1122，2122 |
| 4th conductive circuit pattern | 1132，2132 |
| First electronic conduction line pattern | 2012 |
| Second electronic conduction line pattern | 2013 |
| 3rd electronic conduction line pattern | 2022 |
| 4th electronic conduction line pattern | 2023 |
| First electric contact mat | 1126，2024 |
| Second electric contact mat | 1136，2025 |
| First electric connection pad | 122 |
| Second electric connection pad | 123 |
| 3rd electric connection pad | 132 |
| 4th electric connection pad | 133 |
| First perforate | 1123，2123 |
| Second perforate | 1133，2133 |
| First groove | 1124，2124 |
| Second groove | 1134，2134 |
| First welding resisting layer | 1125 |
| Second welding resisting layer | 1135 |
| Sub-sandwich layer substrate | 201 |
| 3rd intermediate plate | 202 |
| Collecting through hole | 2014 |
| Conductive hole | 2026 |
| First conductive hole | 124 |
| Second conductive hole | 134 |
| First conductive member | 14 |
| Second conductive member | 15 |
| 3rd conductive member | 16 |
| 4th conductive member | 17 |
| First conducting wire | 125 |
| Second conducting wire | 135 |
| First active surface | 181 |
| Second active surface | 191 |
| First non-active | 182 |
| Second non-active | 192 |
| First electronic pads | 183 |
| Second electronic pads | 193 |
Following embodiment will further illustrate the present invention in conjunction with above-mentioned accompanying drawing.
Embodiment
Below, multiple embodiment explains IC support plate of the present invention structure in conjunction with above-mentioned accompanying drawing is enumerated.
Refer to Fig. 1, the semiconductor device 100 that the technical program first embodiment provides comprises IC support plate 10, first chip 18 and the second chip 19.
Described IC support plate 10 comprises circuit board 11, first intermediate plate 12 and the second intermediate plate 13.
Described circuit board 11 comprises sandwich layer circuit substrate 111, first laminated circuit substrate 112 and the second laminated circuit substrate 113.
Described sandwich layer circuit substrate 111 is for being formed with double-sided PCB or the multilayer circuit board of conducting wire, and it comprises the first substrate 1111 and is formed at the first conductive circuit pattern 1112 and the second conductive circuit pattern 1113 of the relative both sides of the first substrate 1111.In the present embodiment, described sandwich layer circuit substrate 111 is four-layer circuit board, has two-layer conductive circuit pattern in described first substrate 1111.Be electrically connected between described sandwich layer circuit substrate 111 each layers of conductive circuit pattern.
Described first laminated circuit substrate 112 is laminated to the first conductive circuit pattern 1112 side of described sandwich layer circuit substrate 111.Described first laminated circuit substrate 112 can be the single-sided circuit board or multilayer circuit board that are formed with conducting wire, and it comprises the second substrate 1121 and is formed at three conductive circuit pattern 1122 of described second substrate 1121 away from described first conductive circuit pattern 1112 side.In the present embodiment, described first laminated circuit substrate 112 is two-tier circuit plate, has one deck conductive circuit pattern in described second substrate 1121.Described 3rd conductive circuit pattern 1122 is electrically connected by the conductive hole in described second substrate 1121 and described first conductive circuit pattern 1112.Described first laminated circuit substrate 112 has the first perforate 1123 running through described first laminated circuit substrate 112 in a thickness direction, with the first conductive circuit pattern 1112 described in exposed portion.Described first laminated circuit substrate 112 with the first perforate 1123 coordinates formation first groove 1124 jointly with described sandwich layer circuit substrate 111.
The surface of described first conductive circuit pattern 1112 of part that described first perforate 1123 is exposed and gap are coated with the first welding resisting layer 1125, and be formed with multiple open region in described first welding resisting layer 1125, be the first electric contact mat 1126 with described first conductive circuit pattern 1112 of the part that the open region defining described first welding resisting layer 1125 is exposed.So, described sandwich layer circuit substrate 111 has multiple first electric contact mats 1126 exposed from described first perforate 1123.
Described second laminated circuit substrate 113 is laminated to the second conductive circuit pattern 1113 side of described sandwich layer circuit substrate 111.Described second laminated circuit substrate 113 can be the single-sided circuit board or multilayer circuit board that are formed with conducting wire, and it comprises the 3rd substrate 1131 and is formed at four conductive circuit pattern 1132 of described 3rd substrate 1131 away from described second conductive circuit pattern 1113 side.In the present embodiment, described second laminated circuit substrate 113 is two-tier circuit plate, has one deck conductive circuit pattern in described 3rd substrate 1131.Described 4th conductive circuit pattern 1132 is electrically connected by the conductive hole in described 3rd substrate 1131 and described second conductive circuit pattern 1113.Described second laminated circuit substrate 113 has the second perforate 1133 running through described second laminated circuit substrate 113 in a thickness direction, the second conductive circuit pattern 1113 described in exposed portion.Described second laminated circuit substrate 113 with the second perforate 1133 coordinates formation second groove 1134 jointly with described sandwich layer circuit substrate 111.
The surface of described second conductive circuit pattern 1113 of part that described second perforate 1133 is exposed and gap are coated with the second welding resisting layer 1135, and be formed with multiple open region in described second welding resisting layer 1135, be the second electric contact mat 1136 with described second conductive circuit pattern 1113 of the part that the open region defining described second welding resisting layer 1135 is exposed.So, described sandwich layer circuit substrate 111 has multiple second electric contact mats 1136 exposed from described second perforate 1133.
Described first intermediate plate 12 is positioned in described first groove 1124, and is electrically connected with described circuit board 11.Described first intermediate plate 12 comprises the first substrate of glass 121 of being formed with multiple first conductive hole 124 and many first conducting wires 125 and is exposed to described first substrate of glass 121 multiple first electric connection pad 122 of both sides and multiple second electric connection pad 123 relatively.Described multiple first electric connection pad 122 is electrically connected with multiple described first electric contact mat 1126 one by one respectively by first conductive member 14.Described first conductive member 14 is metal column or soldered ball.In the present embodiment, described first conductive member 14 is soldered ball.Described multiple second electric connection pad 123 is in order to be electrically connected the first chip 18.
Described multiple first conductive hole 124 is positioned at described first substrate of glass 121 near described sandwich layer circuit substrate 111 side, and each described first conductive hole 124 near described sandwich layer circuit substrate 111 one end, all described first electric connection pad 122 is electrically connected with one, each described first conductive hole 124 is all electrically connected with first conducting wire 125 away from described sandwich layer circuit substrate 111 one end.Described many first conducting wires 125 are positioned at described first substrate of glass 121 away from described sandwich layer circuit substrate 111 side, and away from described sandwich layer circuit substrate 111 one end, all described second electric connection pad 123 is electrically connected with one in the first conducting wire 125 described in every bar.Near described sandwich layer circuit substrate 111 one end, all described first conductive hole 124 is electrically connected away from one end of described sandwich layer circuit substrate 111 with one in first conducting wire 125 described in every bar, to realize each described first electric connection pad 122 all by the electric connection with corresponding described second electric connection pad 123 of first conductive hole 124 and first conducting wire 125.
Described first chip 18 structure is loaded on the side of described first intermediate plate 12 away from described sandwich layer circuit substrate 111.Described first chip 18 has first active surface 181 and the first non-active face 182 relative with described first active surface 181.First active surface 181 side of described first chip 18 also has multiple first electronic pads 183.Each described first electronic pads 183 is all electrically connected by the 3rd conductive member 16 and second electric connection pad 123.Described first chip 18 and being contained in completely in described first perforate 1123 with the first intermediate plate 12 that described first chip 18 is electrically connected.Preferably, in the present embodiment, described first chip 18 is logic chip.Described 3rd conductive member 16 is soldering projection.
Described second intermediate plate 13 is positioned in described second groove 1134, and is electrically connected with described circuit board 11.Described second intermediate plate 13 comprises the second substrate of glass 131 of being formed with multiple second conductive hole 134 and many articles of the second conducting wires 135 and is exposed to described second substrate of glass 131 multiple 3rd electric connection pad 132 of both sides and multiple 4th electric connection pad 133 relatively.Described multiple 3rd electric connection pad 132 is electrically connected with multiple described second electric contact mat 1136 one by one respectively by second conductive member 15.Described second conductive member 15 is metal column or soldered ball.In the present embodiment, described second conductive member 15 is soldered ball.Described multiple 4th electric connection pad 133 is in order to be electrically connected the second chip 19.
Described multiple second conductive hole 134 is positioned at described second substrate of glass 131 near described sandwich layer circuit substrate 111 side, and each described second conductive hole 134 is all electrically connected with the 3rd electric connection pad 132 near described sandwich layer circuit substrate 111 one end, each described second conductive hole 134 is all electrically connected with second conducting wire 135 away from one end of described sandwich layer circuit substrate 111.Described many second conducting wires 135 are positioned at described second substrate of glass 131 away from described sandwich layer circuit substrate 111 side, and described in every article, the second conducting wire 135 is all electrically connected with the 4th electric connection pad 133 away from one end of described sandwich layer circuit substrate 111.Second conducting wire 135 described in every bar is all electrically connected with second conductive hole 134 one end away from described sandwich layer circuit substrate 111 near one end of described sandwich layer circuit substrate 111, to realize described 3rd electric connection pad 132 by the electric connection with corresponding the 4th electric connection pad 133 of second conductive hole 134 and one article of second conducting wire 135.
Described second chip 19 structure is loaded on the side of described second intermediate plate 13 away from described sandwich layer circuit substrate 111.Described second chip 19 has second active surface 191 and the second non-active face 192 relative with described second active surface 191.Second active surface 191 of described second chip 19 also has multiple second electronic pads 193.Each described second electronic pads 193 is all electrically connected by the 4th conductive member 17 and the 4th electric connection pad 133.Described second chip 19 and being contained in completely in described second perforate 1133 with the second intermediate plate 13 that described second chip 19 is electrically connected.Preferably, in the present embodiment, described second chip 19 is memory chip.Described 4th conductive member 17 is soldering projection.
Be understandable that, the structure of IC support plate of the present invention is not limited to the structure described in this example, as long as it comprises the circuit board with groove structure and is positioned in groove be electrically connected the first intermediate plate with described circuit board.In the present embodiment, the 3rd conductive circuit pattern and the 4th conductive circuit pattern are equally also coated with welding resisting layer.
Be understandable that, the structure of semiconductor device of the present invention is not limited to the structure described in the present embodiment, as long as it comprises described IC support plate and the first chip, and described first intermediate plate and being contained in completely in corresponding described first perforate to the first chip of its electric connection.
IC support plate in the present invention utilizes the first intermediate plate as the connection medium of circuit board and external chip.Due to the first intermediate plate, there is the first substrate of glass, and glass can make live width line-spacing (that is: the distance between the width/wire of wire) and be less than 5/5 micron of ultra fine-line, therefore general circuit board is made can to adapt to the live width line-spacing of chip, and the cost of the first intermediate plate is lower, the cost of whole IC support plate is reduced.Semiconductor device in the present invention is contained in described first perforate completely due to the first intermediate plate and with the first chip of its electric connection, makes can accommodate more chip in IC support plate of the same area, thus makes whole semiconductor device thinning.
Refer to Fig. 2, the semiconductor device 200 that the technical program second embodiment provides is roughly the same with the semiconductor device 100 that the technical program first embodiment provides, and its difference is the circuit board 21 of described IC support plate 20.In the present embodiment, described circuit board 21 comprises sandwich layer circuit substrate 211, first laminated circuit substrate 212 and the second laminated circuit substrate 213.Described sandwich layer circuit substrate 211 is different from described sandwich layer circuit substrate 111.
Particularly, described sandwich layer circuit substrate 211 comprises sub-sandwich layer substrate 201 and the 3rd intermediate plate 202.Described sub-sandwich layer substrate 201 is for being formed with the single-sided circuit board of conducting wire, double-sided PCB or multilayer circuit board, and it to comprise at the bottom of the first subbase 2011 and be formed at the first electronic conduction line pattern 2012 and the second electronic conduction line pattern 2013 of 2011 relative both sides at the bottom of described first subbase.In the present embodiment, described sub-sandwich layer substrate 201 is four-layer circuit board, has two-layer conductive circuit pattern in 2011 at the bottom of described first subbase.Be electrically connected between described sub-sandwich layer substrate 201 each layers of conductive circuit pattern.Described sub-sandwich layer substrate 201 also has the collecting through hole 2014 running through described sub-sandwich layer substrate 201 at thickness direction.Described 3rd intermediate plate 202 is embedded in described collecting through hole 2014.Preferably, the shape of described 3rd intermediate plate 202, size and thickness respectively with the shape of described collecting through hole 2014, size and consistency of thickness.
In the present embodiment, described 3rd intermediate plate 202 is for being formed with the glass substrate of conducting wire, and it to comprise at the bottom of the second subbase 2021 and be formed at the 3rd electronic conduction line pattern 2022 and the 4th electronic conduction line pattern 2023 of 2021 relative both sides at the bottom of described second subbase.There is multilayer conductive circuit figure in 2021 at the bottom of described second subbase.Described 3rd electronic conduction line pattern 2022 comprises multiple first electric contact mat 2024, and described 4th electronic conduction line pattern 2023 comprises multiple second electric contact mat 2025.Described 3rd electronic conduction line pattern 2022 and described 4th electronic conduction line pattern 2023 are electrically connected by the conductive hole 2026 at the bottom of described second subbase in 2021.That is, each described first electric contact mat 2024 is all electrically connected by the conductive hole 2026 at the bottom of described second subbase in 2021 and second electric contact mat 2025.At the bottom of described first subbase 2011 and described second subbase at the bottom of 2021 the first substrates 2111 forming described sandwich layer circuit substrate 211.Described first electronic conduction line pattern 2012 and described 3rd electronic conduction line pattern 2022 form the first conductive circuit pattern 2112 of described sandwich layer circuit substrate 211.Whether described first electronic conduction line pattern 2012 can as required, be selected directly to be electrical connected with described 3rd electronic conduction line pattern 2022.Described second electronic conduction line pattern 2013 and the 4th electronic conduction line pattern 2023 form the second conductive circuit pattern 2113.Whether described second electronic conduction line pattern 2013 can be selected directly to be electrically connected with described 4th electronic conduction line pattern 2023 as required.
In the present embodiment, described first laminated circuit substrate 212 is the same with the first laminated circuit substrate 112 described in the first embodiment, is laminated to the first conductive circuit pattern 2112 side of described sandwich layer circuit substrate 211.Described first laminated circuit substrate 212 is for being formed with single-sided circuit board or the multilayer circuit board of conductive circuit pattern, and it comprises the second substrate 2121 and is formed at three conductive circuit pattern 2122 of described second substrate 2121 away from described first conductive circuit pattern 2112 side.In the present embodiment, described first laminated circuit substrate 212 is two-tier circuit plate, has one deck conductive circuit pattern in described second substrate 2121.Described 3rd conductive circuit pattern 2122 is electrically connected with described first electronic conduction line pattern 2012 and described 3rd electronic conduction line pattern 2022 respectively by the conductive hole in described second substrate 2121.Described first laminated circuit substrate 212 has the first perforate 2123 running through described first laminated circuit substrate in a thickness direction.The projection of described first perforate 2123 on described sandwich layer circuit substrate 211 all falls within described 3rd intermediate plate 202.First electric contact mat 2024 described in described first laminated circuit substrate 212 cover part.Described first laminated circuit substrate 212 with the first perforate 2123 coordinates formation first groove 2124 jointly with described 3rd intermediate plate 202.
Described second laminated circuit substrate 213 is laminated to the second conductive circuit pattern 2113 side of described sandwich layer circuit substrate 211.Described second laminated circuit substrate 213 is for being formed with single-sided circuit board or the multilayer circuit board of conductive circuit pattern, and it comprises the 3rd substrate 2131 and is formed at four conductive circuit pattern 2132 of described 3rd substrate 2131 away from described second conductive circuit pattern 2113 side.In the present embodiment, described second laminated circuit substrate 213 is two-tier circuit plate, has one deck conductive circuit pattern in described 3rd substrate 2131.Described 4th conductive circuit pattern 2132 is electrically connected respectively at described second electronic conduction line pattern 2013 and described 4th electronic conduction line pattern 2023 by the conductive hole in described 3rd substrate 231.Described second laminated circuit substrate 213 has the second perforate 2133 running through described second laminated circuit substrate 213 in a thickness direction.The projection of described second perforate 2133 on described sandwich layer circuit substrate 211 all falls within described 3rd intermediate plate 202, to make the second electric contact mat 2025 described in described second laminated circuit substrate 213 cover part.Described second laminated circuit substrate 213 with the second perforate 2133 coordinates formation second groove 2134 jointly with described 3rd intermediate plate 202.
Be understandable that, the structure of IC support plate of the present invention is not limited to the structure described in this example, as long as it comprises and has groove structure and sandwich layer circuit substrate comprises the circuit board of the 3rd intermediate plate and is positioned in groove and is electrically connected the first intermediate plate with described circuit board.In the present embodiment, the 3rd conductive circuit pattern and the 4th conductive circuit pattern are equally also coated with welding resisting layer.
Be understandable that, the structure of semiconductor device of the present invention is not limited to the structure described in the present embodiment, as long as it comprises described IC support plate and the first chip, and described first intermediate plate and being contained in completely in corresponding described first perforate to the first chip of its electric connection.
IC support plate in the present invention utilize there is conductive circuit pattern and the glass substrate of both sides conducting as the connection medium of circuit board and external chip.Because glass substrate can make the circuit that live width line-spacing (that is: the distance between the width/wire of wire) is less than 5/5 micron, therefore general circuit board is made can to adapt to the live width line-spacing of chip, and due to the first intermediate plate cost lower, the cost of whole IC support plate is reduced.In addition, the semiconductor device in the present invention is contained in described perforate completely due to intermediate plate and with the chip of its electric connection, makes can accommodate more chip in IC support plate of the same area, and whole semiconductor device can be made thinning.
Be understandable that, for the person of ordinary skill of the art, other various corresponding change and distortion can be made according to the technical conceive of the technical program, and all these change the protection range that all should belong to the technical program claim with distortion.
Claims (10)
1. an IC support plate, it comprises:
One circuit board, it comprises the sandwich layer circuit substrate being formed with conducting wire and the first laminated circuit substrate being formed with conducting wire, described ground floor volt circuit substrate layer is pressed on described sandwich layer circuit substrate side, described first laminated circuit substrate has the first perforate, described first perforate runs through described first laminated circuit substrate, with sandwich layer circuit substrate described in exposed portion, described sandwich layer circuit substrate has multiple first electric contact mats exposed from described first perforate; And
First intermediate plate, it is contained in described first perforate completely, and be electrically connected with described circuit board, described first intermediate plate comprises first substrate of glass being formed with multiple conductive hole and is exposed to described first substrate of glass relative to multiple first electric connection pad of both sides and multiple second electric connection pad, each described first electric connection pad is all electrically connected by a conductive hole in described first substrate of glass and described second electric connection pad, each described first electric connection pad is all electrical connected by first conductive member and first electric contact mat, described multiple second electric connection pad is in order to be electrically connected external chip.
2. IC support plate as claimed in claim 1; it is characterized in that; described circuit board also comprises the second laminated circuit substrate that is formed with conducting wire; described second layer volt circuit substrate layer is pressed on described sandwich layer circuit substrate away from described first intermediate plate side; described second laminated circuit substrate has the second perforate; described second perforate runs through described second laminated circuit substrate; with exposed portion sandwich layer circuit substrate, described sandwich layer circuit substrate also has multiple second electric contact mats exposed from described second perforate; And
Described IC support plate also comprises second intermediate plate, it is contained in described second perforate completely, and be electrically connected with described circuit board, described second intermediate plate comprises second substrate of glass being formed with multiple conductive hole and is exposed to described second substrate of glass relative to multiple 3rd electric connection pad of both sides and multiple 4th electric connection pad, each described 3rd electric connection pad is all electrically connected by a conductive hole in described second substrate of glass and described 4th electric connection pad, each described 3rd electric connection pad is all electrical connected by second conductive member and second electric contact mat, described multiple 4th electric connection pad is in order to be electrically connected external chip.
3. IC support plate as claimed in claim 1, it is characterized in that, in unit are, the number of described second electric connection pad is many compared with the number of the first electric connection pad described in unit are.
4. IC support plate as claimed in claim 1, it is characterized in that, described sandwich layer circuit substrate comprises sub-sandwich layer substrate and is embedded at the 3rd intermediate plate in described sub-sandwich layer substrate, described sub-sandwich layer substrate has a collecting through hole, described collecting through hole runs through described sub-sandwich layer substrate, described 3rd intermediate plate is embedded in described collecting through hole, and described 3rd intermediate plate is the glass substrate being formed with conducting wire.
5. IC support plate as claimed in claim 4, it is characterized in that, the projection of described first perforate on described sandwich layer circuit substrate all drops on described 3rd intermediate plate.
6. IC support plate as claimed in claim 4, it is characterized in that, described multiple first electric contact mat is formed at described 3rd intermediate plate near described first intermediate plate side.
7. a semiconductor device, it comprises:
IC support plate, it comprises circuit board and the first intermediate plate, described circuit board comprises the sandwich layer circuit substrate being formed with conducting wire and the first laminated circuit substrate being formed with conducting wire, described ground floor volt circuit substrate layer is pressed on described sandwich layer circuit substrate side, described first laminated circuit substrate has the first perforate, described first perforate runs through described first laminated circuit substrate, with sandwich layer circuit substrate described in exposed portion, described sandwich layer circuit substrate has multiple first electric contact mats exposed from described first perforate, described first intermediate plate is positioned in described first perforate, and be electrically connected with described circuit board, described first intermediate plate comprises first substrate of glass being formed with multiple conductive hole and is exposed to described first substrate of glass relative to multiple first electric connection pad of both sides and the second electric connection pad, each described first electric connection pad is all electrically connected by a conductive hole in described first substrate of glass and described second electric connection pad, each described first electric connection pad is all electrical connected by first conductive member and first electric contact mat, and
First chip, its structure is contained in described first intermediate plate away from described sandwich layer circuit substrate side, and described first chip and being contained in completely in described first perforate with the first intermediate plate of its electric connection.
8. semiconductor device as claimed in claim 7, it is characterized in that, described first chip is memory chip.
9. semiconductor device as claimed in claim 7, it is characterized in that, described circuit board also comprises the second laminated circuit substrate that is formed with conducting wire, described second layer volt circuit substrate layer is pressed on described sandwich layer circuit substrate away from described first intermediate plate side, described second laminated circuit substrate has the second perforate, described second perforate runs through described second laminated circuit substrate, with exposed portion sandwich layer circuit substrate, described sandwich layer circuit substrate also has multiple second electric contact mats exposed from described second perforate;
Described IC support plate also comprises the second intermediate plate, described second intermediate plate is positioned in described second perforate, and be electrically connected with described circuit board, described second intermediate plate comprises second substrate of glass being formed with multiple conductive hole and is exposed to described second substrate of glass relative to multiple 3rd electric connection pad of both sides and multiple 4th electric connection pad, each described 3rd electric connection pad is all electrically connected by a conductive hole in described second substrate of glass and described 4th electric connection pad, each described 3rd electric connection pad is all electrical connected by second conductive member and second electric contact mat, and
Described semiconductor device also comprises the second chip, described second chip packaging in described second intermediate plate away from described sandwich layer circuit substrate side and described second chip and being contained in completely in described second perforate with the second intermediate plate of its electric connection.
10. semiconductor device as claimed in claim 9, it is characterized in that, described second chip is logic chip.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310217967.0A CN104218016A (en) | 2013-06-04 | 2013-06-04 | IC (integrated circuit) carrier board and semiconductor device with same |
| TW102120394A TW201513746A (en) | 2013-06-04 | 2013-06-07 | IC substrate and semiconductor devices with the IC substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310217967.0A CN104218016A (en) | 2013-06-04 | 2013-06-04 | IC (integrated circuit) carrier board and semiconductor device with same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104218016A true CN104218016A (en) | 2014-12-17 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310217967.0A Pending CN104218016A (en) | 2013-06-04 | 2013-06-04 | IC (integrated circuit) carrier board and semiconductor device with same |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN104218016A (en) |
| TW (1) | TW201513746A (en) |
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Also Published As
| Publication number | Publication date |
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| TW201513746A (en) | 2015-04-01 |
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