CN110265384B - Packaging structure - Google Patents
Packaging structure Download PDFInfo
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- CN110265384B CN110265384B CN201810201931.6A CN201810201931A CN110265384B CN 110265384 B CN110265384 B CN 110265384B CN 201810201931 A CN201810201931 A CN 201810201931A CN 110265384 B CN110265384 B CN 110265384B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Geometry (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
The invention discloses a packaging structure which comprises a first substrate, a second substrate, a plurality of chips, a plurality of first conductive pieces and a plurality of second conductive pieces. The first substrate is provided with a concave area, and the second substrate is arranged in the concave area and protrudes out of the first substrate. The chip is arranged on the first substrate and the second substrate, so that the second substrate is positioned between the first substrate and the chip. The first conductive member is located between the chip and the first substrate, and the chip is electrically connected to the first substrate through the first conductive member. The second conductive member is located between the plurality of chips and the second substrate, and the chips are electrically connected to the second substrate through the second conductive member. Therefore, the purpose of increasing the signal transmission space of the chip passing through the second substrate under the condition of the same packaging structure area and volume can be achieved, and the length of the circuit is shortened to improve the transmission efficiency.
Description
Technical Field
The present invention relates to a package structure, and more particularly, to a package structure for increasing a signal transmission space of a chip.
Background
In the packaging process today, many methods have been proposed to provide a higher density of the number of indirect points on the chip. For example, a Silicon interposer (Silicon interposer) is interposed between the chip and the substrate, and electrically connected by a through-Silicon via (tsv) technique. However, the silicon interposer has a large volume and thickness, which also causes problems of high cost and complicated process.
Embedded multi-chip interconnection bridging (EMIB) technology utilizes an embedded chip as a bridging structure, but when the chip is connected by a flip chip process, the density of conductive contacts is still limited because the substrate is a flat surface, and thus the density of the contacts cannot be controlled to a greater extent.
Disclosure of Invention
An aspect of the present invention is a package structure, which can increase the signal transmission space of a chip through a second substrate and shorten the line length to improve the transmission efficiency at the same time with the same package structure area and volume.
According to some embodiments of the present invention, a package structure includes a first substrate, a second substrate, a plurality of chips, a plurality of first conductive members and a plurality of second conductive members. The first substrate is provided with a concave area, and the second substrate is arranged in the concave area and protrudes out of the first substrate. The chip is arranged on the first substrate and the second substrate, so that the second substrate is positioned between the first substrate and the chip. The first conductive member is located between the plurality of chips and the first substrate, and the chips are electrically connected with the first substrate through the first conductive member. The second conductive member is located between the plurality of chips and the second substrate, and the chips are electrically connected to the second substrate through the second conductive member.
In some embodiments of the present invention, the height of the first conductive member is greater than the height of the second conductive member.
In some embodiments of the present invention, the package structure further includes a first solder mask layer and a second solder mask layer. The first solder mask layer is at least positioned on the first substrate in the recessed area, and the second solder mask layer is at least positioned on the surface of the second substrate facing the recessed area.
In some embodiments of the present invention, the first solder mask layer has a plurality of first openings, and the second solder mask layer has a plurality of second openings. The package structure further includes a plurality of third conductive members. The third conductive member is electrically connected to the first substrate and the second substrate through the first opening and the second opening.
In some embodiments of the present invention, the chips are located at the same level.
In some embodiments of the present invention, the package structure further includes a filling adhesive layer. The filling adhesive layer surrounds the first conductive member and the second conductive member and covers the first substrate and the second substrate.
In the above embodiments of the present invention, since the first substrate has the recessed region and the second substrate is disposed in the recessed region, the chip, the first substrate and the second substrate can be electrically connected through the first conductive member and the second conductive member, so that the signal transmission space of the chip through the second substrate can be increased under the same package structure area and volume, and the transmission efficiency can be improved by shortening the line length.
Another aspect of the invention is a package structure.
According to some embodiments of the present invention, a package structure includes a first substrate, a plurality of chips, a second substrate, and a plurality of first conductive members. The chips are arranged on the first substrate, are adjacent to each other and commonly have a concave area. The second substrate is disposed in the recessed area and electrically connected to the chip, wherein a surface of the second substrate facing away from the recessed area is substantially flush with a surface of the chip facing away from the first substrate. The first conductive member is located between the chip and the first substrate, and the chip is electrically connected to the first substrate through the first conductive member.
In some embodiments of the present invention, each chip has a conductive via therein that has a circuit structure and an electrical connection to the circuit structure. The package structure further includes a plurality of second conductive members. The second conductive member is located between the chip and the second substrate, and the second substrate is electrically connected to the first substrate through the second conductive member, the conductive through hole, the circuit structure and the first conductive member.
In some embodiments of the present invention, the package structure further includes a filling adhesive layer. The filling adhesive layer surrounds the first conductive member and covers the first substrate.
In some embodiments of the present invention, the chips have a pitch such that the second substrate is exposed from the pitch. The package structure further includes a plurality of third conductive members. The third conductive members are located between the first substrate and the exposed second substrate, and the second substrate is electrically connected to the first substrate through the plurality of third conductive members.
In some embodiments of the present invention, the package structure further includes a filling adhesive layer. The filling adhesive layer surrounds the first conductive members and the third conductive members and covers the first substrate.
In some embodiments of the present invention, the height of the third conductive member is greater than the height of the first conductive member.
In the above embodiments of the present invention, since the adjacent chips commonly have the recessed area, and the recessed area can be located in the inactive area of the back surface of the chip, the second substrate can be disposed in the recessed area to provide additional routing options for the chip, and the signal transmission space of the chip can be increased under the same area and volume of the package structure.
Drawings
Fig. 1A to 1C are cross-sectional views of a package structure according to an embodiment of the invention at different stages in the manufacturing process.
Fig. 1D is a cross-sectional view of a package structure according to another embodiment of the invention.
Fig. 2A is a cross-sectional view of a package structure according to another embodiment of the invention.
Fig. 2B is a cross-sectional view of a package structure according to another embodiment of the invention.
Fig. 3A is a cross-sectional view of a package structure according to another embodiment of the invention.
Fig. 3B is a cross-sectional view of a package structure according to another embodiment of the invention.
Detailed Description
In the following description, numerous implementation details are set forth in order to provide a thorough understanding of the present invention. It should be understood, however, that these implementation details are not to be interpreted as limiting the invention. That is, in some embodiments of the invention, such implementation details are not necessary. In addition, some conventional structures and components are shown in simplified schematic form in the drawings. And the thickness of layers and regions in the drawings may be exaggerated for clarity, and the same reference numerals denote the same elements in the description of the drawings.
Fig. 1A to 1C are cross-sectional views of a package structure 100a at different stages during the manufacturing process according to an embodiment of the invention. Referring to fig. 1A, the first substrate 110 has a recessed region 111 for disposing the second substrate 120. After the second substrate 120 is fixed in the recess region 111 of the first substrate 110, the upper surface of the second substrate 120 is higher than the upper surface of the first substrate 110. That is to say. The second substrate 120 protrudes from the first substrate 110.
The first substrate 110 has a dielectric layer 112, a circuit layer 113 and a conductive via 114. The circuit layer 113 and the conductive via 114 are disposed in the dielectric layer 112. The number of the dielectric layers, the circuit layers and the conductive vias is not limited to the invention. In the present embodiment, the first substrate 110 further has electrical connection pads 115 disposed on the uppermost surface of the dielectric layer 112. The pads 115 may electrically connect to the circuit layer 113 through the conductive vias 114. In the present embodiment, the first substrate 110 further has a solder mask 116. The solder mask 116 is disposed on the upper surface and the lower surface of the first substrate 110 and the surface of the recess region 111. In the present embodiment, the solder mask layer 126 on the upper surface of the first substrate 110 has an opening 117, so that a portion of the electrical connection pad 115 is exposed. During fabrication, the solder mask 116 covering the pads 115 is formed, and then the solder mask 116 is patterned to form the opening 117. The electrical connection pads 115 in the openings 117 may be used to dispose a solder material.
Similarly, the second substrate 120 has a dielectric layer 122, a circuit layer 123 and a conductive via 124. The circuit layer 123 and the conductive via 124 are disposed in the dielectric layer 122. In the present embodiment, the second substrate 120 further has electrical connection pads 125 and a solder mask layer 126 disposed on the dielectric layer 122, and the electrical connection pads 125 can electrically connect the circuit layer 123 through the conductive vias 124. The solder mask layer 126 is disposed on the upper surface and the lower surface of the second substrate 120. In the present embodiment, the solder mask layer 126 on the upper surface of the second substrate 120 has an opening 127, so that a portion of the electrical connection pad 125 is exposed. The pads 125 in the openings 127 may be used to dispose solder material.
In some embodiments, the total thickness of the second substrate 120 is less than 0.1 millimeters. In some embodiments, the depth of the recessed region 111 is between about 30 microns to about 50 microns.
Referring to fig. 1B, the package structure 100a includes a chip 130a, a chip 130B, a first substrate 110, a second substrate 120, a first conductive member 140, and a second conductive member 150. After the second substrate 120 is disposed in the recess region 111 of the first substrate 110, the chips 130a and 130b may be disposed on the first substrate 110 and the second substrate 120. In the present embodiment, the chip 130a has electrical connection pads 135a and 135 c. The pads 135a and 135c face the first substrate 110 and the second substrate 120, respectively, and are electrically connected to a circuit layer (not shown) in the chip 130 a. The chip 130b has electrical connection pads 135b and 135 d. The pads 135b and 135d face the first substrate 110 and the second substrate 120, respectively, and are electrically connected to a circuit layer (not shown) in the chip 130 b. That is, the pads 135c of the chip 130a are located at the side adjacent to the chip 130b, and the pads 135d of the chip 130b are located at the side adjacent to the chip 130 a.
In the present embodiment, the chip 130a has a first conductive member 140 and a second conductive member 150 respectively on the electrical connection pads 135a and 135 c. The chip 130b has a first conductive member 140 and a second conductive member 150 on the pads 135b and 135d, respectively. When the chips 130a and 130b are disposed on the first substrate 110 and the second substrate 120, the first conductive members 140 of the chips 130a and 130b can be electrically connected to the first substrate 110, and the second conductive members 150 of the chips 130a and 130b can be electrically connected to the second substrate 120. In some embodiments, the first conductive member 140 and the second conductive member 150 may be metal bumps. The material of the first conductive member 140 and the second conductive member 150 may be a tin-lead alloy or copper, and the forming method may include electroplating, printing or other methods, which is not limited in the invention.
In the present embodiment, the lower surfaces of the chips 130a and 130b have the passivation layer 136, and the passivation layer 136 has the openings 137 to expose portions of the pads 135a, 135b, 135c, and 135 d. The first conductive member 140 is disposed on the pads 135a, 135b in the opening 137, and the second conductive member 150 is disposed on the pads 135c, 135d in the opening 137. In some embodiments, the pads 135a, 135b, 135c, 135d may have an under-ball metallurgy layer (not shown) disposed thereon.
When the chip 130a and the chip 130b are bonded to the first substrate 110 and the second substrate 120, a reflow process may melt the first conductive member 140 and the second conductive member 150 into solder balls. Therefore, the first conductive member 140 can electrically connect the pads 115 on the first substrate 110 and the pads 135a on the chip 130a, and electrically connect the pads 115 on the first substrate 110 and the pads 135b on the chip 130 b. In addition, the second conductive member 150 can electrically connect the pads 125 on the second substrate 120 and the pads 135c on the chip 130a, and electrically connect the pads 125 on the second substrate 120 and the pads 135d on the chip 130 b.
Referring to fig. 1C, in the present embodiment, after the reflow process is completed, a filling adhesive layer 170 may be formed between the chip 130a, the first substrate 110 and the second substrate 120, and between the chip 130b, the first substrate 110 and the second substrate 120. The filling adhesive layer 170 covers the first substrate 110 and the second substrate 120 and surrounds the first conductive member 140 and the second conductive member 150, so that the electrical connection reliability of the first conductive member 140 and the second conductive member 150 can be increased and short circuit can be avoided. The package structure 100a may be applied to a chip signal integration system. In the present embodiment, the chips 130a and 130b may be in contact with each other or have a spacing therebetween, which is not limited by the requirements of the designer.
Further, in the embodiment, since the second substrate 120 protrudes from the upper surface of the first substrate 110, the vertical distance H1 between the chips 130a, 130b and the second substrate 120 is smaller than the vertical distance H2 between the chips 130a, 130b and the first substrate 110. Therefore, the height of the second conductive member 150 is smaller than the height of the first conductive member 140, so that the chip 130a and the chip 130b are located at the same horizontal plane after being bonded, thereby reducing stress accumulation on the chip surface during the assembly process. In addition, the second conductive members 150 have a smaller height than the first conductive members 140 and a smaller volume than the first conductive members 140, so that the second conductive members 150 may have a smaller distance therebetween. In this way, the density of the second conductive members 150 on the chips 130a and 130b may be greater than the density of the first conductive members 140 on the chips 130a and 130b, so as to increase the signal transmission space of the chips 130a and 130b through the second substrate 120 under the same package structure area and volume, and simultaneously shorten the line length to improve the transmission efficiency.
Fig. 1D is a cross-sectional view of a package structure 100b according to another embodiment of the invention. As shown, the package structure 100b includes a first substrate 110 having a recess region 111, a second substrate 120, a chip 130a, a chip 130b, a first conductive member 140, and a second conductive member 150. The difference from the embodiment of fig. 1C is that: the recessed area 111 of the first substrate 110 of the package structure 100b further has electrical connection pads 115' facing the second substrate 120. The solder mask 116 in the recessed region 111 of the first substrate 110 has openings 117 'to expose portions of the pads 115'. The second substrate 120 of the package structure 100b further has electrical connection pads 125' on the dielectric layer 122 facing the recessed region 111. The solder mask layer 126 of the second substrate 120 facing the recessed region 111 has an opening 127 'to expose a portion of the electrical connection pad 125'. In addition, the third conductive member 160 is located between the electrical pads 115 'and 125', so that the electrical pads 115 'and 125' can be electrically connected and conducted.
In the embodiment, the thickness of the third conductive member 160 makes the upper surface of the second substrate 120 higher than the upper surface of the first substrate 110 after the bonding, so that the distance between the chip 130a, the chip 130b and the second substrate 120 is smaller than the distance between the chip 130a, the chip 130b and the first substrate 110. Therefore, the height of the second conductive member 150 is smaller than the height of the first conductive member 140, and is matched with the height of the third conductive member 160, so that the chip 130a and the chip 130b after being combined are located at the same horizontal plane, thereby reducing the stress accumulation on the chip surface during the assembly process. In the embodiment, the designer may adjust the heights of the first conductive member 140, the second conductive member 150, and the third conductive member 160 to make the chip 130a and the chip 130b located at the same horizontal plane, which is more flexible in design.
In addition, in the embodiment, the electrical connection between the first substrate 110 and the second substrate 120 can further increase the utilization space of the circuit configuration from the chips 130a and 130b to the first substrate 110 and the second substrate 120, thereby achieving the purpose of improving the signal integration capability under the same package structure area and volume.
In some embodiments, the third conductive member 160 may be a metal bump. The material of the third conductive member 160 may be tin-lead alloy or copper, and the forming method may include electroplating, printing or other methods, which is not limited in the invention.
In the following description, further applications of the above embodiments will be explained.
Fig. 2A is a cross-sectional view of a package structure 200a according to another embodiment of the invention. As shown in the figure, the first substrate 210 may have a plurality of recessed regions 211a, 211b, 211c with depths d1, d2, d3, respectively, and d 1-d 2-d 3. The substrates 220a, 220b, 220c have thicknesses t1, t2, t3, respectively, and t2> t3> t 1. The recessed regions 211a, 211b, 211c are used for disposing the substrates 220a, 220b, 220c with different thicknesses, respectively. The substrate 220a connects the two adjacent chips 230a and 230b above it, the substrate 220b connects the two adjacent chips 230b and 230c above it, and the substrate 220c connects the two adjacent chips 230c and 230d above it. By adjusting the heights of the conductive members 240, 250, 260, 270 of the package structure 200a, the chips 230a, 230b, 230c, 230d after being bonded are located on the same horizontal plane, and the smaller conductive member height has a smaller volume, so that the distance between the conductive members can be reduced, thereby increasing the density of the conductive members, achieving the effect of increasing the signal transmission density under the same package structure area and volume, and improving the signal integration capability.
Fig. 2B is a cross-sectional view of a package structure 200B according to another embodiment of the invention. As shown in the figure, in the embodiment, the first substrate 210 may have a plurality of recessed regions 211d, 211e, 211f with depths d4, d5, d6, and d4> d6> d5, respectively. The substrates 220d, 220e, and 220f have thicknesses t4, t5, and t6, respectively, and t4 ═ t5 ═ t 6. The recessed regions 211d, 211e, 211f are used to set the substrates 220d, 220e, 220f with the same thickness, respectively. The substrate 220d connects the two adjacent chips 230a and 230b above it, the substrate 220e connects the two adjacent chips 230b and 230c above it, and the substrate 220f connects the two adjacent chips 230c and 230d above it. By adjusting the heights of the conductive members 240, 250, 260, 270 of the package structure 200b, the chips 230a, 230b, 230c, 230d after being bonded can be located on the same horizontal plane, and the smaller conductive member height has a smaller volume, so that the spacing between the conductive members can be reduced, thereby increasing the density of the conductive members, achieving the effect of increasing the signal transmission density under the same package structure area and volume, and improving the signal integration capability.
Fig. 3A is a cross-sectional view of a package structure 300a according to another embodiment of the invention. In the embodiment, the package structure 300a includes a first substrate 310, a second substrate 320, a chip 330a, a chip 330b, and a first conductive member 340. The first substrate 310 has a dielectric layer 312, a circuit layer 313 and a conductive via 314. The circuit layer 313 and the conductive via 314 are disposed in the dielectric layer 312. The number of the dielectric layers, the circuit layers and the conductive vias is not limited to the invention. In the present embodiment, the first substrate 310 further has electrical connection pads 315 located on the surface of the uppermost dielectric layer 312. The pads 315 may be electrically connected to the circuit layer 313 through the conductive vias 314. In the present embodiment, the first substrate 310 further has a solder mask 316. The solder mask 316 is disposed on the upper surface and the lower surface of the first substrate 310. In the present embodiment, the solder mask 316 has an opening 317 exposing a portion of the pad 315. During fabrication, the solder mask layer 316 covering the pads 315 may be formed first, and then the solder mask layer 316 is patterned to form the openings 317. The pads 315 in the openings 317 may be used to dispose solder material.
In the present embodiment, the side wall of the chip 330a abuts against the side wall of the chip 330 b. The chip 330a has a recessed area 331a, and the chip 330b has a recessed area 331b, so that the recessed areas 331a and 331b form a common recessed area 331 for disposing the second substrate 320. In the present embodiment, the chip 330a has a circuit layer 333a and a conductive via 334, and the chip 330b has a circuit layer 333b and a conductive via 334. The surfaces of the chips 330a and 330b facing the first substrate 310 also have electrical connection pads 335. The surfaces of the chips 330a and 330b facing the first substrate 310 further have a protection layer 336, and the protection layer 336 has an opening 337 thereon to expose a portion of the electrical connection pad 335. In addition, the first conductive member 340 is disposed between the electrical connection pad 335 and the electrical connection pad 315, so that the electrical connection pad 335 is electrically connected to the electrical connection pad 315.
In the present embodiment, the second substrate 320 has a dielectric layer 322, a circuit layer 323, and a conductive via 324. A wiring layer 323 and conductive vias 324 are disposed in the dielectric layer 322. In this embodiment, after the second substrate 320 is disposed in the recessed area 331, the surface of the second substrate facing away from the recessed area 331 is substantially flush with the surfaces of the chips 330a and 330b facing away from the first substrate 310. In addition, the dielectric layer 322 of the second substrate 320 has a second conductive member 350 on the surface facing the chips 330a and 330 b. The second substrate 320 has solder mask layers 326 on the surfaces facing the chips 330a and 330 b. The solder mask layer 326 has an opening 327 thereon to expose a portion of the second conductive member 350. The circuit layer 323 of the second substrate 320 may be electrically connected to the chips 330a and 330b through the second conductive member 350 and the conductive via 324.
In the present embodiment, a glue filling layer 370 is further disposed between the chips 330a and 330b, the first substrate 310 and the second substrate 320. The underfill layer 370 covers the first substrate 310 and the second substrate 320 and surrounds the first conductive member 340, so that the electrical connection reliability of the first conductive member 340 can be increased and short circuit can be avoided.
In the embodiment, the recess area 331 can be located in the inactive area on the back of the chip 330a and the chip 330b, so that the second substrate 320 can be disposed in the recess area 331 to provide additional routing options for the chip 330a and the chip 330b, and can increase the chip signal transmission space under the same package structure area and volume.
In some embodiments, recessed area 331 can be formed by a launder. In some embodiments, conductive vias 334 may be formed by through-silicon-via. In some embodiments, the total thickness of the second substrate 320 is less than 0.1 millimeters. In some embodiments, the first conductive member 340 may be a metal bump. The material of the first conductive member 340 may be a tin-lead alloy or copper, and the forming method may be electroplating or printing.
Fig. 3B is a cross-sectional view of a package structure 300B according to another embodiment of the invention. The package structure 300b includes a first substrate 310, a second substrate 320, a chip 330a, a chip 330b, a first conductive member 340, and a second conductive member 350. The difference from the package structure 300a of fig. 3A is that: the chip 330a and the chip 330b have a distance D therebetween, such that a portion of the second substrate 320 is exposed from the distance D, and the package structure 300b further has a third conductive member 360. The third conductive member 360 is disposed on the second substrate 320 exposed from the space D. In the present embodiment, the dielectric layer 322 of the second substrate 320 further has electrical connection pads 325' and solder masks 326 on the surfaces facing the chips 330a and 330b and facing the space D. The solder mask layer 326 has openings 327 'to expose portions of the pads 325'. In addition, the third conductive member 360 is disposed between the electrical connection pad 325 'and the electrical connection pad 315, so that the electrical connection pad 325' is electrically connected to the electrical connection pad 315. In the present embodiment, the underfill layer 370 is disposed between the chip 330a, the chip 330b and the first substrate 310, and between the second substrate 320 and the first substrate 310 exposed from the distance D. The underfill layer 370 covers the first substrate 310 and the second substrate 320 exposed from the distance D. In addition, the underfill layer 370 surrounds the first conductive member 340 and the third conductive member 360, so that the electrical connection reliability of the first conductive member 340 and the third conductive member 360 can be increased, and short circuit can be avoided.
Further, in the present embodiment, since the second substrate 320 is exposed from the distance D between the chips 330a and 330b, the vertical distance between the chips 330a and 330b and the first substrate 310 is smaller than the vertical distance between the second substrate 320 and the first substrate 310 exposed from the distance D. In the embodiment, in addition to the second substrate 320 being disposed by the recess 331 formed in the inactive areas on the back surfaces of the chips 330a and 330b, the additional routing selection of the chips 330a and 330b is provided, so as to achieve the purpose of increasing the chip information transmission space under the same package structure area and volume, and the utilization space of the circuit configuration from the chips 330a and 330b to the first substrate 310 and the second substrate 320 is provided by the electrical connection between the first substrate 310 and the second substrate 320 through the third conductive member 360, so as to achieve the purpose of improving the signal integration capability under the same package structure area and volume.
Specifically, in some embodiments, the third conductive member 360 may be a metal bump. The material of the third conductive member 360 may be a tin-lead alloy or copper, and the forming method may be electroplating or printing.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.
Claims (6)
1. A package structure, comprising:
a first substrate;
a plurality of chips disposed on the first substrate, the plurality of chips being adjacent to each other and having a recess region in common;
the second substrate is arranged in the sunken area and is electrically connected with the chips, wherein the surface of the second substrate, which is back to the sunken area, is flush with the surfaces of the chips, which are back to the first substrate; and
the first conductive pieces are positioned between the chips and the first substrate, and the chips are electrically connected with the first substrate through the first conductive pieces.
2. The package structure of claim 1, wherein each of the chips has a circuit structure and a conductive via electrically connecting the circuit structure, the package structure further comprising:
and the second conductive pieces are positioned between the chips and the second substrate, and the second substrate is electrically connected with the first substrate through the second conductive pieces, the conductive through holes, the circuit structure and the first conductive pieces.
3. The package structure of claim 1, further comprising:
and the filling adhesive layer surrounds the plurality of first conductive pieces and covers the first substrate.
4. The package structure of claim 1, wherein the plurality of chips have a pitch, the second substrate being exposed from the pitch, the package structure further comprising:
and the third conductive pieces are positioned between the first substrate and the exposed second substrate, and the second substrate is electrically connected with the first substrate through the third conductive pieces.
5. The package structure of claim 4, further comprising:
and the filling adhesive layer surrounds the first conductive pieces and the third conductive pieces and covers the first substrate.
6. The package structure of claim 4, wherein a height of the third conductive elements is greater than a height of the first conductive elements.
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| CN201810201931.6A CN110265384B (en) | 2018-03-12 | 2018-03-12 | Packaging structure |
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| CN201810201931.6A CN110265384B (en) | 2018-03-12 | 2018-03-12 | Packaging structure |
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| CN110265384B true CN110265384B (en) | 2021-07-16 |
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| US11948877B2 (en) * | 2020-03-31 | 2024-04-02 | Qualcomm Incorporated | Hybrid package apparatus and method of fabricating |
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| CN104218016A (en) * | 2013-06-04 | 2014-12-17 | 宏启胜精密电子(秦皇岛)有限公司 | IC (integrated circuit) carrier board and semiconductor device with same |
| CN105762138A (en) * | 2014-12-15 | 2016-07-13 | 财团法人工业技术研究院 | Integrated millimeter wave chip package structure |
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| TW200901409A (en) * | 2007-06-22 | 2009-01-01 | Nan Ya Printed Circuit Board Corp | Packaging substrate with embedded chip and buried heatsink |
| KR101413220B1 (en) * | 2007-10-02 | 2014-06-30 | 삼성전자주식회사 | Semiconductor package having interposer and method for manufacturing semiconductor package |
| KR101815489B1 (en) * | 2014-02-26 | 2018-01-05 | 인텔 코포레이션 | Embedded multi-device bridge with through-bridge conductive via signal connection |
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| CN100470793C (en) * | 2005-03-16 | 2009-03-18 | 索尼株式会社 | Semiconductor device and method of manufacturing semiconductor device |
| CN101038886A (en) * | 2006-03-15 | 2007-09-19 | 日月光半导体制造股份有限公司 | Method for manufacturing substrate of embedded element |
| CN104218016A (en) * | 2013-06-04 | 2014-12-17 | 宏启胜精密电子(秦皇岛)有限公司 | IC (integrated circuit) carrier board and semiconductor device with same |
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