CN104217963A - Method for performing taper slot ion implantation to manufacture super junction of semiconductor device through taper hole drilling - Google Patents
Method for performing taper slot ion implantation to manufacture super junction of semiconductor device through taper hole drilling Download PDFInfo
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- CN104217963A CN104217963A CN201410441096.5A CN201410441096A CN104217963A CN 104217963 A CN104217963 A CN 104217963A CN 201410441096 A CN201410441096 A CN 201410441096A CN 104217963 A CN104217963 A CN 104217963A
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- 238000000034 method Methods 0.000 title claims abstract description 43
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000005468 ion implantation Methods 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title abstract description 7
- 238000005553 drilling Methods 0.000 title abstract 2
- 238000002347 injection Methods 0.000 claims abstract description 30
- 239000007924 injection Substances 0.000 claims abstract description 30
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 17
- 239000010703 silicon Substances 0.000 claims abstract description 17
- 239000012535 impurity Substances 0.000 claims abstract description 14
- 230000000873 masking effect Effects 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 7
- 238000009826 distribution Methods 0.000 claims description 22
- 239000002019 doping agent Substances 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000002513 implantation Methods 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 239000000945 filler Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 5
- 230000008021 deposition Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- High Energy & Nuclear Physics (AREA)
- Toxicology (AREA)
- Manufacturing & Machinery (AREA)
- Health & Medical Sciences (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Ceramic Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The invention discloses a method for performing taper slot ion implantation to manufacture super junction of a semiconductor device through taper hole drilling and belongs to the technical field of the super junction of the semiconductor device with an aim to solve the problem that the super junction cannot be obtained in the prior art. The method includes: firstly, etching a plurality of regularly-distributed taper holes in a silicon slice, directly injecting impurities into the taper holes to have the same filled, and pushing the junction under high temperature to form the super junction with a P column and an N column arranged alternatively, wherein the bottom of each taper hole is flat in shape; in addition, manufacturing covering layers on the bottoms of the taper hole before injection and removing the covering layers after injection; or etching downwards from the bottoms of the taper holes rightly after injection to remove doping layers high in concentration and formed at the bottoms of the taper holes during injection; or deposing masking layers on side walls and the bottoms of the taper hole before injection till the bottoms of the taper holes are horn-shaped, and removing the masking layers after injection; or extending or deposing injection layers on the side walls or the bottoms of the taper holes before injection till the bottoms of the taper holes are horn-shaped, and injecting the impurities into the injection layers during injection.
Description
Technical field
The present invention relates to a kind of method of carrying out boring groove ion implantation making semiconductor device super junction by opening taper hole, there is the feature that element manufacturing is easy, technique simple, manufacturing cost reduces compared with existing straight trough sidewall slope injection method, compared with existing V groove sidewalls orthogonal injection method, while obtaining super junction smoothly, improve the electric current DYNAMIC DISTRIBUTION uniformity of device, belong to super junction-semiconductor device manufacturing technology field.
Background technology
Be widely adopted in power semiconductor device technology field super junction.Its technique effect of described super junction is mainly manifested in the resistivity relation by changing device withstand voltage and device current path, realizes high voltage, low pressure drop.Super junction essential characteristic is being alternately arranged of N-type post and P type post in the drift region of device.The method of the existing making super junction relevant with the present invention is V groove sidewalls orthogonal injection method.As shown in Figure 1, so-called V groove 1 refers to the groove of the V-shaped form of sidewall, the method is injected in the mode of vertical (zero angle), for existing straight trough sidewall slope injection method, because two sidewalls 2 of V groove 1 tilt to intersect, without injecting dead angle, easily, not easily there is filling cavity and gap in extension, deposition, filling; Further, zero angle is once injected and can be completed doping, and technique is simple.Scheme disclosed in the Chinese patent application that application number is CN201010517994 just belongs to a kind of V groove sidewalls orthogonal injection method.But, the program has it not enough, one is be difficult to obtain bottom desirable wedge angle owing to etching V groove 1 on silicon chip, in fact described V trench bottom is without wedge angle flat 3, when on such V groove 1 sidewall 2 surface with without wedge angle after flat 3 superficial growth one deck thin oxide layers 4, with in the mode doping process of high energy ion implantation, as shown in Figure 1, due to described vertical with injection face without flat 3 injection directions of wedge angle, the impurity concentration that the impurity concentration of adulterating is adulterated apparently higher than described sidewall 2, cause charge unbalance, like this in fact cannot obtain super junction effect; Two is that its path of super junction be made up of the parallel V groove 1 of multiple tracks belongs to line path, and current dissipation is bad, device current DYNAMIC DISTRIBUTION lack of homogeneity.
Summary of the invention
In order to make the semiconductor device with super junction of making obtain super junction effect, and this device has good electric current DYNAMIC DISTRIBUTION uniformity, we have invented a kind of method of carrying out boring groove ion implantation making semiconductor device super junction by opening taper hole.
First the method for carrying out boring groove ion implantation making semiconductor device super junction by opening taper hole of the present invention etches the taper hole 5 of some regular distribution on silicon chip, as shown in Fig. 2 ~ Fig. 5, in flat shape bottom taper hole 5, then vertical implanted dopant in taper hole 5, recharge taper hole 5, final high temperature knot, as shown in Figure 6, the super junction that formation P post and N post are alternately arranged; And:
A. inject before bottom taper hole 5 on make cover layer 6, as shown in Figure 7, after injection, remove cover layer 6; Or,
B. etch downwards bottom taper hole 5 immediately after injecting, to remove when injecting the high-concentration dopant layer 7 that formed below bottom taper hole 5, as shown in Figure 8,9; Or,
C. before injecting on taper hole 5 sidewall and bottom deposit masking layer 8, until to make bottom taper hole 5 in tip-angled shape, as shown in Figure 10, to remove masking layer 8 after injection; Or,
D. before injecting on taper hole 5 sidewall and bottom extension or deposit implanted layer 9, until make in tip-angled shape bottom taper hole 5, during injection, impurity is injected into described implanted layer 9, as shown in figure 11.
Its technique effect of the present invention is, compared to prior art, the present invention replaces the V groove 1 of some parallel distributions with the taper hole 5 of some regular distribution, forming surface path is also a kind of network path, compared to line access structure, face access structure uniformity is high, the uniformity of this structure brings the balance of electric charge, and current dissipation is good, and device current DYNAMIC DISTRIBUTION uniformity is improved.In addition, the measure of making cover layer 6 that the present invention takes can prevent taper hole 5 impurities at bottom concentration apparently higher than the generation of taper hole 5 sidewall impurity concentration phenomenon; Downward etching thus the measure of to remove when injecting the high-concentration dopant layer 7 formed below bottom taper hole 5 eliminates the phenomenon of taper hole 5 impurities at bottom concentration apparently higher than taper hole 5 sidewall impurity concentration bottom taper hole 5 immediately after the injection that the present invention takes; The deposit masking layer 8 that the present invention takes and the measure of deposit implanted layer 9 fundamentally prevent taper hole 5 impurities at bottom concentration apparently higher than the generation of taper hole 5 sidewall impurity concentration phenomenon.Described four main measures all can ensure the acquisition of super junction effect.
Taper hole in the present invention and V groove of the prior art all belong to cone groove in broad terms, and the present invention and prior art are all adulterated with vertical injection mode, and therefore, the present invention also belongs to a kind of and bores the method that groove ion implantation makes semiconductor device super junction.
Accompanying drawing explanation
Fig. 1 is the V groove sidewalls orthogonal injection method schematic diagram of existing making super junction.Fig. 2 is the tetrapyamid shape taper hole matts distribution schematic top plan view in the method for the present invention.Fig. 3 is the tetrapyamid shape taper hole isosceles triangle distribution schematic top plan view in the method for the present invention.Fig. 4 is the hexagonal pyramid shape taper hole honeycomb distribution schematic top plan view in the method for the present invention.Fig. 5 is that the method taper hole sidewalls orthogonal of the present invention injects schematic diagram, and this figure is simultaneously as Figure of abstract.Fig. 6 fills and high temperature knot result schematic diagram after the method for the present invention is injected.Fig. 7 be the present invention method inject before bottom taper hole on make cover layer schematic diagram.Fig. 8 be the method for the present invention when injecting bottom taper hole below formation high-concentration dopant layer schematic diagram.Fig. 9 etches downwards after the method for the present invention is injected to remove high-concentration dopant layer schematic diagram immediately bottom taper hole.Figure 10 be before the method for the present invention is injected on taper hole sidewall and bottom deposit masking layer and then inject schematic diagram.Figure 11 be the present invention method inject before on taper hole sidewall and bottom extension or deposit implanted layer then to implanted layer implanted dopant schematic diagram.
Embodiment
The present invention carries out boring groove ion implantation by opening taper hole to make its embodiment of method of semiconductor device super junction as follows.
Example is injected to carry out the doping of P type to N-type silicon taper hole.
Before silicon chip makes super junction, first on silicon chip, make mask 10, obtain the etching window of each taper hole 5 by the distribution scheme photo etched mask 10 of taper hole 5 on silicon chip, as shown in Fig. 2 ~ Fig. 5.
First on silicon chip, the taper hole 5 of some regular distribution is etched, as shown in Fig. 2 ~ Fig. 5.The shape of taper hole 5 comprises two kinds, and one is tetrapyamid shape, and the distribution scheme of the taper hole 5 of this shape is matts distribution or isosceles triangle distribution, as shown in Fig. 2 or Fig. 3; Another kind is hexagonal pyramid shape, and the distribution scheme of the taper hole 5 of this shape is honeycomb, as shown in Figure 4.In flat shape bottom taper hole 5.Taper hole 5 sidewall inclination alpha is: 70 °≤α≤85 °.
Before implanted dopant vertical in taper hole 5, taper hole 5 sidewall and bottom grow one deck thin oxide layer 4, this measure can make the impurity concentration of dopant implant be easy to control, or directly to implanted dopant vertical in taper hole 5.
Then vertical implanted dopant in taper hole 5.Inject in low energy mode, Implantation Energy, lower than 80KeV, higher than 60KeV, when taper hole 5 sidewall inclination alpha increases, then improves Implantation Energy, otherwise then reduces.
Recharge taper hole 5.Filler is insulant, or is one of the polysilicon that undopes, amorphous silicon, epitaxial silicon.
Finally removing high temperature knot after filling in taper hole 5 process the filler be dispersed on silicon chip, formation P post and N post replace the super junction of arrangement.
In the manufacturing process of described semiconductor device super junction, also comprise one of following four kinds of schemes:
A. inject before bottom taper hole 5 on make cover layer 6, as shown in Figure 7, described cover layer 6 is silicon oxide layer or photoresist layer, removes cover layer 6 after injection;
B. etch downwards bottom taper hole 5 immediately after injecting, etching depth is less than or equal to the injection degree of depth, to remove when injecting the high-concentration dopant layer 7 that formed below bottom taper hole 5, as shown in Figure 8, Figure 9;
C. inject before on taper hole 5 sidewall and bottom deposit masking layer 8, described masking layer 8 be silicon oxide layer or photoresist layer, until make bottom taper hole 5 be tip-angled shape, as shown in Figure 10, after injection, remove masking layer 8;
D. inject before on taper hole 5 sidewall and bottom extension or deposit implanted layer 9, described implanted layer 9 is silicon epitaxial layers or one of the polysilicon layer that undopes, amorphous silicon layer for deposit, until make in tip-angled shape bottom taper hole 5, as shown in figure 11, during injection, impurity is injected into described implanted layer 9.
Claims (10)
1. one kind is undertaken boring the method that groove ion implantation makes semiconductor device super junction by opening taper hole, it is characterized in that, first on silicon chip, etch the taper hole (5) of some regular distribution, taper hole (5) bottom is in flat shape, then vertical implanted dopant in taper hole (5), recharge taper hole (5), final high temperature knot, the super junction that formation P post and N post are alternately arranged; And:
A. on taper hole (5) bottom, make cover layer (6) before injecting, after injection, remove cover layer (6); Or,
B. etch downwards from taper hole (5) bottom immediately after injecting, remove the high-concentration dopant layer (7) formed below taper hole (5) bottom when injecting; Or,
C. before injecting on taper hole (5) sidewall and bottom deposit masking layer (8), until make taper hole (5) bottom in tip-angled shape, after injection, remove masking layer (8); Or,
D. before injecting on taper hole (5) sidewall and bottom extension or deposit implanted layer (9), until make taper hole (5) bottom in tip-angled shape, during injection, impurity is injected into described implanted layer (9).
2. method of carrying out boring groove ion implantation making semiconductor device super junction by opening taper hole according to claim 1, it is characterized in that, before silicon chip makes super junction, first on silicon chip, make mask (10), obtain the etching window of each taper hole (5) by the distribution scheme photo etched mask (10) of taper hole (5) on silicon chip.
3. method of carrying out boring groove ion implantation making semiconductor device super junction by opening taper hole according to claim 1, it is characterized in that, the shape of taper hole (5) comprises two kinds, one is tetrapyamid shape, and the distribution scheme of the taper hole (5) of this shape is matts distribution or isosceles triangle distribution; Another kind is hexagonal pyramid shape, and the distribution scheme of the taper hole (5) of this shape is honeycomb.
4. method of carrying out boring groove ion implantation making semiconductor device super junction by opening taper hole according to claim 1, it is characterized in that, taper hole (5) sidewall inclination alpha is: 70 °≤α≤85 °.
5. method of carrying out boring groove ion implantation making semiconductor device super junction by opening taper hole according to claim 1, it is characterized in that, before implanted dopant vertical in taper hole (5), taper hole (5) sidewall and bottom grow one deck thin oxide layer (4), or directly to implanted dopant vertical in taper hole (5).
6. method of carrying out boring groove ion implantation making semiconductor device super junction by opening taper hole according to claim 1, it is characterized in that, inject in low energy mode, Implantation Energy is lower than 80KeV, higher than 60KeV, when taper hole (5) sidewall inclination alpha increases, then improve Implantation Energy, otherwise then reduce.
7. method of carrying out boring groove ion implantation making semiconductor device super junction by opening taper hole according to claim 1, it is characterized in that, the filler of filling taper hole (5) is insulant, or is one of the polysilicon that undopes, amorphous silicon, epitaxial silicon.
8. method of carrying out boring groove ion implantation making semiconductor device super junction by opening taper hole according to claim 1, it is characterized in that, described cover layer (6) is silicon oxide layer or photoresist layer.
9. method of carrying out boring groove ion implantation making semiconductor device super junction by opening taper hole according to claim 1, it is characterized in that, described masking layer (8) is silicon oxide layer or photoresist layer.
10. method of carrying out boring groove ion implantation making semiconductor device super junction by opening taper hole according to claim 1, it is characterized in that, described implanted layer (9) is silicon epitaxial layers or one of the polysilicon layer that undopes, amorphous silicon layer for deposit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410441096.5A CN104217963A (en) | 2014-09-01 | 2014-09-01 | Method for performing taper slot ion implantation to manufacture super junction of semiconductor device through taper hole drilling |
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| CN201410441096.5A CN104217963A (en) | 2014-09-01 | 2014-09-01 | Method for performing taper slot ion implantation to manufacture super junction of semiconductor device through taper hole drilling |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070023827A1 (en) * | 2005-08-01 | 2007-02-01 | Semiconductor Components Industries, Llc. | Semiconductor structure with improved on resistance and breakdown voltage performance |
| US20090079002A1 (en) * | 2007-09-21 | 2009-03-26 | Jaegil Lee | Superjunction Structures for Power Devices and Methods of Manufacture |
| CN102129997A (en) * | 2010-01-18 | 2011-07-20 | 上海华虹Nec电子有限公司 | Method for forming P-type pole in N-type super junction vertical double diffused metal oxide semiconductor (VDMOS) |
| CN102129998A (en) * | 2010-01-18 | 2011-07-20 | 上海华虹Nec电子有限公司 | Method for forming polysilicon P type column in N type super-junction VDMOS (Vertical Double Diffused Metal Oxide Semiconductor) |
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2014
- 2014-09-01 CN CN201410441096.5A patent/CN104217963A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070023827A1 (en) * | 2005-08-01 | 2007-02-01 | Semiconductor Components Industries, Llc. | Semiconductor structure with improved on resistance and breakdown voltage performance |
| US20090079002A1 (en) * | 2007-09-21 | 2009-03-26 | Jaegil Lee | Superjunction Structures for Power Devices and Methods of Manufacture |
| CN102129997A (en) * | 2010-01-18 | 2011-07-20 | 上海华虹Nec电子有限公司 | Method for forming P-type pole in N-type super junction vertical double diffused metal oxide semiconductor (VDMOS) |
| CN102129998A (en) * | 2010-01-18 | 2011-07-20 | 上海华虹Nec电子有限公司 | Method for forming polysilicon P type column in N type super-junction VDMOS (Vertical Double Diffused Metal Oxide Semiconductor) |
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Application publication date: 20141217 |