The formation method of polysilicon P type post in the N type hyperconjugation VDMOS
Technical field
The present invention relates to a kind of semiconductor integrated circuit manufacturing process, particularly relate to the formation method of polysilicon P type post in a kind of N type hyperconjugation VDMOS.
Background technology
The P type and the N type semiconductor thin layer that are distributing in the super node MOSFET and alternately arranging, its electric charge compensates mutually, so when device is in cut-off state, applying low voltage can make thin layer exhaust, thereby make p type island region and N type drift region when adopting higher-doped concentration, can realize high puncture voltage, obtain low on-resistance simultaneously, broken through conventional power MOSFET theoretical limit.Fig. 1 is the structure chart of existing N type hyperconjugation VDMOS, comprised the N type epitaxial loayer that is formed at N type substrate and leaks, be formed at the P type post in the described N type epitaxial loayer, and be formed at the P trap of P type post top and the source region in the P trap, the P trap is as the back of the body grid of device, and the N type epitaxial loayer between P trap and drain terminal is as the drift region of device; One polysilicon gate is formed on described back of the body grid and the drift region and by a gate oxide and does separator.Source region and P type post form ohmic contact and draw source electrode and back grid by Metal Contact by a P type heavily doped region; Grid and drain electrode are directly drawn by a Metal Contact.
Wherein the implementation method of P type post mainly contains two classes, and a kind of is that limit growth N type epitaxial loayer limit is injected the P columnar region, and another kind is that N type outer layer growth finishes the back to P columnar region etching deep trouth and growing P-type epitaxial loayer.But the epitaxial growth cost of this dual mode is higher, and process time is longer, and the controllability of the technological parameter relevant with withstand voltage properties and conducting resistance is poor.
Summary of the invention
Technical problem to be solved by this invention provides the formation method of polysilicon P type post in a kind of N type hyperconjugation VDMOS, can reduce the technology cost, and can realize the high voltage endurance of low on-resistance of device, and the controllability of technological parameter is strong, and is applied widely.
For solving the problems of the technologies described above, the formation method of polysilicon P type post comprises the steps: in the N type hyperconjugation VDMOS provided by the invention
Step 1, form N type drain region and N type silicon epitaxy layer on a N type silicon substrate, the foreign body concentration of described N type epitaxial loayer is 1E14~1E15cm
-3On described N type epitaxial loayer, etch V-type groove or bellmouth, on described N type epitaxial loayer, adopt anisotropic etching to form V-type groove or bellmouth, the opening subtended angle is 15 °~30 °, A/F is 2~5 μ m, separation is 10 μ m, groove depth is than shallow 0~10 μ m of epitaxy layer thickness, and A/F, the degree of depth and the spacing of described V-type groove or bellmouth are adjusted according to different demands.
Step 2, three layers of polysilicon of deposit fill up described V-type groove or bellmouth, after the deposit of wherein said second layer polysilicon, carry out the injection of p type impurity, the impurity that described p type impurity injects is that boron, injection energy are 1000keV~2000keV, and dosage is 1E12~1E13cm
-2, the p type impurity total amount of injecting the described N type epitaxial loayer in back equates with N type total impurities, after described three layers of polysilicon deposit are finished, described substrate surface is ground leveling.
Step 3, to the propelling of annealing of the p type impurity of described injection, form described polysilicon P type post; The temperature that described annealing advances is 800~1000 ℃, and the time is 30 minutes~3 hours.
The Metal Contact of source region, grid and source, leakage and the grid of step 4, the described N type hyperconjugation VDMOS of formation.
The present invention is by inserting polysilicon to the V-type groove or the bellmouth of N type epitaxial loayer, and polysilicon is carried out the injection of p type impurity and high temperature advance and form polysilicon P type post, N type extension can be finished in a deposit, its foreign body concentration is adjustable, and P type post does not need the higher P type epitaxial deposition process of cost, and the condition of p type impurity can be regulated according to application demand, the technology cost is low, modulability is good, has higher cellular density simultaneously, can be used for the manufacturing of the high withstand voltage VDMOS of low on-resistance.
Description of drawings
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments:
Fig. 1 is the structure chart of existing N type hyperconjugation VDMOS;
Fig. 2 is the formation method flow diagram of polysilicon P type post in the N type hyperconjugation VDMOS of the present invention;
Fig. 3-Figure 14 is the structure chart of N type hyperconjugation VDMOS in each step of the present invention.
Embodiment
As shown in Figure 2, the formation method of polysilicon P type post comprises the steps: in the N type hyperconjugation VDMOS that the embodiment of the invention provides
Step 1, as shown in Figure 3 is 1E19~1E20cm at bulk concentration
-3N type silicon substrate on growth one deck lightly doped N type silicon epitaxy layer, the foreign body concentration of described N type silicon epitaxy layer is 1E14~1E15cm
-3, epitaxy layer thickness is determined that by range of application wherein said N type substrate is used as the drain region of device.As shown in Figure 4, the growing silicon oxide mask layer, lithographic definition goes out V-type groove zone, and etching formation is the V-type groove zone of hard mask with described silica.As shown in Figure 5, with described silica is the described N type of hard mask etching silicon epitaxy layer, form the V-type groove, its groove depth, opening size and separation can be regulated according to practical application, the opening subtended angle is 15 °~30 °, A/F is 2~5 μ m, and separation is 10 μ m, and groove depth is than shallow 0~10 μ m of epitaxy layer thickness.As shown in Figure 6, remove described silicon oxide masking film layer; As shown in Figure 7, growth one deck sacrificial oxide layer; As shown in Figure 8, remove described sacrificial oxide layer, repair the defective of deep trouth side epitaxial loayer.
Step 2, as shown in Figure 9, the ground floor undoped polycrystalline silicon of deposit; As shown in figure 10, deposit second layer polysilicon, and carry out the high-energy p type impurity and inject, the impurity that described p type impurity injects is that boron, injection energy are 1000keV~2000keV, dosage is 1E12~1E13cm
-2, on using and designing and decide, the p type impurity total amount of injecting the described N type epitaxial loayer in back equates with N type total impurities.As shown in figure 11, the 3rd layer of undoped polycrystalline silicon of deposit, promptly this layer polysilicon do not need to mix.As shown in figure 12, polysilicon fills up to grind behind the described V-type groove and makes surfacingization.
Step 3, as shown in figure 13, annealing advances, and the p type impurity in the polysilicon is evenly distributed, and forms described polysilicon P type post; The temperature that described annealing advances is 800~1000 ℃, and the time is 30 minutes~3 hours, on using and designing and decide.
Step 4, as shown in figure 14 forms the P trap in described polysilicon P type post, form the source region in the P trap, forms P type heavily doped region in described P trap, and this P type heavily doped region is in order to form the ohmic contact of described P trap and source region electrode.Form the Metal Contact of grid and source, leakage and grid at last, finish the making of the super VDMOS of described N type.
More than by specific embodiment the present invention is had been described in detail, but these are not to be construed as limiting the invention.Under the situation that does not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.