CN104183558A - 混合半导体封装 - Google Patents

混合半导体封装 Download PDF

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Publication number
CN104183558A
CN104183558A CN201410208488.7A CN201410208488A CN104183558A CN 104183558 A CN104183558 A CN 104183558A CN 201410208488 A CN201410208488 A CN 201410208488A CN 104183558 A CN104183558 A CN 104183558A
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China
Prior art keywords
belt
terminal
line
bonding
attached
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Granted
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CN201410208488.7A
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CN104183558B (zh
Inventor
A·科姆波施
B·W·康戴
E·奥雷乔拉
M·瑞尔
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Wofu Semiconductor Co ltd
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Infineon Technologies AG
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Abstract

半导体封装包括衬底、附接到衬底的第一侧的RF半导体裸片、附接到衬底的第一侧的电容器和在衬底的第一侧上的第一端子。半导体封装进一步包括将第一端子连接到RF半导体裸片的输出的铜或铝键合接线或带以及将电容器连接到RF半导体裸片的输出的金键合接线或带。金键合接线或带被设计用于与铜或铝键合接线或带相比在RF半导体裸片的操作期间适应更高的RF焦耳加热。也描述了对应的制造方法。

Description

混合半导体封装
技术领域
本申请涉及半导体封装，并且更具体地涉及具有设计用于不同最大操作温度的键合接线或带的半导体封装。
背景技术
对于RF半导体封装而言，期望高可靠性、低成本的键合接线。这种封装的键合接线通常由金、铝或铜制成。这些键合接线中的一些键合接线用作连接到RF功率器件的输出匹配网络的调谐接线。调谐接线与包括在封装中的用于输入和输出连接的其它键合接线相比经受明显更高的温度。例如，由于RF焦耳加热(即欧姆加热和电阻加热)，因此调谐接线的温度通常超过约150℃到160℃，并且在特定应用中甚至200℃，由此作为在RF频率下通过接线的电流的结果，调谐接线释放热量。
与铝和铜键合接线相比，金键合接线可以适应由RF焦耳加热引起的更高温度，但是金明显更为昂贵。在存在氧的情况下，不受保护的铜键合接线容易氧化。氧化铜的生长与温度和时间有关。因此可以预测RF功率器件的寿命并且满足最低要求。铜调谐接线的关键(最大)温度取决于各种条件，诸如器件电灵敏度、元件、合金、时间和温度，并且通常约为150℃，在该温度以下氧化物生长对于大多数器件有用寿命(例如20年)而言不成问题。铜键合接线可以涂覆有诸如钯之类的抗氧化层，但仍在150℃到160℃以上的温度处长时间段氧化。与铜键合接线相比，铝键合接线对上述温度问题不太敏感，并且具有限制进一步氧化的自钝化氧化物层。然而，与铜和金键合接线相比，铝键合接线具有降低的电传导性和热传导性。熔丝电流也明显更小。
对于RF功率封装而言，以其它方式致力于高键合接线温度。例如，可以增加设计时间，使得可以运行足够的仿真以产生降低的调谐接线温度。集成无源器件可以添加到封装以实现优选匹配，减少与调谐接线进行匹配的需要。可以将产品调低以降低调谐接线内的电流。可以增加键合接线的数目。而且，可以增加键合接线直径。在每种情况中，期望致力于RF功率封装内特定键合接线的加热的更好方式。
发明内容
根据半导体封装的一个实施例，该封装包括衬底、附接到衬底的第一侧的RF半导体裸片、附接到衬底的第一侧的电容器和在衬底的第一侧上的第一端子。该封装进一步包括将第一端子连接到RF半导体裸片的输出的铜或铝键合接线或带以及将电容器连接到RF半导体裸片的输出的金键合接线或带。金键合接线或带被设计用于与铜或铝键合接线或带相比在RF半导体裸片的操作期间适应更大的RF焦耳加热。
根据制造半导体封装的方法的一个实施例，该方法包括：将RF半导体裸片附接到衬底的第一侧；将电容器附接到衬底的第一侧；将第一端子布置在衬底的第一侧上；将第一端子经由铜或铝键合接线或带连接到RF半导体裸片的输出；以及将电容器经由金键合接线或带连接到RF半导体裸片的输出，金键合接线或带被设计用于与铜或铝键合接线或带相比在RF半导体裸片的操作期间适应更大的RF焦耳加热。
根据半导体封装的另一实施例，该封装包括金属衬底、附接到金属衬底的电绝缘部件、具有附接到金属衬底的源极端子以及背离金属衬底的栅极端子和漏极端子的RF半导体裸片、具有附接到金属衬底的第一端子和背离金属衬底的第二端子的输入电容器以及具有附接到金属衬底的第一端子和背离金属衬底的第二端子的输出电容器。该封装进一步包括附接到电绝缘部件的输入端子和附接到电绝缘部件的输出端子。第一组铜或铝键合接线或带将输出端子连接到RF半导体裸片的漏极端子。金键合接线或带将输出电容器的第二端子连接到RF半导体裸片的漏极端子。金键合接线或带被设计为适应RF半导体裸片操作期间比第一组铜或铝键合接线或带更高的RF焦耳加热。第二组铜或铝键合接线或带将输入端子连接到输入电容器的第二端子并且将输入电容器的第二端子连接到RF半导体裸片的栅极端子。
本领域技术人员通过阅读下面的具体描述以及通过查看附图将认识到附加特征和优势。
附图说明
图中的组件不一定按照比例绘制，但强调的是图示本发明的原理。而且，在附图中，类似的参考标号标示对应的部分。在附图中：
图1图示了混合半导体封装的一个实施例的自顶向下平面图；
图2图示了图1的混合半导体封装中包括的示例性RF功率电路的示意图；以及
图3图示了根据实施例的图1的混合半导体封装的部分的侧面透视图。
具体实施方式
根据本文描述的实施例，一种半导体封装包括在封装中包括的晶体管裸片的操作期间期望超过特定温度的键合接线或带。这些键合接线或带由金制成。包括在封装中并且期望保持在较低温度下的其它键合接线或带由除了金之外的材料(诸如铝或铜)制成。这样，设计成在器件操作期间最热的键合接线或带在器件的寿命期间可以应对相对高的操作温度，而不会故障和/或氧化。其余键合接线或带由不太昂贵的材料制成，该材料在器件的寿命期间可以在较低温度可靠地工作。
键合接线通常具有(一般)圆形的截面并且键合带通常具有(一般)矩形的截面。可以采用诸如球键合、锲形键合之类的各种标准键合技术来将键合接线或带附接到半导体封装的端子或衬底。通常，在每个键合接线或带与封装的端子或衬底之间产生金属间界面、键或焊点。一些键合接线/带与键合接线或带的剩余部分相比在包括在封装中的器件的操作期间经受更高温度。例如，一些键合接线或带可以用作RF功率器件的输入或输出匹配网络中的调谐接线。电流在这些键合接线或带中以RF射频流动，将键合接线或带加热到可以超过160℃或甚至200℃或更高的温度。在一些应用中，键合接线/带中的这种RF焦耳加热可以接近或甚至超过300℃。这些键合接线/带主要包括金，例如99.99％的纯Au或Au合金。其余键合接线/带主要包括除了金以外的材料，诸如铝(例如纯Al或Al合金)或铜(例如纯Cu或Cu合金，具有或不具有钝化层，诸如钯)。这样，在降低的成本下，金键合接线/带可以可靠地适应相对高的温度并且其余(非金)键合接线/带可以可靠地适应较低的温度。
图1图示了半导体封装100的一个实施例的自顶向下的平面图，并且图2图示了在封装100中容纳的RF功率电路200的电路示意图。在一个实施例中，半导体封装100是RF功率空腔封装。为容易图示起见，在图1中未示出封装盖。在其它一些实施例中，封装100的内件被包裹在诸如环氧树脂之类的模制化合物中。
在任一情况下，封装100包括诸如金属法兰之类的衬底102和诸如陶瓷窗口之类的电绝缘窗口104，在导电衬底102的情况下该电绝缘窗口附接到衬底102。备选地，衬底102可以电绝缘。晶体管裸片106附接到未由绝缘窗口104覆盖的金属衬底102的内部部分。晶体管裸片106可以包括任意类型的功率晶体管，诸如LDMOS(横向扩散的金属氧化物半导体)、DMOS(双扩散MOS)、SiC或GaN晶体管。在一个实施例中，晶体管裸片106是具有附接到金属衬底102的源极端子(S)的RF半导体裸片。在衬底102由金属制成的情况下，该源极端子可以通过衬底102接地。裸片106的栅极端子(G)和漏极端子(D)背离金属衬底102。在电绝缘衬底102的情况下，晶体管裸片106的所有端子布置在裸片106的与衬底102背离的一侧处。晶体管裸片106的相对侧可以粘合或以其它方式附接到封装100的电绝缘衬底102。
封装100进一步包括输入端子108、输出端子110和附接到电绝缘部件104的DC偏置端子112。在电绝缘衬底102的情况下，可以省略绝缘部件104并且端子108、110、112直接附接到衬底102。DC偏置端子112是可选的，并且在经由输出端子110施加DC偏置的情况下可以从封装100省略DC偏置端子112。
封装100也包括输入匹配网络114，该匹配网络114耦合在封装100的输入端子108与晶体管裸片106的栅极端子(G)之间。输入匹配网络114包括DC阻塞电容器CIN，其具有第一端子116，该第一端子116通过绝缘体120与第二端子118隔开。输入匹配网络114的第一导电分支LIN1将封装100的输入端子108连接到输入电容器CIN的第二端子118。输入匹配网络114的第二导电分支LIN2将输入电容器CIN的第二端子118连接到晶体管裸片106的栅极端子。在其中衬底102由金属制成的情况下，输入电容器CIN的第一端子116例如经由附接到衬底102而耦合到接地节点(GND)。
输出匹配网络122耦合在晶体管裸片106的漏极端子(D)与封装100的输出和DC偏置端子110、112之间。输出匹配网络122包括DC阻塞电容器COUT，该DC阻塞电容器COUT具有第一端子124，该第一端子124通过绝缘体128与第二端子126隔开。输出匹配网络122的第一导电分支LOUT1将晶体管裸片106的漏极端子连接到DC阻塞电容器COUT的第二端子126。输出匹配网络122的第二导电分支LOUT2将DC阻塞电容器COUT的第二端子126连接到封装100的DC偏置端子112。在衬底102由金属制成的情况下，DC阻塞电容器COUT的第一端子124例如经由附接到衬底102而耦合到接地节点(GND)，因而在输出匹配网络122的第一导电分支LOUT1和第二导电分支LOUT2之间提供接地的RF/基带“冷点(cold point)”路径。输出匹配网络122的第三导电分支LOUT3将晶体管裸片106的漏极端子连接到封装100的输出端子110。晶体管裸片106的源极端子(S)耦合到接地节点(GND)。
输入匹配网络114和输出匹配网络122的电容器可以实现为与晶体管裸片106分开的分离组件，或者可以与晶体管集成在同一裸片上。输入匹配网络114和输出匹配网络122可以具有其它配置，如本领域容易知道的那样，并且因此在这点上不给出进一步解释。外部端子和电容器(未示出)可以耦合到封装100的输出端子110，用于耦合到晶体管裸片106的输出。封装100可以包括多于一个的裸片106，例如并联连接的多个裸片106。可以在封装100的DC偏置端子112处施加DC偏置(VDD)，用于确保晶体管裸片106的适当偏置。DC阻塞电容器(未示出)可以从外部耦合到封装100的DC偏置端子112。在一些实施例中，DC偏置端子112经由输出电容器COUT提供“冷”点，即在基带和RF处端接/虚拟接地。
输入匹配网络114和输出匹配网络122的导电分支LIN1、LIN2、LOUT1、LOUT2、LOUT3实现为键合接线或带。在一个实施例中，第一组铜或铝键合接线或带130将封装100的输出端子110连接到晶体管裸片106的输出(例如漏极端子)。参照图2的电路示意图，第一组铜或铝键合接线/带130对应于输出匹配网络122的导电分支LOUT3。在由于互感期望将封装100的输出端子110连接到晶体管裸片106的输出的最外键合接线或带比靠内的键合接线或带更热例如160℃以上的情况下，这些键合接线或带的最外键合接线或带可以为金，而阵列的内部部分中的键合接线或带可以为铜或铝。
金键合接线或带132将封装100的DC偏置端子112(或如果省略DC偏置端子112则是输出端子110)连接到输出电容器COUT的第二端子126并且将输出电容器COUT的第二端子126连接到晶体管裸片106的输出。备选地，该连接的第一部分132’可以通过金键合接线或带提供，该金键合接线或带将输出电容器COUT的第二端子126连接到晶体管裸片106的输出。该连接的第二部分132’’可以通过铜或铝键合接线或带提供，该铜或铝键合接线或带将封装100的DC偏置端子112(或如果省略DC偏置端子112则是输出端子110)连接到输出电容器COUT的第二端子126。
参照图2的电路示意图，金键合接线或带132对应于至少导电分支LOUT1，并且取决于LOUT2利用金、铜或铝键合接线或带实现，也可能对应于输出匹配网络122的导电分支LOUT2。在一种情况下，导电分支LOUT1(图1中的部分132’)利用金键合接线或带实现，并且导电分支LOUT2(图1中的部分132’’)利用铜或铝键合接线或带实现。在另一情况下，两个导电分支LOUT1和LOUT2利用金键合接线或带实现。在任一情况下，与第一组铜或铝键合接线或带130相比，金键合接线或带132被设计用于在晶体管裸片106的操作期间适应更高的RF焦耳加热。
第二组铜或铝键合接线或带134将封装100的输入端子108连接到输入电容器CIN的第二端子118，并且将输入电容器CIN的第二端子118连接到晶体管裸片106的栅极端子(G)。这里使用的术语“金键合接线或带”描述包括主要为金(例如99.99％纯Au或金合金)的键合接线或带。这里使用的术语“铜或铝键合接线或带”描述包括主要为铝(例如纯Al或Al合金)或铜(例如纯Cu或Cu合金，具有或不具有钝化层诸如钯)的键合接线或带。
图3图示了根据一个实施例的半导体封装100的部分的侧面透视图。第一组铜或铝键合接线或带130在第一端部129附接到封装100的输出端子110，并且在第二端部131附接到晶体管裸片106的输出(例如漏极端子)。金键合接线或带132在第一端部133附接到封装100的DC偏置端子112(或如果省略DC偏置端子112则是输出端子110)，在第二端部135附接到晶体管裸片106的输出，并且在第一端部133和第二端部135之间的中间区域137处附接到DC阻塞电容器COUT的第二端子126。在另一实施例中，金键合接线或带132提供该连接的第一部分132’并且仅将晶体管裸片106的输出连接到DC阻塞电容器COUT的第二端子126。铜或铝键合接线或带提供从DC阻塞电容器COUT的第二端子126到封装100的DC偏置端子112(或如果省略DC偏置端子112则是输出端子110)的连接的第二部分132’’。在任一情况下，金键合接线或带132可以扭结，即，在附接到DC阻塞电容器COUT的点与附接到晶体管裸片106的点之间具有紧密卷曲、扭曲或弯曲的区域140。
在附图中将封装100的每个端子108、110、112图示为单个连续的键合条带或焊盘，所有对应的键合接线或带130/132/134附接到该单个连续的键合条带或焊盘。备选地，可以通过多个键合焊盘来实现封装端子108、110、112中的一个或多个。在任一情况下，第一组铜或铝键合接线或带132可以经由一个或多个铝键合焊盘附接到封装100的输出端子110，并且可以经由一个或多个铝或金键合焊盘附接到晶体管裸片106的输出。金键合接线或带132可以经由金键合焊盘附接到封装100的DC偏置端子112(或如果省略DC偏置端子112则是输出端子110)、晶体管裸片106的输出和DC阻塞电容器COUT。在一个实施例中，第一组铜或铝键合接线或带130和金键合接线或带132经由一个或多个共享(公共)键合焊盘附接到晶体管裸片106的输出，该一个或多个共享(公共)键合焊盘在图1和图3中由裸片106的漏极端子(D)表示。在这样的配置下，共享键合焊盘由足以可靠地适应异质材料的键合接线或带的材料制成。例如，该一个或多个共享键合焊盘可以包括Ti、Pt和Au。
通常，金键合接线或带被设计用于在比包括在同一封装中的铝或铜键合接线或带明显更高的温度下工作。在RF功率器件的情况下，金键合接线或带可以用作调谐接线。然而，这里描述的金和铝/铜键合接线或带的实施例可以用于如下的任意应用，在这样的应用中焦耳加热引起键合接线或带中的特定键合接线或带产生比其它键合接线或带更大的热量。通常，铜或铝键合接线或带将半导体封装的端子连接到晶体管裸片的输出(例如漏极端子)。金键合接线或带将电容器连接到晶体管裸片的输出，并且被设计成与铜或铝键合接线或带相比在RF半导体裸片的操作期间适应更大的RF焦耳加热。在一个实施例中，在晶体管裸片的操作期间铜或铝键合接线或带的最大温度低于约150℃到160℃，并且在晶体管裸片的操作期间金键合接线或带的最大温度高于160℃，例如高于200℃或甚至接近或超过300℃。铜或铝键合接线或带可以具有与金键合接线或带相同的截面积。备选地，铜或铝键合接线或带可以具有比金键合接线或带更大的截面积。
为便于描述，使用诸如“下方”、“之下”、“更低”、“上方”、“上面”等之类的空间相对术语来说明一个元件相对于第二元件的定位。除了与图中描绘的方向不同的方向之外，这些术语旨在于涵盖器件的不同方向。此外，也使用诸如“第一”、“第二”等的术语来描述各种元件、区域、部分等并且也并不旨在于进行限定。贯穿整个描述，类似的术语指代类似的元件。
如这里使用的，术语“具有”、“含有”、“包括”、“包含”等是开放式术语，指示所述元件或特征的存在，而并不排除附加的元件或特征。除非上下文另外清楚指出，否则冠词“一个”、“一”和“该”旨在于包括复数以及单数。
考虑到上述变型和应用的范围，应理解到的是，本发明并不由前面的描述限定，也不由附图限定。相反，本发明仅由下面的权利要求和其合法等同方案限定。

Claims (22)

1.一种半导体封装，包括：
衬底；
RF半导体裸片，附接到所述衬底的第一侧；
电容器，附接到所述衬底的所述第一侧；
第一端子，在所述衬底的所述第一侧上；
铜或铝键合接线或带，将所述第一端子连接到所述RF半导体裸片的输出；以及
金键合接线或带，将所述电容器连接到所述RF半导体裸片的所述输出，所述金键合接线或带被设计用于与所述铜或铝键合接线或带相比在所述RF半导体裸片的操作期间适应更高的RF焦耳加热。
2.根据权利要求1所述的半导体封装，其中所述RF半导体裸片为GaN、SiC或LDMOS裸片，其具有附接到所述衬底的所述第一侧的源极端子以及与所述衬底背离的漏极端子和栅极端子，其中所述铜或铝键合接线或带将所述第一端子连接到所述裸片的所述漏极端子，并且其中所述金键合接线或带将所述电容器连接到所述裸片的所述漏极端子。
3.根据权利要求1所述的半导体封装，进一步包括在所述衬底的所述第一侧上的第二端子，其中所述铜或铝键合接线或带在第一端部处附接到所述第一端子并且在第二端部处附接到所述RF半导体裸片的所述输出，以及其中所述金键合接线或带在第一端部处附接到所述第二端子，在第二端部处附接到所述RF半导体裸片的所述输出，并且在所述第一端部和所述第二端部之间的中间区域处附接到所述电容器。
4.根据权利要求1所述的半导体封装，其中所述金键合接线或带在附接到所述电容器的点和附接到所述RF半导体裸片的所述输出的点之间扭结。
5.根据权利要求3所述的半导体封装，其中所述铜或铝键合接线或带经由一个或多个铝键合焊盘附接到所述第一端子并且经由一个或多个铝或金键合焊盘附接到所述RF半导体裸片的所述输出，并且其中所述金键合接线或带经由金键合焊盘附接到所述衬底上的所述第一端子或另一端子、所述RF半导体裸片的所述输出和所述电容器。
6.根据权利要求1所述的半导体封装，其中所述铜或铝键合接线或带和所述金键合接线或带经由一个或多个共享键合焊盘附接到所述RF半导体裸片的所述输出。
7.根据权利要求6所述的半导体封装，其中所述一个或多个共享键合焊盘包括Ti、Pt和Au。
8.根据权利要求1所述的半导体封装，其中所述铜或铝键合接线或带的最大温度在所述RF半导体裸片的操作期间低于160℃，并且其中所述金键合接线或带的最大温度在所述RF半导体裸片的操作期间高于160℃。
9.根据权利要求1所述的半导体封装，其中所述铜或铝键合接线或带具有比所述金键合接线或带更大的截面积。
10.根据权利要求1所述的半导体封装，其中所述半导体封装为空气腔封装。
11.根据权利要求1所述的半导体封装，其中所述金键合接线或带为输出匹配网络的调谐接线。
12.根据权利要求1所述的半导体封装，其中所述金键合接线或带在第一端部处附接到所述第一端子，在第二端部处附接到所述RF半导体裸片的所述输出，并且在所述第一端部和所述第二端部之间的中间区域处附接到所述电容器。
13.根据权利要求1所述的半导体封装，其中所述金键合接线或带将所述RF半导体裸片的所述输出连接到所述电容器，并且附加的铜或铝键合接线或带将所述电容器连接到所述第一端子。
14.根据权利要求1所述的半导体封装，进一步包括附加的金键合接线或带，所述附加的金键合接线或带与所述铜或铝键合接线或带形成阵列，并且也将所述第一端子连接到所述RF半导体裸片的所述输出，所述铜或铝键合接线或带布置在所述阵列的内部部分处，并且所述附加的金键合接线或带布置在所述阵列的外部部分处。
15.一种制造半导体封装的方法，所述方法包括：
将RF半导体裸片附接到衬底的第一侧；
将电容器附接到所述衬底的所述第一侧；
将第一端子布置在所述衬底的所述第一侧上；
经由铜或铝键合接线或带将所述第一端子连接到所述RF半导体裸片的输出；以及
经由金键合接线或带将所述电容器连接到所述RF半导体裸片的所述输出，所述金键合接线或带被设计用于与所述铜或铝键合接线或带相比在所述RF半导体裸片的操作期间适应更高的RF焦耳加热。
16.根据权利要求15所述的方法，其中经由所述金键合接线或带将所述电容器连接到所述RF半导体裸片的所述输出包括：
将所述金键合接线或带的第一端部附接到所述衬底上的所述第一端子或另一端子；
将所述金键合接线或带的第二端部附接到所述RF半导体裸片的所述输出；以及
将所述金键合接线或带的在所述第一端部和所述第二端部之间的中间区域附接到所述电容器。
17.根据权利要求16所述的方法，进一步包括在附接到所述电容器的点和附接到所述RF半导体裸片的所述输出的点之间扭结所述金键合接线或带。
18.根据权利要求15所述的方法，其中经由一个或多个共享键合焊盘将所述铜或铝键合接线或带以及所述金键合接线或带附接到所述RF半导体裸片的所述输出。
19.根据权利要求15所述的方法，其中所述铜或铝键合接线或带的最大温度在所述RF半导体裸片的操作期间低于160℃，并且其中所述金键合接线或带的最大温度在所述RF半导体裸片的操作期间高于160℃。
20.一种半导体封装，包括：
金属衬底；
电绝缘部件，附接到所述金属衬底；
RF半导体裸片，具有附接到所述金属衬底的源极端子以及与所述金属衬底背离的栅极端子和漏极端子；
输入电容器，具有附接到所述金属衬底的第一端子和与所述金属衬底背离的第二端子；
输出电容器，具有附接到所述金属衬底的第一端子和与所述金属衬底背离的第二端子；
输入端子，附接到所述电绝缘部件；
输出端子，附接到所述电绝缘部件；
第一组铜或铝键合接线或带，将所述输出端子连接到所述RF半导体裸片的所述漏极端子；
金键合接线或带，将所述输出电容器的所述第二端子连接到所述RF半导体裸片的所述漏极端子，所述金键合接线或带被设计用于与所述第一组铜或铝键合接线或带相比在所述RF半导体裸片的操作期间适应更高的RF焦耳加热；以及
第二组铜或铝键合接线或带，将所述输入端子连接到所述输入电容器的所述第二端子并且将所述输入电容器的所述第二端子连接到所述RF半导体裸片的所述栅极端子。
21.根据权利要求20所述的半导体封装，进一步包括附接到所述电绝缘部件的DC偏置端子，其中所述金键合接线或带将所述DC偏置端子连接到所述输出电容器的所述第二端子并且将所述输出电容器的所述第二端子连接到所述RF半导体裸片的所述漏极端子。
22.根据权利要求20所述的半导体封装，其中所述金键合接线或带将所述RF半导体裸片的所述漏极端子连接到所述电容器的所述第二端子，并且附加的铜或铝键合接线或带将所述电容器的所述第二端子连接到与所述电绝缘部件附接的所述输出端子或另一端子。
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US9373577B2 (en) 2016-06-21
DE102014019946B3 (de) 2022-02-17
DE102014107084B4 (de) 2019-02-21
US20140346637A1 (en) 2014-11-27
KR20140136896A (ko) 2014-12-01
DE102014107084A1 (de) 2014-11-27

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